source: GPL/trunk/alsa-kernel/pci/cs4281.c@ 121

Last change on this file since 121 was 77, checked in by vladest, 19 years ago

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1/*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <sound/driver.h>
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <sound/core.h>
30#include <sound/control.h>
31#include <sound/pcm.h>
32#include <sound/rawmidi.h>
33#include <sound/ac97_codec.h>
34#include <sound/opl3.h>
35#define SNDRV_GET_ID
36#include <sound/initval.h>
37
38#ifndef LINUX_2_2
39#include <linux/gameport.h>
40#endif
41
42MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
43MODULE_DESCRIPTION("Cirrus Logic CS4281");
44MODULE_LICENSE("GPL");
45MODULE_CLASSES("{sound}");
46MODULE_DEVICES("{{Cirrus Logic,CS4281}}");
47
48static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
51static int dual_codec[SNDRV_CARDS]; /* dual codec */
52
53MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
54MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
55MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
56MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
57MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
58MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
59MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
60MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
61MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
62MODULE_PARM(dual_codec, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
63MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
64MODULE_PARM_SYNTAX(dual_codec, SNDRV_ENABLED ",allows:{{0,3}}");
65
66/*
67 *
68 */
69
70#ifndef PCI_VENDOR_ID_CIRRUS
71#define PCI_VENDOR_ID_CIRRUS 0x1013
72#endif
73#ifndef PCI_DEVICE_ID_CIRRUS_4281
74#define PCI_DEVICE_ID_CIRRUS_4281 0x6005
75#endif
76
77/*
78 * Direct registers
79 */
80
81#define CS4281_BA0_SIZE 0x1000
82#define CS4281_BA1_SIZE 0x10000
83
84/*
85 * BA0 registers
86 */
87#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
88#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
89#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
90#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
91#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
92#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
93#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
94#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
95#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
96#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
97#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
98#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
99#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
100
101#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
102#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
103#define BA0_HICR_IEV (1<<0) /* INTENA Value */
104#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
105
106#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
107/* Use same contants as for BA0_HISR */
108
109#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
110
111#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
112#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
113#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
114#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
115
116#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
117#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
118#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
119#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
120#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
121#define BA0_HDSR_RQ (1<<7) /* Pending Request */
122
123#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
124#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
125#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
126#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
127#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
128#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
129#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
130#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
131#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
132#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
133#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
134#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
135#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
136#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
137#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
138#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
139#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
140#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
141#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
142#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
143#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
144#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
145#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
146#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
147
148#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
149#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
150#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
151#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
152#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
153#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
154#define BA0_DMR_USIGN (1<<19) /* Unsigned */
155#define BA0_DMR_BEND (1<<18) /* Big Endian */
156#define BA0_DMR_MONO (1<<17) /* Mono */
157#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
158#define BA0_DMR_TYPE_DEMAND (0<<6)
159#define BA0_DMR_TYPE_SINGLE (1<<6)
160#define BA0_DMR_TYPE_BLOCK (2<<6)
161#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
162#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
163#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
164#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
165#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
166#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
167
168#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
169#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
170#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
171
172#define BA0_FCR0 0x0180 /* FIFO Control 0 */
173#define BA0_FCR1 0x0184 /* FIFO Control 1 */
174#define BA0_FCR2 0x0188 /* FIFO Control 2 */
175#define BA0_FCR3 0x018c /* FIFO Control 3 */
176
177#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
178#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
179#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
180#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
181#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
182#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
183#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
184
185#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
186#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
187#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
188#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
189
190#define BA0_FCHS 0x020c /* FIFO Channel Status */
191#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
192#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
193#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
194#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
195#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
196#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
197#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
198#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
199
200#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
201#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
202#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
203#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
204
205#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
206#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
207#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
208#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
209#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
210#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
211#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
212#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
213
214#define BA0_PMCS 0x0344 /* Power Management Control/Status */
215#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
216
217#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
218#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
219
220#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
221
222#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
223#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
224#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
225#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
226#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
227#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
228#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
229#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
230#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
231#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
232
233#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
234#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
235#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
236#define BA0_TMS 0x03f8 /* Test Register */
237#define BA0_SSVID 0x03fc /* Subsystem ID register */
238
239#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
240#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
241#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
242#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
243#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
244#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
245#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
246
247#define BA0_FRR 0x0410 /* Feature Reporting Register */
248#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
249
250#define BA0_SERMC 0x0420 /* Serial Port Master Control */
251#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
252#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
253#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
254#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
255#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
256#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
257#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
258#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
259#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
260#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
261#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
262#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
263
264#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
265#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
266#define BA0_SERC1_AC97 (1<<1)
267#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
268
269#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
270#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
271#define BA0_SERC2_AC97 (1<<1)
272#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
273
274#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
275
276#define BA0_ACCTL 0x0460 /* AC'97 Control */
277#define BA0_ACCTL_TC (1<<6) /* Target Codec */
278#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
279#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
280#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
281#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
282
283#define BA0_ACSTS 0x0464 /* AC'97 Status */
284#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
285#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
286
287#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
288#define BA0_ACOSV_SLV(x) (1<<((x)-3))
289
290#define BA0_ACCAD 0x046c /* AC'97 Command Address */
291#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
292
293#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
294#define BA0_ACISV_SLV(x) (1<<((x)-3))
295
296#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
297#define BA0_ACSDA 0x047c /* AC'97 Status Data */
298#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
299#define BA0_JSCTL 0x0484 /* Joystick control */
300#define BA0_JSC1 0x0488 /* Joystick control */
301#define BA0_JSC2 0x048c /* Joystick control */
302#define BA0_JSIO 0x04a0
303
304#define BA0_MIDCR 0x0490 /* MIDI Control */
305#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
306#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
307#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
308#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
309#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
310#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
311
312#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
313
314#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
315#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
316#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
317#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
318#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
319
320#define BA0_MIDWP 0x0498 /* MIDI Write */
321#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
322
323#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
324#define BA0_AODSD1_NDS(x) (1<<((x)-3))
325
326#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
327#define BA0_AODSD2_NDS(x) (1<<((x)-3))
328
329#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
330#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
331#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
332#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
333#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
334#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
335#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
336#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
337#define BA0_FMDP 0x0734 /* FM Data Port */
338#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
339#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
340
341#define BA0_SSPM 0x0740 /* Sound System Power Management */
342#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
343#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
344#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
345#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
346#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
347#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
348
349#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
350#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
351
352#define BA0_SSCR 0x074c /* Sound System Control Register */
353#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
354#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
355#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
356#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
357#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
358#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
359#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
360#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
361#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
362
363#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
364#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
365#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
366#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
367#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
368#define BA0_PASR 0x0768 /* playback sample rate */
369#define BA0_CASR 0x076C /* capture sample rate */
370
371/* Source Slot Numbers - Playback */
372#define SRCSLOT_LEFT_PCM_PLAYBACK 0
373#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
374#define SRCSLOT_PHONE_LINE_1_DAC 2
375#define SRCSLOT_CENTER_PCM_PLAYBACK 3
376#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
377#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
378#define SRCSLOT_LFE_PCM_PLAYBACK 6
379#define SRCSLOT_PHONE_LINE_2_DAC 7
380#define SRCSLOT_HEADSET_DAC 8
381#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
382#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
383
384/* Source Slot Numbers - Capture */
385#define SRCSLOT_LEFT_PCM_RECORD 10
386#define SRCSLOT_RIGHT_PCM_RECORD 11
387#define SRCSLOT_PHONE_LINE_1_ADC 12
388#define SRCSLOT_MIC_ADC 13
389#define SRCSLOT_PHONE_LINE_2_ADC 17
390#define SRCSLOT_HEADSET_ADC 18
391#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
392#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
393#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
394#define SRCSLOT_SECONDARY_MIC_ADC 23
395#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
396#define SRCSLOT_SECONDARY_HEADSET_ADC 28
397
398/* Source Slot Numbers - Others */
399#define SRCSLOT_POWER_DOWN 31
400
401/* MIDI modes */
402#define CS4281_MODE_OUTPUT (1<<0)
403#define CS4281_MODE_INPUT (1<<1)
404
405/* joystick bits */
406/* Bits for JSPT */
407#define JSPT_CAX 0x00000001
408#define JSPT_CAY 0x00000002
409#define JSPT_CBX 0x00000004
410#define JSPT_CBY 0x00000008
411#define JSPT_BA1 0x00000010
412#define JSPT_BA2 0x00000020
413#define JSPT_BB1 0x00000040
414#define JSPT_BB2 0x00000080
415
416/* Bits for JSCTL */
417#define JSCTL_SP_MASK 0x00000003
418#define JSCTL_SP_SLOW 0x00000000
419#define JSCTL_SP_MEDIUM_SLOW 0x00000001
420#define JSCTL_SP_MEDIUM_FAST 0x00000002
421#define JSCTL_SP_FAST 0x00000003
422#define JSCTL_ARE 0x00000004
423
424/* Data register pairs masks */
425#define JSC1_Y1V_MASK 0x0000FFFF
426#define JSC1_X1V_MASK 0xFFFF0000
427#define JSC1_Y1V_SHIFT 0
428#define JSC1_X1V_SHIFT 16
429#define JSC2_Y2V_MASK 0x0000FFFF
430#define JSC2_X2V_MASK 0xFFFF0000
431#define JSC2_Y2V_SHIFT 0
432#define JSC2_X2V_SHIFT 16
433
434/* JS GPIO */
435#define JSIO_DAX 0x00000001
436#define JSIO_DAY 0x00000002
437#define JSIO_DBX 0x00000004
438#define JSIO_DBY 0x00000008
439#define JSIO_AXOE 0x00000010
440#define JSIO_AYOE 0x00000020
441#define JSIO_BXOE 0x00000040
442#define JSIO_BYOE 0x00000080
443
444/*
445 *
446 */
447
448typedef struct snd_cs4281 cs4281_t;
449typedef struct snd_cs4281_dma cs4281_dma_t;
450
451struct snd_cs4281_dma {
452 snd_pcm_substream_t *substream;
453 unsigned int regDBA; /* offset to DBA register */
454 unsigned int regDCA; /* offset to DCA register */
455 unsigned int regDBC; /* offset to DBC register */
456 unsigned int regDCC; /* offset to DCC register */
457 unsigned int regDMR; /* offset to DMR register */
458 unsigned int regDCR; /* offset to DCR register */
459 unsigned int regHDSR; /* offset to HDSR register */
460 unsigned int regFCR; /* offset to FCR register */
461 unsigned int regFSIC; /* offset to FSIC register */
462 unsigned int valDMR; /* DMA mode */
463 unsigned int valDCR; /* DMA command */
464 unsigned int valFCR; /* FIFO control */
465 unsigned int fifo_offset; /* FIFO offset within BA1 */
466 unsigned char left_slot; /* FIFO left slot */
467 unsigned char right_slot; /* FIFO right slot */
468 int frag; /* period number */
469};
470
471#define SUSPEND_REGISTERS 20
472
473struct snd_cs4281 {
474 int irq;
475
476 unsigned long ba0; /* virtual (accessible) address */
477 unsigned long ba1; /* virtual (accessible) address */
478 unsigned long ba0_addr;
479 unsigned long ba1_addr;
480
481 int dual_codec;
482
483 ac97_bus_t *ac97_bus;
484 ac97_t *ac97;
485 ac97_t *ac97_secondary;
486
487 struct pci_dev *pci;
488 snd_card_t *card;
489 snd_pcm_t *pcm;
490 snd_rawmidi_t *rmidi;
491 snd_rawmidi_substream_t *midi_input;
492 snd_rawmidi_substream_t *midi_output;
493
494 cs4281_dma_t dma[4];
495
496 unsigned char src_left_play_slot;
497 unsigned char src_right_play_slot;
498 unsigned char src_left_rec_slot;
499 unsigned char src_right_rec_slot;
500
501 unsigned int spurious_dhtc_irq;
502 unsigned int spurious_dtc_irq;
503
504 spinlock_t reg_lock;
505 unsigned int midcr;
506 unsigned int uartm;
507
508 struct snd_cs4281_gameport *gameport;
509
510#ifdef CONFIG_PM
511 u32 suspend_regs[SUSPEND_REGISTERS];
512#endif
513
514};
515
516static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
517
518static struct pci_device_id snd_cs4281_ids[] = {
519 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
520 { 0, }
521};
522
523MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
524
525/*
526 * constants
527 */
528#define CS4281_FIFO_SIZE 32
529
530/*
531 * common I/O routines
532 */
533
534static void snd_cs4281_delay(unsigned int delay)
535{
536 if (delay > 999) {
537 unsigned long end_time;
538 delay = (delay * HZ) / 1000000;
539 if (delay < 1)
540 delay = 1;
541 end_time = jiffies + delay;
542 do {
543 set_current_state(TASK_UNINTERRUPTIBLE);
544 schedule_timeout(1);
545 } while (time_after_eq(end_time, jiffies));
546 } else {
547 udelay(delay);
548 }
549}
550
551inline static void snd_cs4281_delay_long(void)
552{
553 set_current_state(TASK_UNINTERRUPTIBLE);
554 schedule_timeout(1);
555}
556
557static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
558{
559 writel(val, chip->ba0 + offset);
560}
561
562static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
563{
564 return readl(chip->ba0 + offset);
565}
566
567static void snd_cs4281_ac97_write(ac97_t *ac97,
568 unsigned short reg, unsigned short val)
569{
570 /*
571 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
572 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
573 * 3. Write ACCTL = Control Register = 460h for initiating the write
574 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
575 * 5. if DCV not cleared, break and return error
576 */
577 cs4281_t *chip = ac97->private_data;
578 int count;
579
580 /*
581 * Setup the AC97 control registers on the CS461x to send the
582 * appropriate command to the AC97 to perform the read.
583 * ACCAD = Command Address Register = 46Ch
584 * ACCDA = Command Data Register = 470h
585 * ACCTL = Control Register = 460h
586 * set DCV - will clear when process completed
587 * reset CRW - Write command
588 * set VFRM - valid frame enabled
589 * set ESYN - ASYNC generation enabled
590 * set RSTN - ARST# inactive, AC97 codec not reset
591 */
592 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
593 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
594 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
595 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
596 for (count = 0; count < 2000; count++) {
597 /*
598 * First, we want to wait for a short time.
599 */
600 udelay(10);
601 /*
602 * Now, check to see if the write has completed.
603 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
604 */
605 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
606 return;
607 }
608 }
609 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
610}
611
612static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
613 unsigned short reg)
614{
615 cs4281_t *chip = ac97->private_data;
616 int count;
617 unsigned short result;
618 // FIXME: volatile is necessary in the following due to a bug of
619 // some gcc versions
620 volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
621
622 /*
623 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
624 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
625 * 3. Write ACCTL = Control Register = 460h for initiating the write
626 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
627 * 5. if DCV not cleared, break and return error
628 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
629 */
630
631 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
632
633 /*
634 * Setup the AC97 control registers on the CS461x to send the
635 * appropriate command to the AC97 to perform the read.
636 * ACCAD = Command Address Register = 46Ch
637 * ACCDA = Command Data Register = 470h
638 * ACCTL = Control Register = 460h
639 * set DCV - will clear when process completed
640 * set CRW - Read command
641 * set VFRM - valid frame enabled
642 * set ESYN - ASYNC generation enabled
643 * set RSTN - ARST# inactive, AC97 codec not reset
644 */
645
646 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
647 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
648 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
649 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
650 (ac97_num ? BA0_ACCTL_TC : 0));
651
652
653 /*
654 * Wait for the read to occur.
655 */
656 for (count = 0; count < 500; count++) {
657 /*
658 * First, we want to wait for a short time.
659 */
660 udelay(10);
661 /*
662 * Now, check to see if the read has completed.
663 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
664 */
665 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
666 goto __ok1;
667 }
668
669 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
670 result = 0xffff;
671 goto __end;
672
673__ok1:
674 /*
675 * Wait for the valid status bit to go active.
676 */
677 for (count = 0; count < 100; count++) {
678 /*
679 * Read the AC97 status register.
680 * ACSTS = Status Register = 464h
681 * VSTS - Valid Status
682 */
683 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
684 goto __ok2;
685 udelay(10);
686 }
687
688 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
689 result = 0xffff;
690 goto __end;
691
692__ok2:
693 /*
694 * Read the data returned from the AC97 register.
695 * ACSDA = Status Data Register = 474h
696 */
697 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
698
699__end:
700 return result;
701}
702
703/*
704 * PCM part
705 */
706
707static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
708{
709 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
710 cs4281_t *chip = snd_pcm_substream_chip(substream);
711
712 spin_lock(&chip->reg_lock);
713 switch (cmd) {
714 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
715 dma->valDCR |= BA0_DCR_MSK;
716 dma->valFCR |= BA0_FCR_FEN;
717 break;
718 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
719 dma->valDCR &= ~BA0_DCR_MSK;
720 dma->valFCR &= ~BA0_FCR_FEN;
721 break;
722 case SNDRV_PCM_TRIGGER_START:
723 case SNDRV_PCM_TRIGGER_RESUME:
724 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
725 dma->valDMR |= BA0_DMR_DMA;
726 dma->valDCR &= ~BA0_DCR_MSK;
727 dma->valFCR |= BA0_FCR_FEN;
728 break;
729 case SNDRV_PCM_TRIGGER_STOP:
730 case SNDRV_PCM_TRIGGER_SUSPEND:
731 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
732 dma->valDCR |= BA0_DCR_MSK;
733 dma->valFCR &= ~BA0_FCR_FEN;
734 /* Leave wave playback FIFO enabled for FM */
735 if(dma->regFCR != BA0_FCR0)
736 dma->valFCR &= ~BA0_FCR_FEN;
737 break;
738 default:
739 spin_unlock(&chip->reg_lock);
740 return -EINVAL;
741 }
742 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
743 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
744 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
745 spin_unlock(&chip->reg_lock);
746 return 0;
747}
748
749static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
750{
751 unsigned int val = ~0;
752
753 if (real_rate)
754 *real_rate = rate;
755 /* special "hardcoded" rates */
756 switch (rate) {
757 case 8000: return 5;
758 case 11025: return 4;
759 case 16000: return 3;
760 case 22050: return 2;
761 case 44100: return 1;
762 case 48000: return 0;
763 default:
764 goto __variable;
765 }
766__variable:
767 val = 1536000 / rate;
768 if (real_rate)
769 *real_rate = 1536000 / val;
770 return val;
771}
772
773static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
774{
775 int rec_mono;
776
777 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
778 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
779 if (runtime->channels == 1)
780 dma->valDMR |= BA0_DMR_MONO;
781 if (snd_pcm_format_unsigned(runtime->format) > 0)
782 dma->valDMR |= BA0_DMR_USIGN;
783 if (snd_pcm_format_big_endian(runtime->format) > 0)
784 dma->valDMR |= BA0_DMR_BEND;
785 switch (snd_pcm_format_width(runtime->format)) {
786 case 8: dma->valDMR |= BA0_DMR_SIZE8;
787 if (runtime->channels == 1)
788 dma->valDMR |= BA0_DMR_SWAPC;
789 break;
790 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
791 }
792 dma->frag = 0; /* for workaround */
793 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
794 if (runtime->buffer_size != runtime->period_size)
795 dma->valDCR |= BA0_DCR_HTCIE;
796 /* Initialize DMA */
797 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
798 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
799 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
800 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
801 (chip->src_right_play_slot << 8) |
802 (chip->src_left_rec_slot << 16) |
803 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
804 if (!src)
805 goto __skip_src;
806 if (!capture) {
807 if (dma->left_slot == chip->src_left_play_slot) {
808 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
809 snd_assert(dma->right_slot == chip->src_right_play_slot, );
810 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
811 }
812 } else {
813 if (dma->left_slot == chip->src_left_rec_slot) {
814 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
815 snd_assert(dma->right_slot == chip->src_right_rec_slot, );
816 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
817 }
818 }
819__skip_src:
820 /* Deactivate wave playback FIFO before changing slot assignments */
821 if(dma->regFCR == BA0_FCR0)
822 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
823 /* Initialize FIFO */
824 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
825 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
826 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
827 BA0_FCR_OF(dma->fifo_offset);
828 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
829 /* Activate FIFO again for FM playback */
830 if(dma->regFCR == BA0_FCR0)
831 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
832 /* Clear FIFO Status and Interrupt Control Register */
833 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
834}
835
836static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
837 snd_pcm_hw_params_t * hw_params)
838{
839 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
840}
841
842static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
843{
844 return snd_pcm_lib_free_pages(substream);
845}
846
847static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
848{
849 snd_pcm_runtime_t *runtime = substream->runtime;
850 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
851 cs4281_t *chip = snd_pcm_substream_chip(substream);
852
853 spin_lock_irq(&chip->reg_lock);
854 snd_cs4281_mode(chip, dma, runtime, 0, 1);
855 spin_unlock_irq(&chip->reg_lock);
856 return 0;
857}
858
859static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
860{
861 snd_pcm_runtime_t *runtime = substream->runtime;
862 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
863 cs4281_t *chip = snd_pcm_substream_chip(substream);
864
865 spin_lock_irq(&chip->reg_lock);
866 snd_cs4281_mode(chip, dma, runtime, 1, 1);
867 spin_unlock_irq(&chip->reg_lock);
868 return 0;
869}
870
871static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
872{
873 snd_pcm_runtime_t *runtime = substream->runtime;
874 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
875 cs4281_t *chip = snd_pcm_substream_chip(substream);
876
877 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
878 return runtime->buffer_size -
879 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
880}
881
882static snd_pcm_hardware_t snd_cs4281_playback =
883{
884 /* info: */ (SNDRV_PCM_INFO_MMAP |
885 SNDRV_PCM_INFO_INTERLEAVED |
886 SNDRV_PCM_INFO_MMAP_VALID |
887 SNDRV_PCM_INFO_PAUSE |
888 SNDRV_PCM_INFO_RESUME |
889 SNDRV_PCM_INFO_SYNC_START),
890 /* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
891 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
892 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
893 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
894 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
895 /* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
896 /* rate_min: */ 4000,
897 /* rate_max: */ 48000,
898 /* channels_min: */ 1,
899 /* channels_max: */ 2,
900 /* buffer_bytes_max: */ (512*1024),
901 /* period_bytes_min: */ 64,
902 /* period_bytes_max: */ (512*1024),
903 /* periods_min: */ 1,
904 /* periods_max: */ 2,
905 /* fifo_size: */ CS4281_FIFO_SIZE,
906};
907
908static snd_pcm_hardware_t snd_cs4281_capture =
909{
910 /* info: */ (SNDRV_PCM_INFO_MMAP |
911 SNDRV_PCM_INFO_INTERLEAVED |
912 SNDRV_PCM_INFO_MMAP_VALID |
913 SNDRV_PCM_INFO_PAUSE |
914 SNDRV_PCM_INFO_RESUME |
915 SNDRV_PCM_INFO_SYNC_START),
916 /* formats: */ //SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
917 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
918 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
919 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
920 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
921 /* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
922 /* rate_min: */ 4000,
923 /* rate_max: */ 48000,
924 /* channels_min: */ 1,
925 /* channels_max: */ 2,
926 /* buffer_bytes_max: */ (512*1024),
927 /* period_bytes_min: */ 64,
928 /* period_bytes_max: */ (512*1024),
929 /* periods_min: */ 1,
930 /* periods_max: */ 2,
931 /* fifo_size: */ CS4281_FIFO_SIZE,
932};
933
934static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
935{
936 cs4281_t *chip = snd_pcm_substream_chip(substream);
937 snd_pcm_runtime_t *runtime = substream->runtime;
938 cs4281_dma_t *dma;
939
940 dma = &chip->dma[0];
941 dma->substream = substream;
942 dma->left_slot = 0;
943 dma->right_slot = 1;
944 runtime->private_data = dma;
945 runtime->hw = snd_cs4281_playback;
946 snd_pcm_set_sync(substream);
947 /* should be detected from the AC'97 layer, but it seems
948 that although CS4297A rev B reports 18-bit ADC resolution,
949 samples are 20-bit */
950 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
951 return 0;
952}
953
954static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
955{
956 cs4281_t *chip = snd_pcm_substream_chip(substream);
957 snd_pcm_runtime_t *runtime = substream->runtime;
958 cs4281_dma_t *dma;
959
960 dma = &chip->dma[1];
961 dma->substream = substream;
962 dma->left_slot = 10;
963 dma->right_slot = 11;
964 runtime->private_data = dma;
965 runtime->hw = snd_cs4281_capture;
966 snd_pcm_set_sync(substream);
967 /* should be detected from the AC'97 layer, but it seems
968 that although CS4297A rev B reports 18-bit ADC resolution,
969 samples are 20-bit */
970 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
971 return 0;
972}
973
974static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
975{
976 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
977
978 dma->substream = NULL;
979 return 0;
980}
981
982static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
983{
984 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
985
986 dma->substream = NULL;
987 return 0;
988}
989
990static snd_pcm_ops_t snd_cs4281_playback_ops = {
991 /* .open = */ snd_cs4281_playback_open,
992 /* .close = */ snd_cs4281_playback_close,
993 /* .ioctl = */ snd_pcm_lib_ioctl,
994 /* .hw_params = */ snd_cs4281_hw_params,
995 /* .hw_free = */ snd_cs4281_hw_free,
996 /* .prepare = */ snd_cs4281_playback_prepare,
997 /* .trigger = */ snd_cs4281_trigger,
998 /* .pointer = */ snd_cs4281_pointer,
999 0,0,0,0
1000};
1001
1002static snd_pcm_ops_t snd_cs4281_capture_ops = {
1003 /* .open = */ snd_cs4281_capture_open,
1004 /* .close = */ snd_cs4281_capture_close,
1005 /* .ioctl = */ snd_pcm_lib_ioctl,
1006 /* .hw_params = */ snd_cs4281_hw_params,
1007 /* .hw_free = */ snd_cs4281_hw_free,
1008 /* .prepare = */ snd_cs4281_capture_prepare,
1009 /* .trigger = */ snd_cs4281_trigger,
1010 /* .pointer = */ snd_cs4281_pointer,
1011 0,0,0,0
1012};
1013
1014static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
1015{
1016 cs4281_t *chip = pcm->private_data;
1017 chip->pcm = NULL;
1018 snd_pcm_lib_preallocate_free_for_all(pcm);
1019}
1020
1021static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1022{
1023 snd_pcm_t *pcm;
1024 int err;
1025
1026 if (rpcm)
1027 *rpcm = NULL;
1028 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1029 if (err < 0)
1030 return err;
1031
1032 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1033 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1034
1035 pcm->private_data = chip;
1036 pcm->private_free = snd_cs4281_pcm_free;
1037 pcm->info_flags = 0;
1038 strcpy(pcm->name, "CS4281");
1039 chip->pcm = pcm;
1040
1041 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1042 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1043
1044 if (rpcm)
1045 *rpcm = pcm;
1046 return 0;
1047}
1048
1049/*
1050 * Mixer section
1051 */
1052#define CS_VOL_MASK 0x1f
1053
1054static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1055{
1056 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1057 uinfo->count = 2;
1058 uinfo->value.integer.min = 0;
1059 uinfo->value.integer.max = CS_VOL_MASK;
1060 return 0;
1061}
1062
1063static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1064{
1065 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1066 int regL = (kcontrol->private_value >> 16) & 0xffff;
1067 int regR = kcontrol->private_value & 0xffff;
1068 int volL, volR;
1069
1070 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1071 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1072
1073 ucontrol->value.integer.value[0] = volL;
1074 ucontrol->value.integer.value[1] = volR;
1075 return 0;
1076}
1077
1078static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1079{
1080 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1081 int change = 0;
1082 int regL = (kcontrol->private_value >> 16) & 0xffff;
1083 int regR = kcontrol->private_value & 0xffff;
1084 int volL, volR;
1085
1086 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1087 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1088
1089 if (ucontrol->value.integer.value[0] != volL) {
1090 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1091 snd_cs4281_pokeBA0(chip, regL, volL);
1092 change = 1;
1093 }
1094 if (ucontrol->value.integer.value[0] != volR) {
1095 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1096 snd_cs4281_pokeBA0(chip, regR, volR);
1097 change = 1;
1098 }
1099 return change;
1100}
1101
1102static snd_kcontrol_new_t snd_cs4281_fm_vol =
1103{
1104 /* .iface = */SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
1105 /* .name = */"Synth Playback Volume",0,0,0,
1106 /* .info = */snd_cs4281_info_volume,
1107 /* .get = */snd_cs4281_get_volume,
1108 /* .put = */snd_cs4281_put_volume,
1109 /* .private_value = */((BA0_FMLVC << 16) | BA0_FMRVC),
1110};
1111
1112static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1113{
1114 /* .iface = */SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
1115 /* .name = */"PCM Stream Playback Volume",0,0,0,
1116 /* .info = */snd_cs4281_info_volume,
1117 /* .get = */snd_cs4281_get_volume,
1118 /* .put = */snd_cs4281_put_volume,
1119 /* .private_value = */ ((BA0_PPLVC << 16) | BA0_PPRVC),
1120};
1121
1122static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1123{
1124 cs4281_t *chip = bus->private_data;
1125 chip->ac97_bus = NULL;
1126}
1127
1128
1129static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1130{
1131 cs4281_t *chip = ac97->private_data;
1132 if (ac97->num)
1133 chip->ac97_secondary = NULL;
1134 else
1135 chip->ac97 = NULL;
1136}
1137
1138static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1139{
1140 snd_card_t *card = chip->card;
1141 ac97_template_t ac97;
1142 int err;
1143 static ac97_bus_ops_t ops = {
1144 0,
1145 snd_cs4281_ac97_write,
1146 snd_cs4281_ac97_read,
1147 0,0
1148 };
1149 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1150 return err;
1151
1152 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1153
1154 memset(&ac97, 0, sizeof(ac97));
1155 ac97.private_data = chip;
1156 ac97.private_free = snd_cs4281_mixer_free_ac97;
1157 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1158 return err;
1159 if (chip->dual_codec) {
1160 ac97.num = 1;
1161 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1162 return err;
1163 }
1164 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1165 return err;
1166 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1167 return err;
1168 return 0;
1169}
1170
1171/*
1172 * proc interface
1173 */
1174
1175static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1176 snd_info_buffer_t * buffer)
1177{
1178 cs4281_t *chip = entry->private_data;
1179
1180 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1181 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1182 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1183}
1184
1185static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1186 struct file *file, char __user *buf,
1187 unsigned long count, unsigned long pos)
1188{
1189 long size;
1190 cs4281_t *chip = entry->private_data;
1191
1192 size = count;
1193 if (pos + size > CS4281_BA0_SIZE)
1194 size = (long)CS4281_BA0_SIZE - pos;
1195 if (size > 0) {
1196 if (copy_to_user_fromio(buf, (char*)chip->ba0 + pos, size))
1197 return -EFAULT;
1198 }
1199 return size;
1200}
1201
1202static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1203 struct file *file, char __user *buf,
1204 unsigned long count, unsigned long pos)
1205{
1206 long size;
1207 cs4281_t *chip = entry->private_data;
1208
1209 size = count;
1210 if (pos + size > CS4281_BA1_SIZE)
1211 size = (long)CS4281_BA1_SIZE - pos;
1212 if (size > 0) {
1213 if (copy_to_user_fromio(buf, (char*)chip->ba1 + pos, size))
1214 return -EFAULT;
1215 }
1216 return size;
1217}
1218
1219static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1220 .read = snd_cs4281_BA0_read,
1221};
1222
1223static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1224 .read = snd_cs4281_BA1_read,
1225};
1226
1227static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1228{
1229 snd_info_entry_t *entry;
1230
1231 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1232 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1233 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1234 entry->content = SNDRV_INFO_CONTENT_DATA;
1235 entry->private_data = chip;
1236 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1237 entry->size = CS4281_BA0_SIZE;
1238 }
1239 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1240 entry->content = SNDRV_INFO_CONTENT_DATA;
1241 entry->private_data = chip;
1242 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1243 entry->size = CS4281_BA1_SIZE;
1244 }
1245}
1246
1247/*
1248 * joystick support
1249 */
1250
1251#ifndef LINUX_2_2
1252
1253typedef struct snd_cs4281_gameport {
1254 struct gameport info;
1255 cs4281_t *chip;
1256} cs4281_gameport_t;
1257
1258static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1259{
1260 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1261 cs4281_t *chip;
1262 snd_assert(gp, return);
1263 chip = gp->chip;
1264 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1265}
1266
1267static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1268{
1269 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1270 cs4281_t *chip;
1271 snd_assert(gp, return 0);
1272 chip = gp->chip;
1273 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1274}
1275
1276#ifdef COOKED_MODE
1277static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1278{
1279 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1280 cs4281_t *chip;
1281 unsigned js1, js2, jst;
1282
1283 snd_assert(gp, return 0);
1284 chip = gp->chip;
1285
1286 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1287 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1288 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1289
1290 *buttons = (~jst >> 4) & 0x0F;
1291
1292 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1293 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1294 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1295 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1296
1297 for(jst=0;jst<4;++jst)
1298 if(axes[jst]==0xFFFF) axes[jst] = -1;
1299 return 0;
1300}
1301#endif
1302
1303static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1304{
1305 switch (mode) {
1306#ifdef COOKED_MODE
1307 case GAMEPORT_MODE_COOKED:
1308 return 0;
1309#endif
1310 case GAMEPORT_MODE_RAW:
1311 return 0;
1312 default:
1313 return -1;
1314 }
1315 return 0;
1316}
1317
1318static void __devinit snd_cs4281_gameport(cs4281_t *chip)
1319{
1320 cs4281_gameport_t *gp;
1321 gp = kmalloc(sizeof(*gp), GFP_KERNEL);
1322 if (! gp) {
1323 snd_printk(KERN_ERR "cannot allocate gameport area\n");
1324 return;
1325 }
1326 memset(gp, 0, sizeof(*gp));
1327 gp->info.open = snd_cs4281_gameport_open;
1328 gp->info.read = snd_cs4281_gameport_read;
1329 gp->info.trigger = snd_cs4281_gameport_trigger;
1330#ifdef COOKED_MODE
1331 gp->info.cooked_read = snd_cs4281_gameport_cooked_read;
1332#endif
1333 gp->chip = chip;
1334 chip->gameport = gp;
1335
1336 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1337 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1338 gameport_register_port(&gp->info);
1339}
1340
1341#endif /* !LINUX_2_2 */
1342
1343
1344static int snd_cs4281_free(cs4281_t *chip)
1345{
1346#ifndef LINUX_2_2
1347 if (chip->gameport) {
1348 gameport_unregister_port(&chip->gameport->info);
1349 kfree(chip->gameport);
1350 }
1351#endif
1352 if (chip->irq >= 0)
1353 synchronize_irq(chip->irq);
1354
1355 /* Mask interrupts */
1356 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1357 /* Stop the DLL Clock logic. */
1358 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1359 /* Sound System Power Management - Turn Everything OFF */
1360 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1361 /* PCI interface - D3 state */
1362 pci_set_power_state(chip->pci, 3);
1363
1364 if (chip->irq >= 0)
1365 free_irq(chip->irq, (void *)chip);
1366 if (chip->ba0)
1367 iounmap((void *) chip->ba0);
1368 if (chip->ba1)
1369 iounmap((void *) chip->ba1);
1370 pci_release_regions(chip->pci);
1371 kfree(chip);
1372 return 0;
1373}
1374
1375static int snd_cs4281_dev_free(snd_device_t *device)
1376{
1377 cs4281_t *chip = device->device_data;
1378 return snd_cs4281_free(chip);
1379}
1380
1381static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1382#ifdef CONFIG_PM
1383static int cs4281_suspend(snd_card_t *card, unsigned int state);
1384static int cs4281_resume(snd_card_t *card, unsigned int state);
1385#endif
1386
1387static int __devinit snd_cs4281_create(snd_card_t * card,
1388 struct pci_dev *pci,
1389 cs4281_t ** rchip,
1390 int dual_codec)
1391{
1392 cs4281_t *chip;
1393 unsigned int tmp;
1394 int err;
1395#ifdef TARGET_OS2
1396 static snd_device_ops_t ops = {
1397 snd_cs4281_dev_free,0,0,0
1398 };
1399#else
1400 static snd_device_ops_t ops = {
1401 dev_free: snd_cs4281_dev_free,
1402 };
1403#endif
1404
1405 *rchip = NULL;
1406 if ((err = pci_enable_device(pci)) < 0)
1407 return err;
1408 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1409 if (chip == NULL)
1410 return -ENOMEM;
1411 spin_lock_init(&chip->reg_lock);
1412 chip->card = card;
1413 chip->pci = pci;
1414 chip->irq = -1;
1415 pci_set_master(pci);
1416 if (dual_codec < 0 || dual_codec > 3) {
1417 snd_printk(KERN_ERR "invalid snd_dual_codec option %d\n", dual_codec);
1418 dual_codec = 0;
1419 }
1420 chip->dual_codec = dual_codec;
1421
1422 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1423 kfree(chip);
1424 return err;
1425 }
1426 chip->ba0_addr = pci_resource_start(pci, 0);
1427 chip->ba1_addr = pci_resource_start(pci, 1);
1428 chip->ba0 = (unsigned long) ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1429 chip->ba1 = (unsigned long) ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1430 if (!chip->ba0 || !chip->ba1) {
1431 snd_cs4281_free(chip);
1432 return -ENOMEM;
1433 }
1434
1435 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1436 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1437 snd_cs4281_free(chip);
1438 return -ENOMEM;
1439 }
1440 chip->irq = pci->irq;
1441
1442 tmp = snd_cs4281_chip_init(chip);
1443 if(tmp) {
1444 snd_cs4281_free(chip);
1445 return tmp;
1446 }
1447
1448 snd_cs4281_proc_init(chip);
1449
1450 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1451
1452 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1453 snd_cs4281_free(chip);
1454 return err;
1455 }
1456
1457 *rchip = chip;
1458 return 0;
1459}
1460
1461static int snd_cs4281_chip_init(cs4281_t *chip)
1462{
1463 unsigned int tmp;
1464 unsigned long end_time;
1465 int retry_count = 2;
1466
1467 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1468 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1469 if (tmp & BA0_EPPMC_FPDN)
1470 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1471__retry:
1472 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1473 if (tmp != BA0_CFLR_DEFAULT) {
1474 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1475 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1476 if (tmp != BA0_CFLR_DEFAULT) {
1477 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1478 return -EIO;
1479 }
1480 }
1481
1482 /* Set the 'Configuration Write Protect' register
1483 * to 4281h. Allows vendor-defined configuration
1484 * space between 0e4h and 0ffh to be written. */
1485 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1486
1487 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1488 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1489 return -EIO;
1490 }
1491 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1492 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1493 return -EIO;
1494 }
1495
1496 /* Sound System Power Management */
1497 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1498 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1499 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1500
1501 /* Serial Port Power Management */
1502 /* Blast the clock control register to zero so that the
1503 * PLL starts out in a known state, and blast the master serial
1504 * port control register to zero so that the serial ports also
1505 * start out in a known state. */
1506 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1507 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1508
1509 /* Make ESYN go to zero to turn off
1510 * the Sync pulse on the AC97 link. */
1511 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1512 udelay(50);
1513
1514 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1515 * spec) and then drive it high. This is done for non AC97 modes since
1516 * there might be logic external to the CS4281 that uses the ARST# line
1517 * for a reset. */
1518 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1519 udelay(50);
1520 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1521 snd_cs4281_delay(50000);
1522
1523 if (chip->dual_codec)
1524 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1525
1526 /*
1527 * Set the serial port timing configuration.
1528 */
1529 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1530 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1531 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1532
1533 /*
1534 * Start the DLL Clock logic.
1535 */
1536 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1537 snd_cs4281_delay(50000);
1538 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1539
1540 /*
1541 * Wait for the DLL ready signal from the clock logic.
1542 */
1543 end_time = jiffies + HZ;
1544 do {
1545 /*
1546 * Read the AC97 status register to see if we've seen a CODEC
1547 * signal from the AC97 codec.
1548 */
1549 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1550 goto __ok0;
1551 schedule_timeout_uninterruptible(1);
1552 } while (time_after_eq(end_time, jiffies));
1553
1554 snd_printk(KERN_ERR "DLLRDY not seen\n");
1555 return -EIO;
1556
1557__ok0:
1558
1559 /*
1560 * The first thing we do here is to enable sync generation. As soon
1561 * as we start receiving bit clock, we'll start producing the SYNC
1562 * signal.
1563 */
1564 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1565
1566 /*
1567 * Wait for the codec ready signal from the AC97 codec.
1568 */
1569 end_time = jiffies + HZ;
1570 do {
1571 /*
1572 * Read the AC97 status register to see if we've seen a CODEC
1573 * signal from the AC97 codec.
1574 */
1575 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1576 goto __ok1;
1577 schedule_timeout_uninterruptible(1);
1578 } while (time_after_eq(end_time, jiffies));
1579
1580 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1581 return -EIO;
1582
1583__ok1:
1584 if (chip->dual_codec) {
1585 end_time = jiffies + HZ;
1586 do {
1587 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1588 goto __codec2_ok;
1589 schedule_timeout_uninterruptible(1);
1590 } while (time_after_eq(end_time, jiffies));
1591 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1592 chip->dual_codec = 0;
1593 __codec2_ok: ;
1594 }
1595
1596 /*
1597 * Assert the valid frame signal so that we can start sending commands
1598 * to the AC97 codec.
1599 */
1600
1601 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1602
1603 /*
1604 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1605 * the codec is pumping ADC data across the AC-link.
1606 */
1607 end_time = jiffies + HZ;
1608 do {
1609 /*
1610 * Read the input slot valid register and see if input slots 3
1611 * 4 are valid yet.
1612 */
1613 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1614 goto __ok2;
1615 schedule_timeout_uninterruptible(1);
1616 } while (time_after_eq(end_time, jiffies));
1617
1618 if (--retry_count > 0)
1619 goto __retry;
1620 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1621 return -EIO;
1622
1623__ok2:
1624
1625 /*
1626 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1627 * commense the transfer of digital audio data to the AC97 codec.
1628 */
1629 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1630
1631 /*
1632 * Initialize DMA structures
1633 */
1634 for (tmp = 0; tmp < 4; tmp++) {
1635 cs4281_dma_t *dma = &chip->dma[tmp];
1636 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1637 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1638 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1639 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1640 dma->regDMR = BA0_DMR0 + (tmp * 8);
1641 dma->regDCR = BA0_DCR0 + (tmp * 8);
1642 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1643 dma->regFCR = BA0_FCR0 + (tmp * 4);
1644 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1645 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1646
1647 snd_cs4281_pokeBA0(chip, dma->regFCR,
1648 BA0_FCR_LS(31) |
1649 BA0_FCR_RS(31) |
1650 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1651 BA0_FCR_OF(dma->fifo_offset));
1652 }
1653
1654 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1655 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1656 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1657 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1658
1659 /* Activate wave playback FIFO for FM playback */
1660 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1661 BA0_FCR_RS(1) |
1662 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1663 BA0_FCR_OF(chip->dma[0].fifo_offset);
1664 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1665 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1666 (chip->src_right_play_slot << 8) |
1667 (chip->src_left_rec_slot << 16) |
1668 (chip->src_right_rec_slot << 24));
1669
1670 /* Initialize digital volume */
1671 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1672 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1673
1674 /* Enable IRQs */
1675 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1676 /* Unmask interrupts */
1677 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1678 BA0_HISR_MIDI |
1679 BA0_HISR_DMAI |
1680 BA0_HISR_DMA(0) |
1681 BA0_HISR_DMA(1) |
1682 BA0_HISR_DMA(2) |
1683 BA0_HISR_DMA(3)));
1684 synchronize_irq(chip->irq);
1685
1686 return 0;
1687}
1688
1689/*
1690 * MIDI section
1691 */
1692
1693static void snd_cs4281_midi_reset(cs4281_t *chip)
1694{
1695 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1696 udelay(100);
1697 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1698}
1699
1700static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1701{
1702 cs4281_t *chip = substream->rmidi->private_data;
1703
1704 spin_lock_irq(&chip->reg_lock);
1705 chip->midcr |= BA0_MIDCR_RXE;
1706 chip->midi_output = substream;
1707 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1708 snd_cs4281_midi_reset(chip);
1709 } else {
1710 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1711 }
1712 spin_unlock_irq(&chip->reg_lock);
1713 return 0;
1714}
1715
1716static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1717{
1718 cs4281_t *chip = substream->rmidi->private_data;
1719
1720 spin_lock_irq(&chip->reg_lock);
1721 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1722 chip->midi_input = NULL;
1723 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1724 snd_cs4281_midi_reset(chip);
1725 } else {
1726 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1727 }
1728 chip->uartm &= ~CS4281_MODE_INPUT;
1729 spin_unlock_irq(&chip->reg_lock);
1730 return 0;
1731}
1732
1733static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1734{
1735 cs4281_t *chip = substream->rmidi->private_data;
1736
1737 spin_lock_irq(&chip->reg_lock);
1738 chip->uartm |= CS4281_MODE_OUTPUT;
1739 chip->midcr |= BA0_MIDCR_TXE;
1740 chip->midi_input = substream;
1741 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1742 snd_cs4281_midi_reset(chip);
1743 } else {
1744 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1745 }
1746 spin_unlock_irq(&chip->reg_lock);
1747 return 0;
1748}
1749
1750static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1751{
1752 cs4281_t *chip = substream->rmidi->private_data;
1753
1754 spin_lock_irq(&chip->reg_lock);
1755 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1756 chip->midi_output = NULL;
1757 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1758 snd_cs4281_midi_reset(chip);
1759 } else {
1760 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1761 }
1762 chip->uartm &= ~CS4281_MODE_OUTPUT;
1763 spin_unlock_irq(&chip->reg_lock);
1764 return 0;
1765}
1766
1767static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1768{
1769 unsigned long flags;
1770 cs4281_t *chip = substream->rmidi->private_data;
1771
1772 spin_lock_irqsave(&chip->reg_lock, flags);
1773 if (up) {
1774 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1775 chip->midcr |= BA0_MIDCR_RIE;
1776 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1777 }
1778 } else {
1779 if (chip->midcr & BA0_MIDCR_RIE) {
1780 chip->midcr &= ~BA0_MIDCR_RIE;
1781 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1782 }
1783 }
1784 spin_unlock_irqrestore(&chip->reg_lock, flags);
1785}
1786
1787static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1788{
1789 unsigned long flags;
1790 cs4281_t *chip = substream->rmidi->private_data;
1791 unsigned char byte;
1792
1793 spin_lock_irqsave(&chip->reg_lock, flags);
1794 if (up) {
1795 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1796 chip->midcr |= BA0_MIDCR_TIE;
1797 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1798 while ((chip->midcr & BA0_MIDCR_TIE) &&
1799 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1800 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1801 chip->midcr &= ~BA0_MIDCR_TIE;
1802 } else {
1803 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1804 }
1805 }
1806 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1807 }
1808 } else {
1809 if (chip->midcr & BA0_MIDCR_TIE) {
1810 chip->midcr &= ~BA0_MIDCR_TIE;
1811 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1812 }
1813 }
1814 spin_unlock_irqrestore(&chip->reg_lock, flags);
1815}
1816
1817static struct snd_rawmidi_ops snd_cs4281_midi_output =
1818{
1819 .open = snd_cs4281_midi_output_open,
1820 .close = snd_cs4281_midi_output_close,
1821 .trigger = snd_cs4281_midi_output_trigger,
1822};
1823
1824static struct snd_rawmidi_ops snd_cs4281_midi_input =
1825{
1826 .open = snd_cs4281_midi_input_open,
1827 .close = snd_cs4281_midi_input_close,
1828 .trigger = snd_cs4281_midi_input_trigger,
1829};
1830
1831static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1832{
1833 snd_rawmidi_t *rmidi;
1834 int err;
1835
1836 if (rrawmidi)
1837 *rrawmidi = NULL;
1838 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1839 return err;
1840 strcpy(rmidi->name, "CS4281");
1841 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1842 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1843 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1844 rmidi->private_data = chip;
1845 chip->rmidi = rmidi;
1846 if (rrawmidi)
1847 *rrawmidi = rmidi;
1848 return 0;
1849}
1850
1851/*
1852 * Interrupt handler
1853 */
1854
1855static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1856{
1857 cs4281_t *chip = dev_id;
1858 unsigned int status, dma, val;
1859 cs4281_dma_t *cdma;
1860
1861 if (chip == NULL)
1862 return IRQ_NONE;
1863 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1864 if ((status & 0x7fffffff) == 0) {
1865 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1866 return IRQ_NONE;
1867 }
1868
1869 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1870 for (dma = 0; dma < 4; dma++)
1871 if (status & BA0_HISR_DMA(dma)) {
1872 cdma = &chip->dma[dma];
1873 spin_lock(&chip->reg_lock);
1874 /* ack DMA IRQ */
1875 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1876 /* workaround, sometimes CS4281 acknowledges */
1877 /* end or middle transfer position twice */
1878 cdma->frag++;
1879 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1880 cdma->frag--;
1881 chip->spurious_dhtc_irq++;
1882 spin_unlock(&chip->reg_lock);
1883 continue;
1884 }
1885 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1886 cdma->frag--;
1887 chip->spurious_dtc_irq++;
1888 spin_unlock(&chip->reg_lock);
1889 continue;
1890 }
1891 spin_unlock(&chip->reg_lock);
1892 snd_pcm_period_elapsed(cdma->substream);
1893 }
1894 }
1895
1896 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1897 unsigned char c;
1898
1899 spin_lock(&chip->reg_lock);
1900 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1901 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1902 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1903 continue;
1904 spin_unlock(&chip->reg_lock);
1905 snd_rawmidi_receive(chip->midi_input, &c, 1);
1906 spin_lock(&chip->reg_lock);
1907 }
1908 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1909 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1910 break;
1911 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1912 chip->midcr &= ~BA0_MIDCR_TIE;
1913 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1914 break;
1915 }
1916 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1917 }
1918 spin_unlock(&chip->reg_lock);
1919 }
1920
1921 /* EOI to the PCI part... reenables interrupts */
1922 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1923 return IRQ_HANDLED;
1924
1925}
1926
1927/*
1928 * OPL3 command
1929 */
1930static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
1931{
1932 unsigned long flags;
1933 cs4281_t *chip = opl3->private_data;
1934 void __iomem *port;
1935
1936 if (cmd & OPL3_RIGHT)
1937 port = (unsigned long)chip->ba0 + BA0_B1AP; /* right port */
1938 else
1939 port = (unsigned long)chip->ba0 + BA0_B0AP; /* left port */
1940
1941 spin_lock_irqsave(&opl3->reg_lock, flags);
1942
1943 writel((unsigned int)cmd, port);
1944 udelay(10);
1945
1946 writel((unsigned int)val, (unsigned long)port + 4);
1947 udelay(30);
1948
1949 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1950}
1951
1952static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1953 const struct pci_device_id *pci_id)
1954{
1955 static int dev;
1956 snd_card_t *card;
1957 cs4281_t *chip;
1958 opl3_t *opl3;
1959 int err;
1960
1961 if (dev >= SNDRV_CARDS)
1962 return -ENODEV;
1963 if (!enable[dev]) {
1964 dev++;
1965 return -ENOENT;
1966 }
1967
1968 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1969 if (card == NULL)
1970 return -ENOMEM;
1971
1972 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1973 snd_card_free(card);
1974 return err;
1975 }
1976
1977 if ((err = snd_cs4281_mixer(chip)) < 0) {
1978 snd_card_free(card);
1979 return err;
1980 }
1981 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1982 snd_card_free(card);
1983 return err;
1984 }
1985 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1986 snd_card_free(card);
1987 return err;
1988 }
1989 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1990 snd_card_free(card);
1991 return err;
1992 }
1993 opl3->private_data = chip;
1994 opl3->command = snd_cs4281_opl3_command;
1995 snd_opl3_init(opl3);
1996
1997 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1998 snd_card_free(card);
1999 return err;
2000 }
2001#ifndef LINUX_2_2
2002 snd_cs4281_gameport(chip);
2003#endif
2004 strcpy(card->driver, "CS4281");
2005 strcpy(card->shortname, "Cirrus Logic CS4281");
2006 sprintf(card->longname, "%s at 0x%lx, irq %d",
2007 card->shortname,
2008 chip->ba0_addr,
2009 chip->irq);
2010
2011 if ((err = snd_card_register(card)) < 0) {
2012 snd_card_free(card);
2013 return err;
2014 }
2015
2016 pci_set_drvdata(pci, card);
2017 dev++;
2018 return 0;
2019}
2020
2021static void __devexit snd_cs4281_remove(struct pci_dev *pci)
2022{
2023 snd_card_free(pci_get_drvdata(pci));
2024 pci_set_drvdata(pci, NULL);
2025}
2026
2027/*
2028 * Power Management
2029 */
2030#ifdef CONFIG_PM
2031
2032static int saved_regs[SUSPEND_REGISTERS] = {
2033 BA0_JSCTL,
2034 BA0_GPIOR,
2035 BA0_SSCR,
2036 BA0_MIDCR,
2037 BA0_SRCSA,
2038 BA0_PASR,
2039 BA0_CASR,
2040 BA0_DACSR,
2041 BA0_ADCSR,
2042 BA0_FMLVC,
2043 BA0_FMRVC,
2044 BA0_PPLVC,
2045 BA0_PPRVC,
2046};
2047
2048#define number_of(array) (sizeof(array) / sizeof(array[0]))
2049
2050#define CLKCR1_CKRA 0x00010000L
2051
2052static int cs4281_suspend(snd_card_t *card, unsigned int state)
2053{
2054 cs4281_t *chip = card->pm_private_data;
2055 u32 ulCLK;
2056 unsigned int i;
2057
2058 snd_pcm_suspend_all(chip->pcm);
2059
2060 if (chip->ac97)
2061 snd_ac97_suspend(chip->ac97);
2062 if (chip->ac97_secondary)
2063 snd_ac97_suspend(chip->ac97_secondary);
2064
2065 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2066 ulCLK |= CLKCR1_CKRA;
2067 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2068
2069 /* Disable interrupts. */
2070 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2071
2072 /* remember the status registers */
2073 for (i = 0; i < number_of(saved_regs); i++)
2074 if (saved_regs[i])
2075 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2076
2077 /* Turn off the serial ports. */
2078 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2079
2080 /* Power off FM, Joystick, AC link, */
2081 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2082
2083 /* DLL off. */
2084 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2085
2086 /* AC link off. */
2087 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2088
2089 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2090 ulCLK &= ~CLKCR1_CKRA;
2091 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2092
2093 return 0;
2094}
2095
2096static int cs4281_resume(snd_card_t *card, unsigned int state)
2097{
2098 cs4281_t *chip = card->pm_private_data;
2099 unsigned int i;
2100 u32 ulCLK;
2101
2102 pci_enable_device(chip->pci);
2103
2104 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2105 ulCLK |= CLKCR1_CKRA;
2106 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2107
2108 snd_cs4281_chip_init(chip);
2109
2110 /* restore the status registers */
2111 for (i = 0; i < number_of(saved_regs); i++)
2112 if (saved_regs[i])
2113 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2114
2115 if (chip->ac97)
2116 snd_ac97_resume(chip->ac97);
2117 if (chip->ac97_secondary)
2118 snd_ac97_resume(chip->ac97_secondary);
2119
2120 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2121 ulCLK &= ~CLKCR1_CKRA;
2122 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2123
2124 return 0;
2125}
2126
2127
2128#endif /* CONFIG_PM */
2129
2130static struct pci_driver driver = {
2131 0, 0,0,
2132 "CS4281",
2133 snd_cs4281_ids,
2134 snd_cs4281_probe,
2135 snd_cs4281_remove,
2136 SND_PCI_PM_CALLBACKS
2137};
2138
2139static int __init alsa_card_cs4281_init(void)
2140{
2141 int err;
2142
2143 if ((err = pci_module_init(&driver)) < 0) {
2144#ifdef MODULE
2145 // printk(KERN_ERR "CS4281 soundcard not found or device busy\n");
2146#endif
2147 return err;
2148 }
2149 return 0;
2150}
2151
2152static void __exit alsa_card_cs4281_exit(void)
2153{
2154 pci_unregister_driver(&driver);
2155}
2156
2157module_init(alsa_card_cs4281_init)
2158module_exit(alsa_card_cs4281_exit)
2159
2160#ifndef MODULE
2161
2162/* format is: snd-cs4281=snd_enable,snd_index,snd_id */
2163
2164static int __init alsa_card_cs4281_setup(char *str)
2165{
2166 static unsigned __initdata nr_dev = 0;
2167
2168 if (nr_dev >= SNDRV_CARDS)
2169 return 0;
2170 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2171 get_option(&str,&index[nr_dev]) == 2 &&
2172 get_id(&str,&id[nr_dev]) == 2);
2173 nr_dev++;
2174 return 1;
2175}
2176
2177__setup("snd-cs4281=", alsa_card_cs4281_setup);
2178
2179#endif /* ifndef MODULE */
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