source: GPL/trunk/alsa-kernel/pci/cmipci.c@ 752

Last change on this file since 752 was 717, checked in by David Azarewicz, 3 years ago

Merge changes from next branch.
File size: 102.8 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 */
6
7/* Does not work. Warning may block system in capture mode */
8/* #define USE_VAR48KRATE */
9
10#include <linux/io.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/gameport.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <sound/core.h>
20#include <sound/info.h>
21#include <sound/control.h>
22#include <sound/pcm.h>
23#include <sound/rawmidi.h>
24#include <sound/mpu401.h>
25#include <sound/opl3.h>
26#include <sound/sb.h>
27#include <sound/asoundef.h>
28#include <sound/initval.h>
29
30#ifdef TARGET_OS2
31#define KBUILD_MODNAME "cmipci"
32#endif
33MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
34MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
35MODULE_LICENSE("GPL");
36
37#if IS_REACHABLE(CONFIG_GAMEPORT)
38#define SUPPORT_JOYSTICK 1
39#endif
40
41static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
43static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
44#ifndef TARGET_OS2
45static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
46static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
47static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
48#else
49static long mpu_port[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
50static long fm_port[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
51static bool soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
52#endif
53#ifdef SUPPORT_JOYSTICK
54static int joystick_port[SNDRV_CARDS];
55#endif
56
57module_param_array(index, int, NULL, 0444);
58MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
59module_param_array(id, charp, NULL, 0444);
60MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
61module_param_array(enable, bool, NULL, 0444);
62MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
63module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
64MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
65module_param_hw_array(fm_port, long, ioport, NULL, 0444);
66MODULE_PARM_DESC(fm_port, "FM port.");
67module_param_array(soft_ac3, bool, NULL, 0444);
68MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
69#ifdef SUPPORT_JOYSTICK
70module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
71MODULE_PARM_DESC(joystick_port, "Joystick port address.");
72#endif
73
74/*
75 * CM8x38 registers definition
76 */
77
78#define CM_REG_FUNCTRL0 0x00
79#define CM_RST_CH1 0x00080000
80#define CM_RST_CH0 0x00040000
81#define CM_CHEN1 0x00020000 /* ch1: enable */
82#define CM_CHEN0 0x00010000 /* ch0: enable */
83#define CM_PAUSE1 0x00000008 /* ch1: pause */
84#define CM_PAUSE0 0x00000004 /* ch0: pause */
85#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
86#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
87
88#define CM_REG_FUNCTRL1 0x04
89#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
90#define CM_DSFC_SHIFT 13
91#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
92#define CM_ASFC_SHIFT 10
93#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
94#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
95#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
96#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
97#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
98#define CM_BREQ 0x00000010 /* bus master enabled */
99#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
100#define CM_UART_EN 0x00000004 /* legacy UART */
101#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
102#define CM_ZVPORT 0x00000001 /* ZVPORT */
103
104#define CM_REG_CHFORMAT 0x08
105
106#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
107#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
108#define CM_CHB3D 0x20000000 /* 4 channels */
109
110#define CM_CHIP_MASK1 0x1f000000
111#define CM_CHIP_037 0x01000000
112#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
113#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
114#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
115#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
116#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
117#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
118/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
119
120#define CM_ADCBITLEN_MASK 0x0000C000
121#define CM_ADCBITLEN_16 0x00000000
122#define CM_ADCBITLEN_15 0x00004000
123#define CM_ADCBITLEN_14 0x00008000
124#define CM_ADCBITLEN_13 0x0000C000
125
126#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
127#define CM_ADCDACLEN_060 0x00000000
128#define CM_ADCDACLEN_066 0x00001000
129#define CM_ADCDACLEN_130 0x00002000
130#define CM_ADCDACLEN_280 0x00003000
131
132#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
133#define CM_ADCDLEN_ORIGINAL 0x00000000
134#define CM_ADCDLEN_EXTRA 0x00001000
135#define CM_ADCDLEN_24K 0x00002000
136#define CM_ADCDLEN_WEIGHT 0x00003000
137
138#define CM_CH1_SRATE_176K 0x00000800
139#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
140#define CM_CH1_SRATE_88K 0x00000400
141#define CM_CH0_SRATE_176K 0x00000200
142#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
143#define CM_CH0_SRATE_88K 0x00000100
144#define CM_CH0_SRATE_128K 0x00000300
145#define CM_CH0_SRATE_MASK 0x00000300
146
147#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
148#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
149#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
150#define CM_SPDLOCKED 0x00000010
151
152#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
153#define CM_CH1FMT_SHIFT 2
154#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
155#define CM_CH0FMT_SHIFT 0
156
157#define CM_REG_INT_HLDCLR 0x0C
158#define CM_CHIP_MASK2 0xff000000
159#define CM_CHIP_8768 0x20000000
160#define CM_CHIP_055 0x08000000
161#define CM_CHIP_039 0x04000000
162#define CM_CHIP_039_6CH 0x01000000
163#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
164#define CM_TDMA_INT_EN 0x00040000
165#define CM_CH1_INT_EN 0x00020000
166#define CM_CH0_INT_EN 0x00010000
167
168#define CM_REG_INT_STATUS 0x10
169#define CM_INTR 0x80000000
170#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
171#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
172#define CM_UARTINT 0x00010000
173#define CM_LTDMAINT 0x00008000
174#define CM_HTDMAINT 0x00004000
175#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
176#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
177#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
178#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
179#define CM_CH1BUSY 0x00000008
180#define CM_CH0BUSY 0x00000004
181#define CM_CHINT1 0x00000002
182#define CM_CHINT0 0x00000001
183
184#define CM_REG_LEGACY_CTRL 0x14
185#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
186#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
187#define CM_VMPU_330 0x00000000
188#define CM_VMPU_320 0x20000000
189#define CM_VMPU_310 0x40000000
190#define CM_VMPU_300 0x60000000
191#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
192#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
193#define CM_VSBSEL_220 0x00000000
194#define CM_VSBSEL_240 0x04000000
195#define CM_VSBSEL_260 0x08000000
196#define CM_VSBSEL_280 0x0C000000
197#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
198#define CM_FMSEL_388 0x00000000
199#define CM_FMSEL_3C8 0x01000000
200#define CM_FMSEL_3E0 0x02000000
201#define CM_FMSEL_3E8 0x03000000
202#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
203#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
204#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
205#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
206#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
207#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
208#define CM_C_EECS 0x00040000
209#define CM_C_EEDI46 0x00020000
210#define CM_C_EECK46 0x00010000
211#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
212#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
213#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
214#define CM_EXBASEN 0x00001000 /* external bass input enable */
215
216#define CM_REG_MISC_CTRL 0x18
217#define CM_PWD 0x80000000 /* power down */
218#define CM_RESET 0x40000000
219#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
220#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
221#define CM_TXVX 0x08000000 /* model 037? */
222#define CM_N4SPK3D 0x04000000 /* copy front to rear */
223#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
224#define CM_SPDIF48K 0x01000000 /* write */
225#define CM_SPATUS48K 0x01000000 /* read */
226#define CM_ENDBDAC 0x00800000 /* enable double dac */
227#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
228#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
229#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
230#define CM_FM_EN 0x00080000 /* enable legacy FM */
231#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
232#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
233#define CM_VIDWPDSB 0x00010000 /* model 037? */
234#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
235#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
236#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
237#define CM_VIDWPPRT 0x00002000 /* model 037? */
238#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
239#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
240#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
241#define CM_ENCENTER 0x00000080
242#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
243#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
244#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
245#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
246#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
247#define CM_UPDDMA_2048 0x00000000
248#define CM_UPDDMA_1024 0x00000004
249#define CM_UPDDMA_512 0x00000008
250#define CM_UPDDMA_256 0x0000000C
251#define CM_TWAIT_MASK 0x00000003 /* model 037 */
252#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
253#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
254
255#define CM_REG_TDMA_POSITION 0x1C
256#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
257#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
258
259 /* byte */
260#define CM_REG_MIXER0 0x20
261#define CM_REG_SBVR 0x20 /* write: sb16 version */
262#define CM_REG_DEV 0x20 /* read: hardware device version */
263
264#define CM_REG_MIXER21 0x21
265#define CM_UNKNOWN_21_MASK 0x78 /* ? */
266#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
267#define CM_PROINV 0x02 /* SBPro left/right channel switching */
268#define CM_X_SB16 0x01 /* SB16 compatible */
269
270#define CM_REG_SB16_DATA 0x22
271#define CM_REG_SB16_ADDR 0x23
272
273#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
274#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
275#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
276#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
277
278#define CM_REG_MIXER1 0x24
279#define CM_FMMUTE 0x80 /* mute FM */
280#define CM_FMMUTE_SHIFT 7
281#define CM_WSMUTE 0x40 /* mute PCM */
282#define CM_WSMUTE_SHIFT 6
283#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
284#define CM_REAR2LIN_SHIFT 5
285#define CM_REAR2FRONT 0x10 /* exchange rear/front */
286#define CM_REAR2FRONT_SHIFT 4
287#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
288#define CM_WAVEINL_SHIFT 3
289#define CM_WAVEINR 0x04 /* digical wave rec. right */
290#define CM_WAVEINR_SHIFT 2
291#define CM_X3DEN 0x02 /* 3D surround enable */
292#define CM_X3DEN_SHIFT 1
293#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
294#define CM_CDPLAY_SHIFT 0
295
296#define CM_REG_MIXER2 0x25
297#define CM_RAUXREN 0x80 /* AUX right capture */
298#define CM_RAUXREN_SHIFT 7
299#define CM_RAUXLEN 0x40 /* AUX left capture */
300#define CM_RAUXLEN_SHIFT 6
301#define CM_VAUXRM 0x20 /* AUX right mute */
302#define CM_VAUXRM_SHIFT 5
303#define CM_VAUXLM 0x10 /* AUX left mute */
304#define CM_VAUXLM_SHIFT 4
305#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
306#define CM_VADMIC_SHIFT 1
307#define CM_MICGAINZ 0x01 /* mic boost */
308#define CM_MICGAINZ_SHIFT 0
309
310#define CM_REG_AUX_VOL 0x26
311#define CM_VAUXL_MASK 0xf0
312#define CM_VAUXR_MASK 0x0f
313
314#define CM_REG_MISC 0x27
315#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
316#define CM_XGPO1 0x20
317// #define CM_XGPBIO 0x04
318#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
319#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
320#define CM_SPDVALID 0x02 /* spdif input valid check */
321#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
322
323#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
324/*
325 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
326 * or identical with AC97 codec?
327 */
328#define CM_REG_EXTERN_CODEC CM_REG_AC97
329
330/*
331 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
332 */
333#define CM_REG_MPU_PCI 0x40
334
335/*
336 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
337 */
338#define CM_REG_FM_PCI 0x50
339
340/*
341 * access from SB-mixer port
342 */
343#define CM_REG_EXTENT_IND 0xf0
344#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
345#define CM_VPHONE_SHIFT 5
346#define CM_VPHOM 0x10 /* Phone mute control */
347#define CM_VSPKM 0x08 /* Speaker mute control, default high */
348#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
349#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
350#define CM_VADMIC3 0x01 /* Mic record boost */
351
352/*
353 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
354 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
355 * unit (readonly?).
356 */
357#define CM_REG_PLL 0xf8
358
359/*
360 * extended registers
361 */
362#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
363#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
364#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
365#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
366
367#define CM_REG_EXT_MISC 0x90
368#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
369#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
370#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
371#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
372#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
373#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
374#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
375#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
376
377/*
378 * size of i/o region
379 */
380#define CM_EXTENT_CODEC 0x100
381#define CM_EXTENT_MIDI 0x2
382#define CM_EXTENT_SYNTH 0x4
383
384
385/*
386 * channels for playback / capture
387 */
388#define CM_CH_PLAY 0
389#define CM_CH_CAPT 1
390
391/*
392 * flags to check device open/close
393 */
394#define CM_OPEN_NONE 0
395#define CM_OPEN_CH_MASK 0x01
396#define CM_OPEN_DAC 0x10
397#define CM_OPEN_ADC 0x20
398#define CM_OPEN_SPDIF 0x40
399#define CM_OPEN_MCHAN 0x80
400#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
401#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
402#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
403#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
404#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
405#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
406
407
408#if CM_CH_PLAY == 1
409#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
410#define CM_PLAYBACK_SPDF CM_SPDF_1
411#define CM_CAPTURE_SPDF CM_SPDF_0
412#else
413#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
414#define CM_PLAYBACK_SPDF CM_SPDF_0
415#define CM_CAPTURE_SPDF CM_SPDF_1
416#endif
417
418
419/*
420 * driver data
421 */
422
423struct cmipci_pcm {
424 struct snd_pcm_substream *substream;
425 u8 running; /* dac/adc running? */
426 u8 fmt; /* format bits */
427 u8 is_dac;
428 u8 needs_silencing;
429 unsigned int dma_size; /* in frames */
430 unsigned int shift;
431 unsigned int ch; /* channel (0/1) */
432 unsigned int offset; /* physical address of the buffer */
433};
434
435/* mixer elements toggled/resumed during ac3 playback */
436struct cmipci_mixer_auto_switches {
437 const char *name; /* switch to toggle */
438 int toggle_on; /* value to change when ac3 mode */
439};
440static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
441 {"PCM Playback Switch", 0},
442 {"IEC958 Output Switch", 1},
443 {"IEC958 Mix Analog", 0},
444 // {"IEC958 Out To DAC", 1}, // no longer used
445 {"IEC958 Loop", 0},
446};
447#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
448
449struct cmipci {
450 struct snd_card *card;
451
452 struct pci_dev *pci;
453 unsigned int device; /* device ID */
454 int irq;
455
456 unsigned long iobase;
457 unsigned int ctrl; /* FUNCTRL0 current value */
458
459 struct snd_pcm *pcm; /* DAC/ADC PCM */
460 struct snd_pcm *pcm2; /* 2nd DAC */
461 struct snd_pcm *pcm_spdif; /* SPDIF */
462
463 int chip_version;
464 int max_channels;
465 unsigned int can_ac3_sw: 1;
466 unsigned int can_ac3_hw: 1;
467 unsigned int can_multi_ch: 1;
468 unsigned int can_96k: 1; /* samplerate above 48k */
469 unsigned int do_soft_ac3: 1;
470
471 unsigned int spdif_playback_avail: 1; /* spdif ready? */
472 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
473 int spdif_counter; /* for software AC3 */
474
475 unsigned int dig_status;
476 unsigned int dig_pcm_status;
477
478 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
479
480 int opened[2]; /* open mode */
481 struct mutex open_mutex;
482
483 unsigned int mixer_insensitive: 1;
484 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
485 int mixer_res_status[CM_SAVED_MIXERS];
486
487 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
488
489 /* external MIDI */
490 struct snd_rawmidi *rmidi;
491
492#ifdef SUPPORT_JOYSTICK
493 struct gameport *gameport;
494#endif
495
496 spinlock_t reg_lock;
497
498#ifdef CONFIG_PM_SLEEP
499 unsigned int saved_regs[0x20];
500 unsigned char saved_mixers[0x20];
501#endif
502};
503
504
505/* read/write operations for dword register */
506static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
507{
508 outl(data, cm->iobase + cmd);
509}
510
511static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
512{
513 return inl(cm->iobase + cmd);
514}
515
516/* read/write operations for word register */
517static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
518{
519 outw(data, cm->iobase + cmd);
520}
521
522static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
523{
524 return inw(cm->iobase + cmd);
525}
526
527/* read/write operations for byte register */
528static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
529{
530 outb(data, cm->iobase + cmd);
531}
532
533static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
534{
535 return inb(cm->iobase + cmd);
536}
537
538/* bit operations for dword register */
539static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
540{
541 unsigned int val, oval;
542 val = oval = inl(cm->iobase + cmd);
543 val |= flag;
544 if (val == oval)
545 return 0;
546 outl(val, cm->iobase + cmd);
547 return 1;
548}
549
550static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
551{
552 unsigned int val, oval;
553 val = oval = inl(cm->iobase + cmd);
554 val &= ~flag;
555 if (val == oval)
556 return 0;
557 outl(val, cm->iobase + cmd);
558 return 1;
559}
560
561/* bit operations for byte register */
562static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
563{
564 unsigned char val, oval;
565 val = oval = inb(cm->iobase + cmd);
566 val |= flag;
567 if (val == oval)
568 return 0;
569 outb(val, cm->iobase + cmd);
570 return 1;
571}
572
573static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
574{
575 unsigned char val, oval;
576 val = oval = inb(cm->iobase + cmd);
577 val &= ~flag;
578 if (val == oval)
579 return 0;
580 outb(val, cm->iobase + cmd);
581 return 1;
582}
583
584
585/*
586 * PCM interface
587 */
588
589/*
590 * calculate frequency
591 */
592
593static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
594
595static unsigned int snd_cmipci_rate_freq(unsigned int rate)
596{
597 unsigned int i;
598
599 for (i = 0; i < ARRAY_SIZE(rates); i++) {
600 if (rates[i] == rate)
601 return i;
602 }
603 snd_BUG();
604 return 0;
605}
606
607#ifdef USE_VAR48KRATE
608/*
609 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
610 * does it this way .. maybe not. Never get any information from C-Media about
611 * that <werner@suse.de>.
612 */
613static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
614{
615 unsigned int delta, tolerance;
616 int xm, xn, xr;
617
618 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
619 rate <<= 1;
620 *n = -1;
621 if (*r > 0xff)
622 goto out;
623 tolerance = rate*CM_TOLERANCE_RATE;
624
625 for (xn = (1+2); xn < (0x1f+2); xn++) {
626 for (xm = (1+2); xm < (0xff+2); xm++) {
627 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
628
629 if (xr < rate)
630 delta = rate - xr;
631 else
632 delta = xr - rate;
633
634 /*
635 * If we found one, remember this,
636 * and try to find a closer one
637 */
638 if (delta < tolerance) {
639 tolerance = delta;
640 *m = xm - 2;
641 *n = xn - 2;
642 }
643 }
644 }
645out:
646 return (*n > -1);
647}
648
649/*
650 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
651 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
652 * at the register CM_REG_FUNCTRL1 (0x04).
653 * Problem: other ways are also possible (any information about that?)
654 */
655static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
656{
657 unsigned int reg = CM_REG_PLL + slot;
658 /*
659 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
660 * for DSFC/ASFC (000 up to 111).
661 */
662
663 /* FIXME: Init (Do we've to set an other register first before programming?) */
664
665 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
666 snd_cmipci_write_b(cm, reg, rate>>8);
667 snd_cmipci_write_b(cm, reg, rate&0xff);
668
669 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
670}
671#endif /* USE_VAR48KRATE */
672
673static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
674 struct snd_pcm_hw_params *hw_params)
675{
676 struct cmipci *cm = snd_pcm_substream_chip(substream);
677 if (params_channels(hw_params) > 2) {
678 mutex_lock(&cm->open_mutex);
679 if (cm->opened[CM_CH_PLAY]) {
680 mutex_unlock(&cm->open_mutex);
681 return -EBUSY;
682 }
683 /* reserve the channel A */
684 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
685 mutex_unlock(&cm->open_mutex);
686 }
687 return 0;
688}
689
690static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
691{
692 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
693 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
694 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
695 udelay(10);
696}
697
698
699/*
700 */
701
702static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
703static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
704 .count = 3,
705 .list = hw_channels,
706 .mask = 0,
707};
708static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
709 .count = 4,
710 .list = hw_channels,
711 .mask = 0,
712};
713static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
714 .count = 5,
715 .list = hw_channels,
716 .mask = 0,
717};
718
719static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
720{
721 if (channels > 2) {
722 if (!cm->can_multi_ch || !rec->ch)
723 return -EINVAL;
724 if (rec->fmt != 0x03) /* stereo 16bit only */
725 return -EINVAL;
726 }
727
728 if (cm->can_multi_ch) {
729 spin_lock_irq(&cm->reg_lock);
730 if (channels > 2) {
731 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
732 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
733 } else {
734 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
735 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
736 }
737 if (channels == 8)
738 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
739 else
740 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
741 if (channels == 6) {
742 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
743 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
744 } else {
745 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
746 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
747 }
748 if (channels == 4)
749 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
750 else
751 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
752 spin_unlock_irq(&cm->reg_lock);
753 }
754 return 0;
755}
756
757
758/*
759 * prepare playback/capture channel
760 * channel to be used must have been set in rec->ch.
761 */
762static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
763 struct snd_pcm_substream *substream)
764{
765 unsigned int reg, freq, freq_ext, val;
766 unsigned int period_size;
767 struct snd_pcm_runtime *runtime = substream->runtime;
768
769 rec->fmt = 0;
770 rec->shift = 0;
771 if (snd_pcm_format_width(runtime->format) >= 16) {
772 rec->fmt |= 0x02;
773 if (snd_pcm_format_width(runtime->format) > 16)
774 rec->shift++; /* 24/32bit */
775 }
776 if (runtime->channels > 1)
777 rec->fmt |= 0x01;
778 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
779 dev_dbg(cm->card->dev, "cannot set dac channels\n");
780 return -EINVAL;
781 }
782
783 rec->offset = runtime->dma_addr;
784 /* buffer and period sizes in frame */
785 rec->dma_size = runtime->buffer_size << rec->shift;
786 period_size = runtime->period_size << rec->shift;
787 if (runtime->channels > 2) {
788 /* multi-channels */
789 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
790 period_size = (period_size * runtime->channels) / 2;
791 }
792
793 spin_lock_irq(&cm->reg_lock);
794
795 /* set buffer address */
796 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
797 snd_cmipci_write(cm, reg, rec->offset);
798 /* program sample counts */
799 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
800 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
801 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
802
803 /* set adc/dac flag */
804 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
805 if (rec->is_dac)
806 cm->ctrl &= ~val;
807 else
808 cm->ctrl |= val;
809 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
810 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
811
812 /* set sample rate */
813 freq = 0;
814 freq_ext = 0;
815 if (runtime->rate > 48000)
816 switch (runtime->rate) {
817 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
818 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
819 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
820 default: snd_BUG(); break;
821 }
822 else
823 freq = snd_cmipci_rate_freq(runtime->rate);
824 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
825 if (rec->ch) {
826 val &= ~CM_DSFC_MASK;
827 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
828 } else {
829 val &= ~CM_ASFC_MASK;
830 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
831 }
832 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
833 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
834
835 /* set format */
836 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
837 if (rec->ch) {
838 val &= ~CM_CH1FMT_MASK;
839 val |= rec->fmt << CM_CH1FMT_SHIFT;
840 } else {
841 val &= ~CM_CH0FMT_MASK;
842 val |= rec->fmt << CM_CH0FMT_SHIFT;
843 }
844 if (cm->can_96k) {
845 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
846 val |= freq_ext << (rec->ch * 2);
847 }
848 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
849 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
850
851 if (!rec->is_dac && cm->chip_version) {
852 if (runtime->rate > 44100)
853 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
854 else
855 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
856 }
857
858 rec->running = 0;
859 spin_unlock_irq(&cm->reg_lock);
860
861 return 0;
862}
863
864/*
865 * PCM trigger/stop
866 */
867static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
868 int cmd)
869{
870 unsigned int inthld, chen, reset, pause;
871 int result = 0;
872
873 inthld = CM_CH0_INT_EN << rec->ch;
874 chen = CM_CHEN0 << rec->ch;
875 reset = CM_RST_CH0 << rec->ch;
876 pause = CM_PAUSE0 << rec->ch;
877
878 spin_lock(&cm->reg_lock);
879 switch (cmd) {
880 case SNDRV_PCM_TRIGGER_START:
881 rec->running = 1;
882 /* set interrupt */
883 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
884 cm->ctrl |= chen;
885 /* enable channel */
886 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
887 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
888 break;
889 case SNDRV_PCM_TRIGGER_STOP:
890 rec->running = 0;
891 /* disable interrupt */
892 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
893 /* reset */
894 cm->ctrl &= ~chen;
895 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
896 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
897 rec->needs_silencing = rec->is_dac;
898 break;
899 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
900 case SNDRV_PCM_TRIGGER_SUSPEND:
901 cm->ctrl |= pause;
902 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
903 break;
904 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
905 case SNDRV_PCM_TRIGGER_RESUME:
906 cm->ctrl &= ~pause;
907 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
908 break;
909 default:
910 result = -EINVAL;
911 break;
912 }
913 spin_unlock(&cm->reg_lock);
914 return result;
915}
916
917/*
918 * return the current pointer
919 */
920static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
921 struct snd_pcm_substream *substream)
922{
923 size_t ptr;
924 unsigned int reg, rem, tries;
925
926 if (!rec->running)
927 return 0;
928#if 1 // this seems better..
929 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
930 for (tries = 0; tries < 3; tries++) {
931 rem = snd_cmipci_read_w(cm, reg);
932 if (rem < rec->dma_size)
933 goto ok;
934 }
935 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
936 return SNDRV_PCM_POS_XRUN;
937ok:
938 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
939#else
940 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
941 ptr = snd_cmipci_read(cm, reg) - rec->offset;
942 ptr = bytes_to_frames(substream->runtime, ptr);
943#endif
944 if (substream->runtime->channels > 2)
945 ptr = (ptr * 2) / substream->runtime->channels;
946 return ptr;
947}
948
949/*
950 * playback
951 */
952
953static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
954 int cmd)
955{
956 struct cmipci *cm = snd_pcm_substream_chip(substream);
957 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
958}
959
960static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
961{
962 struct cmipci *cm = snd_pcm_substream_chip(substream);
963 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
964}
965
966
967
968/*
969 * capture
970 */
971
972static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
973 int cmd)
974{
975 struct cmipci *cm = snd_pcm_substream_chip(substream);
976 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
977}
978
979static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
980{
981 struct cmipci *cm = snd_pcm_substream_chip(substream);
982 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
983}
984
985
986/*
987 * hw preparation for spdif
988 */
989
990static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
991 struct snd_ctl_elem_info *uinfo)
992{
993 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
994 uinfo->count = 1;
995 return 0;
996}
997
998static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
999 struct snd_ctl_elem_value *ucontrol)
1000{
1001 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1002 int i;
1003
1004 spin_lock_irq(&chip->reg_lock);
1005 for (i = 0; i < 4; i++)
1006 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1007 spin_unlock_irq(&chip->reg_lock);
1008 return 0;
1009}
1010
1011static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1012 struct snd_ctl_elem_value *ucontrol)
1013{
1014 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1015 int i, change;
1016 unsigned int val;
1017
1018 val = 0;
1019 spin_lock_irq(&chip->reg_lock);
1020 for (i = 0; i < 4; i++)
1021 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1022 change = val != chip->dig_status;
1023 chip->dig_status = val;
1024 spin_unlock_irq(&chip->reg_lock);
1025 return change;
1026}
1027
1028static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1029{
1030 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1031 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1032 .info = snd_cmipci_spdif_default_info,
1033 .get = snd_cmipci_spdif_default_get,
1034 .put = snd_cmipci_spdif_default_put
1035};
1036
1037static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1038 struct snd_ctl_elem_info *uinfo)
1039{
1040 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1041 uinfo->count = 1;
1042 return 0;
1043}
1044
1045static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1046 struct snd_ctl_elem_value *ucontrol)
1047{
1048 ucontrol->value.iec958.status[0] = 0xff;
1049 ucontrol->value.iec958.status[1] = 0xff;
1050 ucontrol->value.iec958.status[2] = 0xff;
1051 ucontrol->value.iec958.status[3] = 0xff;
1052 return 0;
1053}
1054
1055static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1056{
1057 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1058 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1059 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1060 .info = snd_cmipci_spdif_mask_info,
1061 .get = snd_cmipci_spdif_mask_get,
1062};
1063
1064static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1065 struct snd_ctl_elem_info *uinfo)
1066{
1067 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1068 uinfo->count = 1;
1069 return 0;
1070}
1071
1072static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1073 struct snd_ctl_elem_value *ucontrol)
1074{
1075 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1076 int i;
1077
1078 spin_lock_irq(&chip->reg_lock);
1079 for (i = 0; i < 4; i++)
1080 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1081 spin_unlock_irq(&chip->reg_lock);
1082 return 0;
1083}
1084
1085static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1086 struct snd_ctl_elem_value *ucontrol)
1087{
1088 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1089 int i, change;
1090 unsigned int val;
1091
1092 val = 0;
1093 spin_lock_irq(&chip->reg_lock);
1094 for (i = 0; i < 4; i++)
1095 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1096 change = val != chip->dig_pcm_status;
1097 chip->dig_pcm_status = val;
1098 spin_unlock_irq(&chip->reg_lock);
1099 return change;
1100}
1101
1102static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1103{
1104 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1105 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1106 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1107 .info = snd_cmipci_spdif_stream_info,
1108 .get = snd_cmipci_spdif_stream_get,
1109 .put = snd_cmipci_spdif_stream_put
1110};
1111
1112/*
1113 */
1114
1115/* save mixer setting and mute for AC3 playback */
1116static int save_mixer_state(struct cmipci *cm)
1117{
1118 if (! cm->mixer_insensitive) {
1119 struct snd_ctl_elem_value *val;
1120 unsigned int i;
1121
1122 val = kmalloc(sizeof(*val), GFP_KERNEL);
1123 if (!val)
1124 return -ENOMEM;
1125 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1126 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1127 if (ctl) {
1128 int event;
1129 memset(val, 0, sizeof(*val));
1130 ctl->get(ctl, val);
1131 cm->mixer_res_status[i] = val->value.integer.value[0];
1132 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1133 event = SNDRV_CTL_EVENT_MASK_INFO;
1134 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1135 ctl->put(ctl, val); /* toggle */
1136 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1137 }
1138 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1139 snd_ctl_notify(cm->card, event, &ctl->id);
1140 }
1141 }
1142 kfree(val);
1143 cm->mixer_insensitive = 1;
1144 }
1145 return 0;
1146}
1147
1148
1149/* restore the previously saved mixer status */
1150static void restore_mixer_state(struct cmipci *cm)
1151{
1152 if (cm->mixer_insensitive) {
1153 struct snd_ctl_elem_value *val;
1154 unsigned int i;
1155
1156 val = kmalloc(sizeof(*val), GFP_KERNEL);
1157 if (!val)
1158 return;
1159 cm->mixer_insensitive = 0; /* at first clear this;
1160 otherwise the changes will be ignored */
1161 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1162 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1163 if (ctl) {
1164 int event;
1165
1166 memset(val, 0, sizeof(*val));
1167 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1168 ctl->get(ctl, val);
1169 event = SNDRV_CTL_EVENT_MASK_INFO;
1170 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1171 val->value.integer.value[0] = cm->mixer_res_status[i];
1172 ctl->put(ctl, val);
1173 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1174 }
1175 snd_ctl_notify(cm->card, event, &ctl->id);
1176 }
1177 }
1178 kfree(val);
1179 }
1180}
1181
1182/* spinlock held! */
1183static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1184{
1185 if (do_ac3) {
1186 /* AC3EN for 037 */
1187 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1188 /* AC3EN for 039 */
1189 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1190
1191 if (cm->can_ac3_hw) {
1192 /* SPD24SEL for 037, 0x02 */
1193 /* SPD24SEL for 039, 0x20, but cannot be set */
1194 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1195 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1196 } else { /* can_ac3_sw */
1197 /* SPD32SEL for 037 & 039, 0x20 */
1198 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1199 /* set 176K sample rate to fix 033 HW bug */
1200 if (cm->chip_version == 33) {
1201 if (rate >= 48000) {
1202 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1203 } else {
1204 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1205 }
1206 }
1207 }
1208
1209 } else {
1210 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1211 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1212
1213 if (cm->can_ac3_hw) {
1214 /* chip model >= 37 */
1215 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1216 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1217 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1218 } else {
1219 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1220 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1221 }
1222 } else {
1223 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1224 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1225 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1226 }
1227 }
1228}
1229
1230static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1231{
1232 int rate, err;
1233
1234 rate = subs->runtime->rate;
1235
1236 if (up && do_ac3) {
1237 err = save_mixer_state(cm);
1238 if (err < 0)
1239 return err;
1240 }
1241
1242 spin_lock_irq(&cm->reg_lock);
1243 cm->spdif_playback_avail = up;
1244 if (up) {
1245 /* they are controlled via "IEC958 Output Switch" */
1246 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1247 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1248 if (cm->spdif_playback_enabled)
1249 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1250 setup_ac3(cm, subs, do_ac3, rate);
1251
1252 if (rate == 48000 || rate == 96000)
1253 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1254 else
1255 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1256 if (rate > 48000)
1257 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1258 else
1259 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1260 } else {
1261 /* they are controlled via "IEC958 Output Switch" */
1262 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1263 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1264 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1265 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1266 setup_ac3(cm, subs, 0, 0);
1267 }
1268 spin_unlock_irq(&cm->reg_lock);
1269 return 0;
1270}
1271
1272
1273/*
1274 * preparation
1275 */
1276
1277/* playback - enable spdif only on the certain condition */
1278static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1279{
1280 struct cmipci *cm = snd_pcm_substream_chip(substream);
1281 int rate = substream->runtime->rate;
1282 int err, do_spdif, do_ac3 = 0;
1283
1284 do_spdif = (rate >= 44100 && rate <= 96000 &&
1285 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1286 substream->runtime->channels == 2);
1287 if (do_spdif && cm->can_ac3_hw)
1288 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1289 err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1290 if (err < 0)
1291 return err;
1292 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1293}
1294
1295/* playback (via device #2) - enable spdif always */
1296static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1297{
1298 struct cmipci *cm = snd_pcm_substream_chip(substream);
1299 int err, do_ac3;
1300
1301 if (cm->can_ac3_hw)
1302 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1303 else
1304 do_ac3 = 1; /* doesn't matter */
1305 err = setup_spdif_playback(cm, substream, 1, do_ac3);
1306 if (err < 0)
1307 return err;
1308 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1309}
1310
1311/*
1312 * Apparently, the samples last played on channel A stay in some buffer, even
1313 * after the channel is reset, and get added to the data for the rear DACs when
1314 * playing a multichannel stream on channel B. This is likely to generate
1315 * wraparounds and thus distortions.
1316 * To avoid this, we play at least one zero sample after the actual stream has
1317 * stopped.
1318 */
1319static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1320{
1321 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1322 unsigned int reg, val;
1323
1324 if (rec->needs_silencing && runtime && runtime->dma_area) {
1325 /* set up a small silence buffer */
1326 memset(runtime->dma_area, 0, PAGE_SIZE);
1327 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1328 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1329 snd_cmipci_write(cm, reg, val);
1330
1331 /* configure for 16 bits, 2 channels, 8 kHz */
1332 if (runtime->channels > 2)
1333 set_dac_channels(cm, rec, 2);
1334 spin_lock_irq(&cm->reg_lock);
1335 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1336 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1337 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1338 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1339 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1340 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1341 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1342 if (cm->can_96k)
1343 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1344 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1345
1346 /* start stream (we don't need interrupts) */
1347 cm->ctrl |= CM_CHEN0 << rec->ch;
1348 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1349 spin_unlock_irq(&cm->reg_lock);
1350
1351 msleep(1);
1352
1353 /* stop and reset stream */
1354 spin_lock_irq(&cm->reg_lock);
1355 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1356 val = CM_RST_CH0 << rec->ch;
1357 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1358 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1359 spin_unlock_irq(&cm->reg_lock);
1360
1361 rec->needs_silencing = 0;
1362 }
1363}
1364
1365static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1366{
1367 struct cmipci *cm = snd_pcm_substream_chip(substream);
1368 setup_spdif_playback(cm, substream, 0, 0);
1369 restore_mixer_state(cm);
1370 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1371 return 0;
1372}
1373
1374static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1375{
1376 struct cmipci *cm = snd_pcm_substream_chip(substream);
1377 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1378 return 0;
1379}
1380
1381/* capture */
1382static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1383{
1384 struct cmipci *cm = snd_pcm_substream_chip(substream);
1385 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1386}
1387
1388/* capture with spdif (via device #2) */
1389static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1390{
1391 struct cmipci *cm = snd_pcm_substream_chip(substream);
1392
1393 spin_lock_irq(&cm->reg_lock);
1394 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1395 if (cm->can_96k) {
1396 if (substream->runtime->rate > 48000)
1397 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1398 else
1399 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1400 }
1401 if (snd_pcm_format_width(substream->runtime->format) > 16)
1402 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1403 else
1404 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1405
1406 spin_unlock_irq(&cm->reg_lock);
1407
1408 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1409}
1410
1411static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1412{
1413 struct cmipci *cm = snd_pcm_substream_chip(subs);
1414
1415 spin_lock_irq(&cm->reg_lock);
1416 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1417 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1418 spin_unlock_irq(&cm->reg_lock);
1419
1420 return 0;
1421}
1422
1423
1424/*
1425 * interrupt handler
1426 */
1427static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1428{
1429 struct cmipci *cm = dev_id;
1430 unsigned int status, mask = 0;
1431
1432 /* fastpath out, to ease interrupt sharing */
1433 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1434 if (!(status & CM_INTR))
1435 return IRQ_NONE;
1436
1437 /* acknowledge interrupt */
1438 spin_lock(&cm->reg_lock);
1439 if (status & CM_CHINT0)
1440 mask |= CM_CH0_INT_EN;
1441 if (status & CM_CHINT1)
1442 mask |= CM_CH1_INT_EN;
1443 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1444 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1445 spin_unlock(&cm->reg_lock);
1446
1447 if (cm->rmidi && (status & CM_UARTINT))
1448 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1449
1450 if (cm->pcm) {
1451 if ((status & CM_CHINT0) && cm->channel[0].running)
1452 snd_pcm_period_elapsed(cm->channel[0].substream);
1453 if ((status & CM_CHINT1) && cm->channel[1].running)
1454 snd_pcm_period_elapsed(cm->channel[1].substream);
1455 }
1456 return IRQ_HANDLED;
1457}
1458
1459/*
1460 * h/w infos
1461 */
1462
1463/* playback on channel A */
1464static const struct snd_pcm_hardware snd_cmipci_playback =
1465{
1466 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1467 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1468 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1469 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1470 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1471 .rate_min = 5512,
1472 .rate_max = 48000,
1473 .channels_min = 1,
1474 .channels_max = 2,
1475 .buffer_bytes_max = (128*1024),
1476 .period_bytes_min = 64,
1477 .period_bytes_max = (128*1024),
1478 .periods_min = 2,
1479 .periods_max = 1024,
1480 .fifo_size = 0,
1481};
1482
1483/* capture on channel B */
1484static const struct snd_pcm_hardware snd_cmipci_capture =
1485{
1486 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1487 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1488 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1489 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1490 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1491 .rate_min = 5512,
1492 .rate_max = 48000,
1493 .channels_min = 1,
1494 .channels_max = 2,
1495 .buffer_bytes_max = (128*1024),
1496 .period_bytes_min = 64,
1497 .period_bytes_max = (128*1024),
1498 .periods_min = 2,
1499 .periods_max = 1024,
1500 .fifo_size = 0,
1501};
1502
1503/* playback on channel B - stereo 16bit only? */
1504static const struct snd_pcm_hardware snd_cmipci_playback2 =
1505{
1506 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1507 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1508 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1509 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1510 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1511 .rate_min = 5512,
1512 .rate_max = 48000,
1513 .channels_min = 2,
1514 .channels_max = 2,
1515 .buffer_bytes_max = (128*1024),
1516 .period_bytes_min = 64,
1517 .period_bytes_max = (128*1024),
1518 .periods_min = 2,
1519 .periods_max = 1024,
1520 .fifo_size = 0,
1521};
1522
1523/* spdif playback on channel A */
1524static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1525{
1526 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1527 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1528 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1529 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1530 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1531 .rate_min = 44100,
1532 .rate_max = 48000,
1533 .channels_min = 2,
1534 .channels_max = 2,
1535 .buffer_bytes_max = (128*1024),
1536 .period_bytes_min = 64,
1537 .period_bytes_max = (128*1024),
1538 .periods_min = 2,
1539 .periods_max = 1024,
1540 .fifo_size = 0,
1541};
1542
1543/* spdif playback on channel A (32bit, IEC958 subframes) */
1544static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1545{
1546 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1547 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1548 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1549 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1550 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1551 .rate_min = 44100,
1552 .rate_max = 48000,
1553 .channels_min = 2,
1554 .channels_max = 2,
1555 .buffer_bytes_max = (128*1024),
1556 .period_bytes_min = 64,
1557 .period_bytes_max = (128*1024),
1558 .periods_min = 2,
1559 .periods_max = 1024,
1560 .fifo_size = 0,
1561};
1562
1563/* spdif capture on channel B */
1564static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1565{
1566 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1567 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1568 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1569 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1570 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1571 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1572 .rate_min = 44100,
1573 .rate_max = 48000,
1574 .channels_min = 2,
1575 .channels_max = 2,
1576 .buffer_bytes_max = (128*1024),
1577 .period_bytes_min = 64,
1578 .period_bytes_max = (128*1024),
1579 .periods_min = 2,
1580 .periods_max = 1024,
1581 .fifo_size = 0,
1582};
1583
1584static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1585 32000, 44100, 48000, 88200, 96000, 128000 };
1586static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1587 .count = ARRAY_SIZE(rate_constraints),
1588 .list = rate_constraints,
1589 .mask = 0,
1590};
1591
1592/*
1593 * check device open/close
1594 */
1595static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1596{
1597 int ch = mode & CM_OPEN_CH_MASK;
1598
1599 /* FIXME: a file should wait until the device becomes free
1600 * when it's opened on blocking mode. however, since the current
1601 * pcm framework doesn't pass file pointer before actually opened,
1602 * we can't know whether blocking mode or not in open callback..
1603 */
1604 mutex_lock(&cm->open_mutex);
1605 if (cm->opened[ch]) {
1606 mutex_unlock(&cm->open_mutex);
1607 return -EBUSY;
1608 }
1609 cm->opened[ch] = mode;
1610 cm->channel[ch].substream = subs;
1611 if (! (mode & CM_OPEN_DAC)) {
1612 /* disable dual DAC mode */
1613 cm->channel[ch].is_dac = 0;
1614 spin_lock_irq(&cm->reg_lock);
1615 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1616 spin_unlock_irq(&cm->reg_lock);
1617 }
1618 mutex_unlock(&cm->open_mutex);
1619 return 0;
1620}
1621
1622static void close_device_check(struct cmipci *cm, int mode)
1623{
1624 int ch = mode & CM_OPEN_CH_MASK;
1625
1626 mutex_lock(&cm->open_mutex);
1627 if (cm->opened[ch] == mode) {
1628 if (cm->channel[ch].substream) {
1629 snd_cmipci_ch_reset(cm, ch);
1630 cm->channel[ch].running = 0;
1631 cm->channel[ch].substream = NULL;
1632 }
1633 cm->opened[ch] = 0;
1634 if (! cm->channel[ch].is_dac) {
1635 /* enable dual DAC mode again */
1636 cm->channel[ch].is_dac = 1;
1637 spin_lock_irq(&cm->reg_lock);
1638 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1639 spin_unlock_irq(&cm->reg_lock);
1640 }
1641 }
1642 mutex_unlock(&cm->open_mutex);
1643}
1644
1645/*
1646 */
1647
1648static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1649{
1650 struct cmipci *cm = snd_pcm_substream_chip(substream);
1651 struct snd_pcm_runtime *runtime = substream->runtime;
1652 int err;
1653
1654 err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1655 if (err < 0)
1656 return err;
1657 runtime->hw = snd_cmipci_playback;
1658 if (cm->chip_version == 68) {
1659 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1660 SNDRV_PCM_RATE_96000;
1661 runtime->hw.rate_max = 96000;
1662 } else if (cm->chip_version == 55) {
1663 err = snd_pcm_hw_constraint_list(runtime, 0,
1664 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1665 if (err < 0)
1666 return err;
1667 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1668 runtime->hw.rate_max = 128000;
1669 }
1670 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1671 cm->dig_pcm_status = cm->dig_status;
1672 return 0;
1673}
1674
1675static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1676{
1677 struct cmipci *cm = snd_pcm_substream_chip(substream);
1678 struct snd_pcm_runtime *runtime = substream->runtime;
1679 int err;
1680
1681 err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1682 if (err < 0)
1683 return err;
1684 runtime->hw = snd_cmipci_capture;
1685 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1686 runtime->hw.rate_min = 41000;
1687 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1688 } else if (cm->chip_version == 55) {
1689 err = snd_pcm_hw_constraint_list(runtime, 0,
1690 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1691 if (err < 0)
1692 return err;
1693 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1694 runtime->hw.rate_max = 128000;
1695 }
1696 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1697 return 0;
1698}
1699
1700static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1701{
1702 struct cmipci *cm = snd_pcm_substream_chip(substream);
1703 struct snd_pcm_runtime *runtime = substream->runtime;
1704 int err;
1705
1706 /* use channel B */
1707 err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1708 if (err < 0)
1709 return err;
1710 runtime->hw = snd_cmipci_playback2;
1711 mutex_lock(&cm->open_mutex);
1712 if (! cm->opened[CM_CH_PLAY]) {
1713 if (cm->can_multi_ch) {
1714 runtime->hw.channels_max = cm->max_channels;
1715 if (cm->max_channels == 4)
1716 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1717 else if (cm->max_channels == 6)
1718 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1719 else if (cm->max_channels == 8)
1720 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1721 }
1722 }
1723 mutex_unlock(&cm->open_mutex);
1724 if (cm->chip_version == 68) {
1725 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1726 SNDRV_PCM_RATE_96000;
1727 runtime->hw.rate_max = 96000;
1728 } else if (cm->chip_version == 55) {
1729 err = snd_pcm_hw_constraint_list(runtime, 0,
1730 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1731 if (err < 0)
1732 return err;
1733 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1734 runtime->hw.rate_max = 128000;
1735 }
1736 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1737 return 0;
1738}
1739
1740static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1741{
1742 struct cmipci *cm = snd_pcm_substream_chip(substream);
1743 struct snd_pcm_runtime *runtime = substream->runtime;
1744 int err;
1745
1746 /* use channel A */
1747 err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1748 if (err < 0)
1749 return err;
1750 if (cm->can_ac3_hw) {
1751 runtime->hw = snd_cmipci_playback_spdif;
1752 if (cm->chip_version >= 37) {
1753 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1754 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1755 }
1756 if (cm->can_96k) {
1757 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1758 SNDRV_PCM_RATE_96000;
1759 runtime->hw.rate_max = 96000;
1760 }
1761 } else {
1762 runtime->hw = snd_cmipci_playback_iec958_subframe;
1763 }
1764 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1765 cm->dig_pcm_status = cm->dig_status;
1766 return 0;
1767}
1768
1769static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1770{
1771 struct cmipci *cm = snd_pcm_substream_chip(substream);
1772 struct snd_pcm_runtime *runtime = substream->runtime;
1773 int err;
1774
1775 /* use channel B */
1776 err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1777 if (err < 0)
1778 return err;
1779 runtime->hw = snd_cmipci_capture_spdif;
1780 if (cm->can_96k && !(cm->chip_version == 68)) {
1781 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1782 SNDRV_PCM_RATE_96000;
1783 runtime->hw.rate_max = 96000;
1784 }
1785 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1786 return 0;
1787}
1788
1789
1790/*
1791 */
1792
1793static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1794{
1795 struct cmipci *cm = snd_pcm_substream_chip(substream);
1796 close_device_check(cm, CM_OPEN_PLAYBACK);
1797 return 0;
1798}
1799
1800static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1801{
1802 struct cmipci *cm = snd_pcm_substream_chip(substream);
1803 close_device_check(cm, CM_OPEN_CAPTURE);
1804 return 0;
1805}
1806
1807static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1808{
1809 struct cmipci *cm = snd_pcm_substream_chip(substream);
1810 close_device_check(cm, CM_OPEN_PLAYBACK2);
1811 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1812 return 0;
1813}
1814
1815static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1816{
1817 struct cmipci *cm = snd_pcm_substream_chip(substream);
1818 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1819 return 0;
1820}
1821
1822static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1823{
1824 struct cmipci *cm = snd_pcm_substream_chip(substream);
1825 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1826 return 0;
1827}
1828
1829
1830/*
1831 */
1832
1833static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1834 .open = snd_cmipci_playback_open,
1835 .close = snd_cmipci_playback_close,
1836 .hw_free = snd_cmipci_playback_hw_free,
1837 .prepare = snd_cmipci_playback_prepare,
1838 .trigger = snd_cmipci_playback_trigger,
1839 .pointer = snd_cmipci_playback_pointer,
1840};
1841
1842static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1843 .open = snd_cmipci_capture_open,
1844 .close = snd_cmipci_capture_close,
1845 .prepare = snd_cmipci_capture_prepare,
1846 .trigger = snd_cmipci_capture_trigger,
1847 .pointer = snd_cmipci_capture_pointer,
1848};
1849
1850static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1851 .open = snd_cmipci_playback2_open,
1852 .close = snd_cmipci_playback2_close,
1853 .hw_params = snd_cmipci_playback2_hw_params,
1854 .hw_free = snd_cmipci_playback2_hw_free,
1855 .prepare = snd_cmipci_capture_prepare, /* channel B */
1856 .trigger = snd_cmipci_capture_trigger, /* channel B */
1857 .pointer = snd_cmipci_capture_pointer, /* channel B */
1858};
1859
1860static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1861 .open = snd_cmipci_playback_spdif_open,
1862 .close = snd_cmipci_playback_spdif_close,
1863 .hw_free = snd_cmipci_playback_hw_free,
1864 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1865 .trigger = snd_cmipci_playback_trigger,
1866 .pointer = snd_cmipci_playback_pointer,
1867};
1868
1869static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1870 .open = snd_cmipci_capture_spdif_open,
1871 .close = snd_cmipci_capture_spdif_close,
1872 .hw_free = snd_cmipci_capture_spdif_hw_free,
1873 .prepare = snd_cmipci_capture_spdif_prepare,
1874 .trigger = snd_cmipci_capture_trigger,
1875 .pointer = snd_cmipci_capture_pointer,
1876};
1877
1878
1879/*
1880 */
1881
1882static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1883{
1884 struct snd_pcm *pcm;
1885 int err;
1886
1887 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1888 if (err < 0)
1889 return err;
1890
1891 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1892 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1893
1894 pcm->private_data = cm;
1895 pcm->info_flags = 0;
1896 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1897 cm->pcm = pcm;
1898
1899 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1900 &cm->pci->dev, 64*1024, 128*1024);
1901
1902 return 0;
1903}
1904
1905static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1906{
1907 struct snd_pcm *pcm;
1908 int err;
1909
1910 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1911 if (err < 0)
1912 return err;
1913
1914 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1915
1916 pcm->private_data = cm;
1917 pcm->info_flags = 0;
1918 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1919 cm->pcm2 = pcm;
1920
1921 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1922 &cm->pci->dev, 64*1024, 128*1024);
1923
1924 return 0;
1925}
1926
1927static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1928{
1929 struct snd_pcm *pcm;
1930 int err;
1931
1932 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1933 if (err < 0)
1934 return err;
1935
1936 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1937 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1938
1939 pcm->private_data = cm;
1940 pcm->info_flags = 0;
1941 strcpy(pcm->name, "C-Media PCI IEC958");
1942 cm->pcm_spdif = pcm;
1943
1944 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1945 &cm->pci->dev, 64*1024, 128*1024);
1946
1947 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1948 snd_pcm_alt_chmaps, cm->max_channels, 0,
1949 NULL);
1950 if (err < 0)
1951 return err;
1952
1953 return 0;
1954}
1955
1956/*
1957 * mixer interface:
1958 * - CM8338/8738 has a compatible mixer interface with SB16, but
1959 * lack of some elements like tone control, i/o gain and AGC.
1960 * - Access to native registers:
1961 * - A 3D switch
1962 * - Output mute switches
1963 */
1964
1965static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1966{
1967 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1968 outb(data, s->iobase + CM_REG_SB16_DATA);
1969}
1970
1971static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1972{
1973 unsigned char v;
1974
1975 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1976 v = inb(s->iobase + CM_REG_SB16_DATA);
1977 return v;
1978}
1979
1980/*
1981 * general mixer element
1982 */
1983struct cmipci_sb_reg {
1984 unsigned int left_reg, right_reg;
1985 unsigned int left_shift, right_shift;
1986 unsigned int mask;
1987 unsigned int invert: 1;
1988 unsigned int stereo: 1;
1989};
1990
1991#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1992 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1993
1994#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1995{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1996 .info = snd_cmipci_info_volume, \
1997 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1998 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1999}
2000
2001#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2002#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2003#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2004#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2005
2006static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2007{
2008 r->left_reg = val & 0xff;
2009 r->right_reg = (val >> 8) & 0xff;
2010 r->left_shift = (val >> 16) & 0x07;
2011 r->right_shift = (val >> 19) & 0x07;
2012 r->invert = (val >> 22) & 1;
2013 r->stereo = (val >> 23) & 1;
2014 r->mask = (val >> 24) & 0xff;
2015}
2016
2017static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2018 struct snd_ctl_elem_info *uinfo)
2019{
2020 struct cmipci_sb_reg reg;
2021
2022 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2023 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2024 uinfo->count = reg.stereo + 1;
2025 uinfo->value.integer.min = 0;
2026 uinfo->value.integer.max = reg.mask;
2027 return 0;
2028}
2029
2030static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2031 struct snd_ctl_elem_value *ucontrol)
2032{
2033 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2034 struct cmipci_sb_reg reg;
2035 int val;
2036
2037 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2038 spin_lock_irq(&cm->reg_lock);
2039 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2040 if (reg.invert)
2041 val = reg.mask - val;
2042 ucontrol->value.integer.value[0] = val;
2043 if (reg.stereo) {
2044 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2045 if (reg.invert)
2046 val = reg.mask - val;
2047 ucontrol->value.integer.value[1] = val;
2048 }
2049 spin_unlock_irq(&cm->reg_lock);
2050 return 0;
2051}
2052
2053static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2054 struct snd_ctl_elem_value *ucontrol)
2055{
2056 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2057 struct cmipci_sb_reg reg;
2058 int change;
2059 int left, right, oleft, oright;
2060
2061 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2062 left = ucontrol->value.integer.value[0] & reg.mask;
2063 if (reg.invert)
2064 left = reg.mask - left;
2065 left <<= reg.left_shift;
2066 if (reg.stereo) {
2067 right = ucontrol->value.integer.value[1] & reg.mask;
2068 if (reg.invert)
2069 right = reg.mask - right;
2070 right <<= reg.right_shift;
2071 } else
2072 right = 0;
2073 spin_lock_irq(&cm->reg_lock);
2074 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2075 left |= oleft & ~(reg.mask << reg.left_shift);
2076 change = left != oleft;
2077 if (reg.stereo) {
2078 if (reg.left_reg != reg.right_reg) {
2079 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2080 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2081 } else
2082 oright = left;
2083 right |= oright & ~(reg.mask << reg.right_shift);
2084 change |= right != oright;
2085 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2086 } else
2087 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2088 spin_unlock_irq(&cm->reg_lock);
2089 return change;
2090}
2091
2092/*
2093 * input route (left,right) -> (left,right)
2094 */
2095#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2096{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2097 .info = snd_cmipci_info_input_sw, \
2098 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2099 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2100}
2101
2102static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2103 struct snd_ctl_elem_info *uinfo)
2104{
2105 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2106 uinfo->count = 4;
2107 uinfo->value.integer.min = 0;
2108 uinfo->value.integer.max = 1;
2109 return 0;
2110}
2111
2112static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2113 struct snd_ctl_elem_value *ucontrol)
2114{
2115 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2116 struct cmipci_sb_reg reg;
2117 int val1, val2;
2118
2119 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2120 spin_lock_irq(&cm->reg_lock);
2121 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2122 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2123 spin_unlock_irq(&cm->reg_lock);
2124 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2125 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2126 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2127 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2128 return 0;
2129}
2130
2131static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2132 struct snd_ctl_elem_value *ucontrol)
2133{
2134 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2135 struct cmipci_sb_reg reg;
2136 int change;
2137 int val1, val2, oval1, oval2;
2138
2139 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2140 spin_lock_irq(&cm->reg_lock);
2141 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2142 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2143 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2144 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2145 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2146 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2147 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2148 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2149 change = val1 != oval1 || val2 != oval2;
2150 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2151 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2152 spin_unlock_irq(&cm->reg_lock);
2153 return change;
2154}
2155
2156/*
2157 * native mixer switches/volumes
2158 */
2159
2160#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2161{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2162 .info = snd_cmipci_info_native_mixer, \
2163 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2164 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2165}
2166
2167#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2168{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2169 .info = snd_cmipci_info_native_mixer, \
2170 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2171 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2172}
2173
2174#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2175{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2176 .info = snd_cmipci_info_native_mixer, \
2177 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2178 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2179}
2180
2181#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2182{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2183 .info = snd_cmipci_info_native_mixer, \
2184 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2185 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2186}
2187
2188static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2189 struct snd_ctl_elem_info *uinfo)
2190{
2191 struct cmipci_sb_reg reg;
2192
2193 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2194 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2195 uinfo->count = reg.stereo + 1;
2196 uinfo->value.integer.min = 0;
2197 uinfo->value.integer.max = reg.mask;
2198 return 0;
2199
2200}
2201
2202static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2203 struct snd_ctl_elem_value *ucontrol)
2204{
2205 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2206 struct cmipci_sb_reg reg;
2207 unsigned char oreg, val;
2208
2209 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2210 spin_lock_irq(&cm->reg_lock);
2211 oreg = inb(cm->iobase + reg.left_reg);
2212 val = (oreg >> reg.left_shift) & reg.mask;
2213 if (reg.invert)
2214 val = reg.mask - val;
2215 ucontrol->value.integer.value[0] = val;
2216 if (reg.stereo) {
2217 val = (oreg >> reg.right_shift) & reg.mask;
2218 if (reg.invert)
2219 val = reg.mask - val;
2220 ucontrol->value.integer.value[1] = val;
2221 }
2222 spin_unlock_irq(&cm->reg_lock);
2223 return 0;
2224}
2225
2226static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2227 struct snd_ctl_elem_value *ucontrol)
2228{
2229 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2230 struct cmipci_sb_reg reg;
2231 unsigned char oreg, nreg, val;
2232
2233 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2234 spin_lock_irq(&cm->reg_lock);
2235 oreg = inb(cm->iobase + reg.left_reg);
2236 val = ucontrol->value.integer.value[0] & reg.mask;
2237 if (reg.invert)
2238 val = reg.mask - val;
2239 nreg = oreg & ~(reg.mask << reg.left_shift);
2240 nreg |= (val << reg.left_shift);
2241 if (reg.stereo) {
2242 val = ucontrol->value.integer.value[1] & reg.mask;
2243 if (reg.invert)
2244 val = reg.mask - val;
2245 nreg &= ~(reg.mask << reg.right_shift);
2246 nreg |= (val << reg.right_shift);
2247 }
2248 outb(nreg, cm->iobase + reg.left_reg);
2249 spin_unlock_irq(&cm->reg_lock);
2250 return (nreg != oreg);
2251}
2252
2253/*
2254 * special case - check mixer sensitivity
2255 */
2256static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2257 struct snd_ctl_elem_value *ucontrol)
2258{
2259 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2260 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2261}
2262
2263static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2264 struct snd_ctl_elem_value *ucontrol)
2265{
2266 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2267 if (cm->mixer_insensitive) {
2268 /* ignored */
2269 return 0;
2270 }
2271 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2272}
2273
2274
2275static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2276 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2277 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2278 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2279 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2280 { /* switch with sensitivity */
2281 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2282 .name = "PCM Playback Switch",
2283 .info = snd_cmipci_info_native_mixer,
2284 .get = snd_cmipci_get_native_mixer_sensitive,
2285 .put = snd_cmipci_put_native_mixer_sensitive,
2286 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2287 },
2288 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2289 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2290 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2291 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2292 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2293 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2294 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2295 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2296 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2297 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2298 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2299 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2300 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2301 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2302 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2303 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2304 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2305 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2306 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2307 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2308 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2309 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2310 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2311};
2312
2313/*
2314 * other switches
2315 */
2316
2317struct cmipci_switch_args {
2318 int reg; /* register index */
2319 unsigned int mask; /* mask bits */
2320 unsigned int mask_on; /* mask bits to turn on */
2321 unsigned int is_byte: 1; /* byte access? */
2322 unsigned int ac3_sensitive: 1; /* access forbidden during
2323 * non-audio operation?
2324 */
2325};
2326
2327#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2328
2329static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2330 struct snd_ctl_elem_value *ucontrol,
2331 struct cmipci_switch_args *args)
2332{
2333 unsigned int val;
2334 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2335
2336 spin_lock_irq(&cm->reg_lock);
2337 if (args->ac3_sensitive && cm->mixer_insensitive) {
2338 ucontrol->value.integer.value[0] = 0;
2339 spin_unlock_irq(&cm->reg_lock);
2340 return 0;
2341 }
2342 if (args->is_byte)
2343 val = inb(cm->iobase + args->reg);
2344 else
2345 val = snd_cmipci_read(cm, args->reg);
2346 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2347 spin_unlock_irq(&cm->reg_lock);
2348 return 0;
2349}
2350
2351static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2352 struct snd_ctl_elem_value *ucontrol)
2353{
2354 struct cmipci_switch_args *args;
2355 args = (struct cmipci_switch_args *)kcontrol->private_value;
2356 if (snd_BUG_ON(!args))
2357 return -EINVAL;
2358 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2359}
2360
2361static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2362 struct snd_ctl_elem_value *ucontrol,
2363 struct cmipci_switch_args *args)
2364{
2365 unsigned int val;
2366 int change;
2367 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2368
2369 spin_lock_irq(&cm->reg_lock);
2370 if (args->ac3_sensitive && cm->mixer_insensitive) {
2371 /* ignored */
2372 spin_unlock_irq(&cm->reg_lock);
2373 return 0;
2374 }
2375 if (args->is_byte)
2376 val = inb(cm->iobase + args->reg);
2377 else
2378 val = snd_cmipci_read(cm, args->reg);
2379 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2380 args->mask_on : (args->mask & ~args->mask_on));
2381 if (change) {
2382 val &= ~args->mask;
2383 if (ucontrol->value.integer.value[0])
2384 val |= args->mask_on;
2385 else
2386 val |= (args->mask & ~args->mask_on);
2387 if (args->is_byte)
2388 outb((unsigned char)val, cm->iobase + args->reg);
2389 else
2390 snd_cmipci_write(cm, args->reg, val);
2391 }
2392 spin_unlock_irq(&cm->reg_lock);
2393 return change;
2394}
2395
2396static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2397 struct snd_ctl_elem_value *ucontrol)
2398{
2399 struct cmipci_switch_args *args;
2400 args = (struct cmipci_switch_args *)kcontrol->private_value;
2401 if (snd_BUG_ON(!args))
2402 return -EINVAL;
2403 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2404}
2405
2406#ifndef TARGET_OS2
2407#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2408static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2409 .reg = xreg, \
2410 .mask = xmask, \
2411 .mask_on = xmask_on, \
2412 .is_byte = xis_byte, \
2413 .ac3_sensitive = xac3, \
2414}
2415#else
2416#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2417 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2418 xreg, \
2419 xmask, \
2420 xmask_on, \
2421 xis_byte, \
2422 xac3, \
2423 }
2424#endif
2425
2426#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2427 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2428
2429#if 0 /* these will be controlled in pcm device */
2430DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2431DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2432#endif
2433DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2434DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2435DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2436DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2437DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2438DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2439DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2440DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2441// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2442DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2443DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2444/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2445DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2446DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2447#if CM_CH_PLAY == 1
2448DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2449#else
2450DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2451#endif
2452DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2453// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2454// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2455// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2456DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2457
2458#define DEFINE_SWITCH(sname, stype, sarg) \
2459{ .name = sname, \
2460 .iface = stype, \
2461 .info = snd_cmipci_uswitch_info, \
2462 .get = snd_cmipci_uswitch_get, \
2463 .put = snd_cmipci_uswitch_put, \
2464 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2465}
2466
2467#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2468#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2469
2470
2471/*
2472 * callbacks for spdif output switch
2473 * needs toggle two registers..
2474 */
2475static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2476 struct snd_ctl_elem_value *ucontrol)
2477{
2478 int changed;
2479 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2480 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2481 return changed;
2482}
2483
2484static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2485 struct snd_ctl_elem_value *ucontrol)
2486{
2487 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2488 int changed;
2489 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2490 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2491 if (changed) {
2492 if (ucontrol->value.integer.value[0]) {
2493 if (chip->spdif_playback_avail)
2494 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2495 } else {
2496 if (chip->spdif_playback_avail)
2497 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2498 }
2499 }
2500 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2501 return changed;
2502}
2503
2504
2505static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2506 struct snd_ctl_elem_info *uinfo)
2507{
2508 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2509 static const char *const texts[3] = {
2510 "Line-In", "Rear Output", "Bass Output"
2511 };
2512
2513 return snd_ctl_enum_info(uinfo, 1,
2514 cm->chip_version >= 39 ? 3 : 2, texts);
2515}
2516
2517static inline unsigned int get_line_in_mode(struct cmipci *cm)
2518{
2519 unsigned int val;
2520 if (cm->chip_version >= 39) {
2521 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2522 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2523 return 2;
2524 }
2525 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2526 if (val & CM_REAR2LIN)
2527 return 1;
2528 return 0;
2529}
2530
2531static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2532 struct snd_ctl_elem_value *ucontrol)
2533{
2534 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2535
2536 spin_lock_irq(&cm->reg_lock);
2537 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2538 spin_unlock_irq(&cm->reg_lock);
2539 return 0;
2540}
2541
2542static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2543 struct snd_ctl_elem_value *ucontrol)
2544{
2545 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2546 int change;
2547
2548 spin_lock_irq(&cm->reg_lock);
2549 if (ucontrol->value.enumerated.item[0] == 2)
2550 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2551 else
2552 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2553 if (ucontrol->value.enumerated.item[0] == 1)
2554 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2555 else
2556 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2557 spin_unlock_irq(&cm->reg_lock);
2558 return change;
2559}
2560
2561static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_info *uinfo)
2563{
2564 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2565
2566 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2567}
2568
2569static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2570 struct snd_ctl_elem_value *ucontrol)
2571{
2572 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2573 /* same bit as spdi_phase */
2574 spin_lock_irq(&cm->reg_lock);
2575 ucontrol->value.enumerated.item[0] =
2576 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2577 spin_unlock_irq(&cm->reg_lock);
2578 return 0;
2579}
2580
2581static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2582 struct snd_ctl_elem_value *ucontrol)
2583{
2584 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2585 int change;
2586
2587 spin_lock_irq(&cm->reg_lock);
2588 if (ucontrol->value.enumerated.item[0])
2589 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2590 else
2591 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2592 spin_unlock_irq(&cm->reg_lock);
2593 return change;
2594}
2595
2596/* both for CM8338/8738 */
2597static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2598 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2599 {
2600 .name = "Line-In Mode",
2601 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2602 .info = snd_cmipci_line_in_mode_info,
2603 .get = snd_cmipci_line_in_mode_get,
2604 .put = snd_cmipci_line_in_mode_put,
2605 },
2606};
2607
2608/* for non-multichannel chips */
2609static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2610DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2611
2612/* only for CM8738 */
2613static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2614#if 0 /* controlled in pcm device */
2615 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2616 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2617 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2618#endif
2619 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2620 { .name = "IEC958 Output Switch",
2621 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2622 .info = snd_cmipci_uswitch_info,
2623 .get = snd_cmipci_spdout_enable_get,
2624 .put = snd_cmipci_spdout_enable_put,
2625 },
2626 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2627 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2628 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2629// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2630 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2631 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2632};
2633
2634/* only for model 033/037 */
2635static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2636 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2637 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2638 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2639};
2640
2641/* only for model 039 or later */
2642static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2643 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2644 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2645 {
2646 .name = "Mic-In Mode",
2647 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2648 .info = snd_cmipci_mic_in_mode_info,
2649 .get = snd_cmipci_mic_in_mode_get,
2650 .put = snd_cmipci_mic_in_mode_put,
2651 }
2652};
2653
2654/* card control switches */
2655static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2656DEFINE_CARD_SWITCH("Modem", modem);
2657
2658
2659static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2660{
2661 struct snd_card *card;
2662 const struct snd_kcontrol_new *sw;
2663 struct snd_kcontrol *kctl;
2664 unsigned int idx;
2665 int err;
2666
2667 if (snd_BUG_ON(!cm || !cm->card))
2668 return -EINVAL;
2669
2670 card = cm->card;
2671
2672 strcpy(card->mixername, "CMedia PCI");
2673
2674 spin_lock_irq(&cm->reg_lock);
2675 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2676 spin_unlock_irq(&cm->reg_lock);
2677
2678 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2679 if (cm->chip_version == 68) { // 8768 has no PCM volume
2680 if (!strcmp(snd_cmipci_mixers[idx].name,
2681 "PCM Playback Volume"))
2682 continue;
2683 }
2684 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2685 if (err < 0)
2686 return err;
2687 }
2688
2689 /* mixer switches */
2690 sw = snd_cmipci_mixer_switches;
2691 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2692 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2693 if (err < 0)
2694 return err;
2695 }
2696 if (! cm->can_multi_ch) {
2697 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2698 if (err < 0)
2699 return err;
2700 }
2701 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2702 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2703 sw = snd_cmipci_8738_mixer_switches;
2704 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2705 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2706 if (err < 0)
2707 return err;
2708 }
2709 if (cm->can_ac3_hw) {
2710 kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2711 err = snd_ctl_add(card, kctl);
2712 if (err < 0)
2713 return err;
2714 kctl->id.device = pcm_spdif_device;
2715 kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2716 err = snd_ctl_add(card, kctl);
2717 if (err < 0)
2718 return err;
2719 kctl->id.device = pcm_spdif_device;
2720 kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2721 err = snd_ctl_add(card, kctl);
2722 if (err < 0)
2723 return err;
2724 kctl->id.device = pcm_spdif_device;
2725 }
2726 if (cm->chip_version <= 37) {
2727 sw = snd_cmipci_old_mixer_switches;
2728 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2729 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2730 if (err < 0)
2731 return err;
2732 }
2733 }
2734 }
2735 if (cm->chip_version >= 39) {
2736 sw = snd_cmipci_extra_mixer_switches;
2737 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2738 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2739 if (err < 0)
2740 return err;
2741 }
2742 }
2743
2744 /* card switches */
2745 /*
2746 * newer chips don't have the register bits to force modem link
2747 * detection; the bit that was FLINKON now mutes CH1
2748 */
2749 if (cm->chip_version < 39) {
2750 err = snd_ctl_add(cm->card,
2751 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2752 if (err < 0)
2753 return err;
2754 }
2755
2756 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2757 struct snd_ctl_elem_id elem_id;
2758 struct snd_kcontrol *ctl;
2759 memset(&elem_id, 0, sizeof(elem_id));
2760 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2761 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2762 ctl = snd_ctl_find_id(cm->card, &elem_id);
2763 if (ctl)
2764 cm->mixer_res_ctl[idx] = ctl;
2765 }
2766
2767 return 0;
2768}
2769
2770
2771/*
2772 * proc interface
2773 */
2774
2775static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2776 struct snd_info_buffer *buffer)
2777{
2778 struct cmipci *cm = entry->private_data;
2779 int i, v;
2780
2781 snd_iprintf(buffer, "%s\n", cm->card->longname);
2782 for (i = 0; i < 0x94; i++) {
2783 if (i == 0x28)
2784 i = 0x90;
2785 v = inb(cm->iobase + i);
2786 if (i % 4 == 0)
2787 snd_iprintf(buffer, "\n%02x:", i);
2788 snd_iprintf(buffer, " %02x", v);
2789 }
2790 snd_iprintf(buffer, "\n");
2791}
2792
2793static void snd_cmipci_proc_init(struct cmipci *cm)
2794{
2795 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2796}
2797
2798static const struct pci_device_id snd_cmipci_ids[] = {
2799 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2800 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2801 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2802 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2803 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2804 {0,},
2805};
2806
2807
2808/*
2809 * check chip version and capabilities
2810 * driver name is modified according to the chip model
2811 */
2812static void query_chip(struct cmipci *cm)
2813{
2814 unsigned int detect;
2815
2816 /* check reg 0Ch, bit 24-31 */
2817 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2818 if (! detect) {
2819 /* check reg 08h, bit 24-28 */
2820 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2821 switch (detect) {
2822 case 0:
2823 cm->chip_version = 33;
2824 if (cm->do_soft_ac3)
2825 cm->can_ac3_sw = 1;
2826 else
2827 cm->can_ac3_hw = 1;
2828 break;
2829 case CM_CHIP_037:
2830 cm->chip_version = 37;
2831 cm->can_ac3_hw = 1;
2832 break;
2833 default:
2834 cm->chip_version = 39;
2835 cm->can_ac3_hw = 1;
2836 break;
2837 }
2838 cm->max_channels = 2;
2839 } else {
2840 if (detect & CM_CHIP_039) {
2841 cm->chip_version = 39;
2842 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2843 cm->max_channels = 6;
2844 else
2845 cm->max_channels = 4;
2846 } else if (detect & CM_CHIP_8768) {
2847 cm->chip_version = 68;
2848 cm->max_channels = 8;
2849 cm->can_96k = 1;
2850 } else {
2851 cm->chip_version = 55;
2852 cm->max_channels = 6;
2853 cm->can_96k = 1;
2854 }
2855 cm->can_ac3_hw = 1;
2856 cm->can_multi_ch = 1;
2857 }
2858}
2859
2860#ifdef SUPPORT_JOYSTICK
2861static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2862{
2863 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2864 struct gameport *gp;
2865 struct resource *r = NULL;
2866 int i, io_port = 0;
2867
2868 if (joystick_port[dev] == 0)
2869 return -ENODEV;
2870
2871 if (joystick_port[dev] == 1) { /* auto-detect */
2872 for (i = 0; ports[i]; i++) {
2873 io_port = ports[i];
2874 r = devm_request_region(&cm->pci->dev, io_port, 1,
2875 "CMIPCI gameport");
2876 if (r)
2877 break;
2878 }
2879 } else {
2880 io_port = joystick_port[dev];
2881 r = devm_request_region(&cm->pci->dev, io_port, 1,
2882 "CMIPCI gameport");
2883 }
2884
2885 if (!r) {
2886 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2887 return -EBUSY;
2888 }
2889
2890 cm->gameport = gp = gameport_allocate_port();
2891 if (!gp) {
2892 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2893 return -ENOMEM;
2894 }
2895 gameport_set_name(gp, "C-Media Gameport");
2896 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2897 gameport_set_dev_parent(gp, &cm->pci->dev);
2898 gp->io = io_port;
2899
2900 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2901
2902 gameport_register_port(cm->gameport);
2903
2904 return 0;
2905}
2906
2907static void snd_cmipci_free_gameport(struct cmipci *cm)
2908{
2909 if (cm->gameport) {
2910 gameport_unregister_port(cm->gameport);
2911 cm->gameport = NULL;
2912
2913 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2914 }
2915}
2916#else
2917static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2918static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2919#endif
2920
2921static void snd_cmipci_free(struct snd_card *card)
2922{
2923 struct cmipci *cm = card->private_data;
2924
2925 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2926 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2927 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2928 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2929 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2930 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2931 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2932
2933 /* reset mixer */
2934 snd_cmipci_mixer_write(cm, 0, 0);
2935
2936 snd_cmipci_free_gameport(cm);
2937}
2938
2939static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2940{
2941 long iosynth;
2942 unsigned int val;
2943 struct snd_opl3 *opl3;
2944 int err;
2945
2946 if (!fm_port)
2947 goto disable_fm;
2948
2949 if (cm->chip_version >= 39) {
2950 /* first try FM regs in PCI port range */
2951 iosynth = cm->iobase + CM_REG_FM_PCI;
2952 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2953 OPL3_HW_OPL3, 1, &opl3);
2954 } else {
2955 err = -EIO;
2956 }
2957 if (err < 0) {
2958 /* then try legacy ports */
2959 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2960 iosynth = fm_port;
2961 switch (iosynth) {
2962 case 0x3E8: val |= CM_FMSEL_3E8; break;
2963 case 0x3E0: val |= CM_FMSEL_3E0; break;
2964 case 0x3C8: val |= CM_FMSEL_3C8; break;
2965 case 0x388: val |= CM_FMSEL_388; break;
2966 default:
2967 goto disable_fm;
2968 }
2969 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2970 /* enable FM */
2971 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2972
2973 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2974 OPL3_HW_OPL3, 0, &opl3) < 0) {
2975 dev_err(cm->card->dev,
2976 "no OPL device at %#lx, skipping...\n",
2977 iosynth);
2978 goto disable_fm;
2979 }
2980 }
2981 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2982 if (err < 0) {
2983 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2984 return err;
2985 }
2986 return 0;
2987
2988 disable_fm:
2989 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2990 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2991 return 0;
2992}
2993
2994static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2995 int dev)
2996{
2997 struct cmipci *cm = card->private_data;
2998 int err;
2999 unsigned int val;
3000 long iomidi = 0;
3001 int integrated_midi = 0;
3002 char modelstr[16];
3003 int pcm_index, pcm_spdif_index;
3004 static const struct pci_device_id intel_82437vx[] = {
3005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3006 {0},
3007 };
3008
3009 err = pcim_enable_device(pci);
3010 if (err < 0)
3011 return err;
3012
3013 spin_lock_init(&cm->reg_lock);
3014 mutex_init(&cm->open_mutex);
3015 cm->device = pci->device;
3016 cm->card = card;
3017 cm->pci = pci;
3018 cm->irq = -1;
3019 cm->channel[0].ch = 0;
3020 cm->channel[1].ch = 1;
3021 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3022
3023 err = pci_request_regions(pci, card->driver);
3024 if (err < 0)
3025 return err;
3026 cm->iobase = pci_resource_start(pci, 0);
3027
3028 if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt,
3029 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3030 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3031 return -EBUSY;
3032 }
3033 cm->irq = pci->irq;
3034 card->sync_irq = cm->irq;
3035 card->private_free = snd_cmipci_free;
3036
3037 pci_set_master(cm->pci);
3038
3039 /*
3040 * check chip version, max channels and capabilities
3041 */
3042
3043 cm->chip_version = 0;
3044 cm->max_channels = 2;
3045 cm->do_soft_ac3 = soft_ac3[dev];
3046
3047 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3048 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3049 query_chip(cm);
3050 /* added -MCx suffix for chip supporting multi-channels */
3051 if (cm->can_multi_ch)
3052 sprintf(cm->card->driver + strlen(cm->card->driver),
3053 "-MC%d", cm->max_channels);
3054 else if (cm->can_ac3_sw)
3055 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3056
3057 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3058 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3059
3060#if CM_CH_PLAY == 1
3061 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3062#else
3063 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3064#endif
3065
3066 /* initialize codec registers */
3067 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3068 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3069 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3070 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3071 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3072 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3073 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3074
3075 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3076 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3077#if CM_CH_PLAY == 1
3078 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3079#else
3080 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3081#endif
3082 if (cm->chip_version) {
3083 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3084 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3085 }
3086 /* Set Bus Master Request */
3087 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3088
3089 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3090 switch (pci->device) {
3091 case PCI_DEVICE_ID_CMEDIA_CM8738:
3092 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3093 if (!pci_dev_present(intel_82437vx))
3094 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3095 break;
3096 default:
3097 break;
3098 }
3099
3100 if (cm->chip_version < 68) {
3101 val = pci->device < 0x110 ? 8338 : 8738;
3102 } else {
3103 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3104 case 0:
3105 val = 8769;
3106 break;
3107 case 2:
3108 val = 8762;
3109 break;
3110 default:
3111 switch ((pci->subsystem_vendor << 16) |
3112 pci->subsystem_device) {
3113 case 0x13f69761:
3114 case 0x584d3741:
3115 case 0x584d3751:
3116 case 0x584d3761:
3117 case 0x584d3771:
3118 case 0x72848384:
3119 val = 8770;
3120 break;
3121 default:
3122 val = 8768;
3123 break;
3124 }
3125 }
3126 }
3127 sprintf(card->shortname, "C-Media CMI%d", val);
3128 if (cm->chip_version < 68)
3129 sprintf(modelstr, " (model %d)", cm->chip_version);
3130 else
3131 modelstr[0] = '\0';
3132 sprintf(card->longname, "%s%s at %#lx, irq %i",
3133 card->shortname, modelstr, cm->iobase, cm->irq);
3134
3135 if (cm->chip_version >= 39) {
3136 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3137 if (val != 0x00 && val != 0xff) {
3138 if (mpu_port[dev])
3139 iomidi = cm->iobase + CM_REG_MPU_PCI;
3140 integrated_midi = 1;
3141 }
3142 }
3143 if (!integrated_midi) {
3144 val = 0;
3145 iomidi = mpu_port[dev];
3146 switch (iomidi) {
3147 case 0x320: val = CM_VMPU_320; break;
3148 case 0x310: val = CM_VMPU_310; break;
3149 case 0x300: val = CM_VMPU_300; break;
3150 case 0x330: val = CM_VMPU_330; break;
3151 default:
3152 iomidi = 0; break;
3153 }
3154 if (iomidi > 0) {
3155 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3156 /* enable UART */
3157 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3158 if (inb(iomidi + 1) == 0xff) {
3159 dev_err(cm->card->dev,
3160 "cannot enable MPU-401 port at %#lx\n",
3161 iomidi);
3162 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3163 CM_UART_EN);
3164 iomidi = 0;
3165 }
3166 }
3167 }
3168
3169 if (cm->chip_version < 68) {
3170 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3171 if (err < 0)
3172 return err;
3173 }
3174
3175 /* reset mixer */
3176 snd_cmipci_mixer_write(cm, 0, 0);
3177
3178 snd_cmipci_proc_init(cm);
3179
3180 /* create pcm devices */
3181 pcm_index = pcm_spdif_index = 0;
3182 err = snd_cmipci_pcm_new(cm, pcm_index);
3183 if (err < 0)
3184 return err;
3185 pcm_index++;
3186 err = snd_cmipci_pcm2_new(cm, pcm_index);
3187 if (err < 0)
3188 return err;
3189 pcm_index++;
3190 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3191 pcm_spdif_index = pcm_index;
3192 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3193 if (err < 0)
3194 return err;
3195 }
3196
3197 /* create mixer interface & switches */
3198 err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3199 if (err < 0)
3200 return err;
3201
3202 if (iomidi > 0) {
3203 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3204 iomidi,
3205 (integrated_midi ?
3206 MPU401_INFO_INTEGRATED : 0) |
3207 MPU401_INFO_IRQ_HOOK,
3208 -1, &cm->rmidi);
3209 if (err < 0)
3210 dev_err(cm->card->dev,
3211 "no UART401 device at 0x%lx\n", iomidi);
3212 }
3213
3214#ifdef USE_VAR48KRATE
3215 for (val = 0; val < ARRAY_SIZE(rates); val++)
3216 snd_cmipci_set_pll(cm, rates[val], val);
3217
3218 /*
3219 * (Re-)Enable external switch spdo_48k
3220 */
3221 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3222#endif /* USE_VAR48KRATE */
3223
3224 if (snd_cmipci_create_gameport(cm, dev) < 0)
3225 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3226
3227 return 0;
3228}
3229
3230/*
3231 */
3232
3233MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3234
3235static int snd_cmipci_probe(struct pci_dev *pci,
3236 const struct pci_device_id *pci_id)
3237{
3238 static int dev;
3239 struct snd_card *card;
3240 struct cmipci *cm;
3241 int err;
3242
3243 if (dev >= SNDRV_CARDS)
3244 return -ENODEV;
3245 if (! enable[dev]) {
3246 dev++;
3247 return -ENOENT;
3248 }
3249
3250 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3251 sizeof(*cm), &card);
3252 if (err < 0)
3253 return err;
3254 cm = card->private_data;
3255
3256 switch (pci->device) {
3257 case PCI_DEVICE_ID_CMEDIA_CM8738:
3258 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3259 strcpy(card->driver, "CMI8738");
3260 break;
3261 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3262 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3263 strcpy(card->driver, "CMI8338");
3264 break;
3265 default:
3266 strcpy(card->driver, "CMIPCI");
3267 break;
3268 }
3269
3270 err = snd_cmipci_create(card, pci, dev);
3271 if (err < 0)
3272 goto error;
3273
3274 err = snd_card_register(card);
3275 if (err < 0)
3276 goto error;
3277
3278 pci_set_drvdata(pci, card);
3279 dev++;
3280 return 0;
3281
3282 error:
3283 snd_card_free(card);
3284 return err;
3285}
3286
3287#ifdef CONFIG_PM_SLEEP
3288/*
3289 * power management
3290 */
3291static const unsigned char saved_regs[] = {
3292 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3293 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3294 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3295 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3296 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3297};
3298
3299static const unsigned char saved_mixers[] = {
3300 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3301 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3302 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3303 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3304 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3305 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3306 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3307 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3308};
3309
3310static int snd_cmipci_suspend(struct device *dev)
3311{
3312 struct snd_card *card = dev_get_drvdata(dev);
3313 struct cmipci *cm = card->private_data;
3314 int i;
3315
3316 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3317
3318 /* save registers */
3319 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3320 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3321 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3322 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3323
3324 /* disable ints */
3325 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3326 return 0;
3327}
3328
3329static int snd_cmipci_resume(struct device *dev)
3330{
3331 struct snd_card *card = dev_get_drvdata(dev);
3332 struct cmipci *cm = card->private_data;
3333 int i;
3334
3335 /* reset / initialize to a sane state */
3336 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3337 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3338 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3339 snd_cmipci_mixer_write(cm, 0, 0);
3340
3341 /* restore registers */
3342 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3343 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3344 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3345 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3346
3347 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3348 return 0;
3349}
3350
3351static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3352#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3353#else
3354#define SND_CMIPCI_PM_OPS NULL
3355#endif /* CONFIG_PM_SLEEP */
3356
3357static struct pci_driver cmipci_driver = {
3358 .name = KBUILD_MODNAME,
3359 .id_table = snd_cmipci_ids,
3360 .probe = snd_cmipci_probe,
3361 .driver = {
3362 .pm = SND_CMIPCI_PM_OPS,
3363 },
3364};
3365
3366module_pci_driver(cmipci_driver);
Note: See TracBrowser for help on using the repository browser.