source: GPL/trunk/alsa-kernel/pci/cmipci.c@ 703

Last change on this file since 703 was 703, checked in by David Azarewicz, 4 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 */
6
7/* Does not work. Warning may block system in capture mode */
8/* #define USE_VAR48KRATE */
9
10#include <linux/io.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/gameport.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <sound/core.h>
20#include <sound/info.h>
21#include <sound/control.h>
22#include <sound/pcm.h>
23#include <sound/rawmidi.h>
24#include <sound/mpu401.h>
25#include <sound/opl3.h>
26#include <sound/sb.h>
27#include <sound/asoundef.h>
28#include <sound/initval.h>
29
30#ifdef TARGET_OS2
31#define KBUILD_MODNAME "cmipci"
32#endif
33MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
34MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
35MODULE_LICENSE("GPL");
36
37#if IS_REACHABLE(CONFIG_GAMEPORT)
38#define SUPPORT_JOYSTICK 1
39#endif
40
41static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
43static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
44#ifndef TARGET_OS2
45static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
46static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
47static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
48#else
49static long mpu_port[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
50static long fm_port[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
51static bool soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
52#endif
53#ifdef SUPPORT_JOYSTICK
54static int joystick_port[SNDRV_CARDS];
55#endif
56
57module_param_array(index, int, NULL, 0444);
58MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
59module_param_array(id, charp, NULL, 0444);
60MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
61module_param_array(enable, bool, NULL, 0444);
62MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
63module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
64MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
65module_param_hw_array(fm_port, long, ioport, NULL, 0444);
66MODULE_PARM_DESC(fm_port, "FM port.");
67module_param_array(soft_ac3, bool, NULL, 0444);
68MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
69#ifdef SUPPORT_JOYSTICK
70module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
71MODULE_PARM_DESC(joystick_port, "Joystick port address.");
72#endif
73
74/*
75 * CM8x38 registers definition
76 */
77
78#define CM_REG_FUNCTRL0 0x00
79#define CM_RST_CH1 0x00080000
80#define CM_RST_CH0 0x00040000
81#define CM_CHEN1 0x00020000 /* ch1: enable */
82#define CM_CHEN0 0x00010000 /* ch0: enable */
83#define CM_PAUSE1 0x00000008 /* ch1: pause */
84#define CM_PAUSE0 0x00000004 /* ch0: pause */
85#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
86#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
87
88#define CM_REG_FUNCTRL1 0x04
89#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
90#define CM_DSFC_SHIFT 13
91#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
92#define CM_ASFC_SHIFT 10
93#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
94#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
95#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
96#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
97#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
98#define CM_BREQ 0x00000010 /* bus master enabled */
99#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
100#define CM_UART_EN 0x00000004 /* legacy UART */
101#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
102#define CM_ZVPORT 0x00000001 /* ZVPORT */
103
104#define CM_REG_CHFORMAT 0x08
105
106#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
107#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
108#define CM_CHB3D 0x20000000 /* 4 channels */
109
110#define CM_CHIP_MASK1 0x1f000000
111#define CM_CHIP_037 0x01000000
112#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
113#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
114#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
115#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
116#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
117#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
118/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
119
120#define CM_ADCBITLEN_MASK 0x0000C000
121#define CM_ADCBITLEN_16 0x00000000
122#define CM_ADCBITLEN_15 0x00004000
123#define CM_ADCBITLEN_14 0x00008000
124#define CM_ADCBITLEN_13 0x0000C000
125
126#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
127#define CM_ADCDACLEN_060 0x00000000
128#define CM_ADCDACLEN_066 0x00001000
129#define CM_ADCDACLEN_130 0x00002000
130#define CM_ADCDACLEN_280 0x00003000
131
132#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
133#define CM_ADCDLEN_ORIGINAL 0x00000000
134#define CM_ADCDLEN_EXTRA 0x00001000
135#define CM_ADCDLEN_24K 0x00002000
136#define CM_ADCDLEN_WEIGHT 0x00003000
137
138#define CM_CH1_SRATE_176K 0x00000800
139#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
140#define CM_CH1_SRATE_88K 0x00000400
141#define CM_CH0_SRATE_176K 0x00000200
142#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
143#define CM_CH0_SRATE_88K 0x00000100
144#define CM_CH0_SRATE_128K 0x00000300
145#define CM_CH0_SRATE_MASK 0x00000300
146
147#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
148#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
149#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
150#define CM_SPDLOCKED 0x00000010
151
152#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
153#define CM_CH1FMT_SHIFT 2
154#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
155#define CM_CH0FMT_SHIFT 0
156
157#define CM_REG_INT_HLDCLR 0x0C
158#define CM_CHIP_MASK2 0xff000000
159#define CM_CHIP_8768 0x20000000
160#define CM_CHIP_055 0x08000000
161#define CM_CHIP_039 0x04000000
162#define CM_CHIP_039_6CH 0x01000000
163#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
164#define CM_TDMA_INT_EN 0x00040000
165#define CM_CH1_INT_EN 0x00020000
166#define CM_CH0_INT_EN 0x00010000
167
168#define CM_REG_INT_STATUS 0x10
169#define CM_INTR 0x80000000
170#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
171#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
172#define CM_UARTINT 0x00010000
173#define CM_LTDMAINT 0x00008000
174#define CM_HTDMAINT 0x00004000
175#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
176#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
177#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
178#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
179#define CM_CH1BUSY 0x00000008
180#define CM_CH0BUSY 0x00000004
181#define CM_CHINT1 0x00000002
182#define CM_CHINT0 0x00000001
183
184#define CM_REG_LEGACY_CTRL 0x14
185#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
186#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
187#define CM_VMPU_330 0x00000000
188#define CM_VMPU_320 0x20000000
189#define CM_VMPU_310 0x40000000
190#define CM_VMPU_300 0x60000000
191#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
192#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
193#define CM_VSBSEL_220 0x00000000
194#define CM_VSBSEL_240 0x04000000
195#define CM_VSBSEL_260 0x08000000
196#define CM_VSBSEL_280 0x0C000000
197#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
198#define CM_FMSEL_388 0x00000000
199#define CM_FMSEL_3C8 0x01000000
200#define CM_FMSEL_3E0 0x02000000
201#define CM_FMSEL_3E8 0x03000000
202#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
203#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
204#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
205#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
206#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
207#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
208#define CM_C_EECS 0x00040000
209#define CM_C_EEDI46 0x00020000
210#define CM_C_EECK46 0x00010000
211#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
212#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
213#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
214#define CM_EXBASEN 0x00001000 /* external bass input enable */
215
216#define CM_REG_MISC_CTRL 0x18
217#define CM_PWD 0x80000000 /* power down */
218#define CM_RESET 0x40000000
219#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
220#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
221#define CM_TXVX 0x08000000 /* model 037? */
222#define CM_N4SPK3D 0x04000000 /* copy front to rear */
223#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
224#define CM_SPDIF48K 0x01000000 /* write */
225#define CM_SPATUS48K 0x01000000 /* read */
226#define CM_ENDBDAC 0x00800000 /* enable double dac */
227#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
228#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
229#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
230#define CM_FM_EN 0x00080000 /* enable legacy FM */
231#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
232#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
233#define CM_VIDWPDSB 0x00010000 /* model 037? */
234#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
235#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
236#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
237#define CM_VIDWPPRT 0x00002000 /* model 037? */
238#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
239#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
240#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
241#define CM_ENCENTER 0x00000080
242#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
243#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
244#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
245#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
246#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
247#define CM_UPDDMA_2048 0x00000000
248#define CM_UPDDMA_1024 0x00000004
249#define CM_UPDDMA_512 0x00000008
250#define CM_UPDDMA_256 0x0000000C
251#define CM_TWAIT_MASK 0x00000003 /* model 037 */
252#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
253#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
254
255#define CM_REG_TDMA_POSITION 0x1C
256#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
257#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
258
259 /* byte */
260#define CM_REG_MIXER0 0x20
261#define CM_REG_SBVR 0x20 /* write: sb16 version */
262#define CM_REG_DEV 0x20 /* read: hardware device version */
263
264#define CM_REG_MIXER21 0x21
265#define CM_UNKNOWN_21_MASK 0x78 /* ? */
266#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
267#define CM_PROINV 0x02 /* SBPro left/right channel switching */
268#define CM_X_SB16 0x01 /* SB16 compatible */
269
270#define CM_REG_SB16_DATA 0x22
271#define CM_REG_SB16_ADDR 0x23
272
273#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
274#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
275#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
276#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
277
278#define CM_REG_MIXER1 0x24
279#define CM_FMMUTE 0x80 /* mute FM */
280#define CM_FMMUTE_SHIFT 7
281#define CM_WSMUTE 0x40 /* mute PCM */
282#define CM_WSMUTE_SHIFT 6
283#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
284#define CM_REAR2LIN_SHIFT 5
285#define CM_REAR2FRONT 0x10 /* exchange rear/front */
286#define CM_REAR2FRONT_SHIFT 4
287#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
288#define CM_WAVEINL_SHIFT 3
289#define CM_WAVEINR 0x04 /* digical wave rec. right */
290#define CM_WAVEINR_SHIFT 2
291#define CM_X3DEN 0x02 /* 3D surround enable */
292#define CM_X3DEN_SHIFT 1
293#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
294#define CM_CDPLAY_SHIFT 0
295
296#define CM_REG_MIXER2 0x25
297#define CM_RAUXREN 0x80 /* AUX right capture */
298#define CM_RAUXREN_SHIFT 7
299#define CM_RAUXLEN 0x40 /* AUX left capture */
300#define CM_RAUXLEN_SHIFT 6
301#define CM_VAUXRM 0x20 /* AUX right mute */
302#define CM_VAUXRM_SHIFT 5
303#define CM_VAUXLM 0x10 /* AUX left mute */
304#define CM_VAUXLM_SHIFT 4
305#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
306#define CM_VADMIC_SHIFT 1
307#define CM_MICGAINZ 0x01 /* mic boost */
308#define CM_MICGAINZ_SHIFT 0
309
310#define CM_REG_MIXER3 0x24
311#define CM_REG_AUX_VOL 0x26
312#define CM_VAUXL_MASK 0xf0
313#define CM_VAUXR_MASK 0x0f
314
315#define CM_REG_MISC 0x27
316#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
317#define CM_XGPO1 0x20
318// #define CM_XGPBIO 0x04
319#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
320#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
321#define CM_SPDVALID 0x02 /* spdif input valid check */
322#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
323
324#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
325/*
326 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
327 * or identical with AC97 codec?
328 */
329#define CM_REG_EXTERN_CODEC CM_REG_AC97
330
331/*
332 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
333 */
334#define CM_REG_MPU_PCI 0x40
335
336/*
337 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
338 */
339#define CM_REG_FM_PCI 0x50
340
341/*
342 * access from SB-mixer port
343 */
344#define CM_REG_EXTENT_IND 0xf0
345#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
346#define CM_VPHONE_SHIFT 5
347#define CM_VPHOM 0x10 /* Phone mute control */
348#define CM_VSPKM 0x08 /* Speaker mute control, default high */
349#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
350#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
351#define CM_VADMIC3 0x01 /* Mic record boost */
352
353/*
354 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
355 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
356 * unit (readonly?).
357 */
358#define CM_REG_PLL 0xf8
359
360/*
361 * extended registers
362 */
363#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
364#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
365#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
366#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
367
368#define CM_REG_EXT_MISC 0x90
369#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
370#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
371#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
372#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
373#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
374#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
375#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
376#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
377
378/*
379 * size of i/o region
380 */
381#define CM_EXTENT_CODEC 0x100
382#define CM_EXTENT_MIDI 0x2
383#define CM_EXTENT_SYNTH 0x4
384
385
386/*
387 * channels for playback / capture
388 */
389#define CM_CH_PLAY 0
390#define CM_CH_CAPT 1
391
392/*
393 * flags to check device open/close
394 */
395#define CM_OPEN_NONE 0
396#define CM_OPEN_CH_MASK 0x01
397#define CM_OPEN_DAC 0x10
398#define CM_OPEN_ADC 0x20
399#define CM_OPEN_SPDIF 0x40
400#define CM_OPEN_MCHAN 0x80
401#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
402#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
403#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
404#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
405#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
406#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
407
408
409#if CM_CH_PLAY == 1
410#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
411#define CM_PLAYBACK_SPDF CM_SPDF_1
412#define CM_CAPTURE_SPDF CM_SPDF_0
413#else
414#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
415#define CM_PLAYBACK_SPDF CM_SPDF_0
416#define CM_CAPTURE_SPDF CM_SPDF_1
417#endif
418
419
420/*
421 * driver data
422 */
423
424struct cmipci_pcm {
425 struct snd_pcm_substream *substream;
426 u8 running; /* dac/adc running? */
427 u8 fmt; /* format bits */
428 u8 is_dac;
429 u8 needs_silencing;
430 unsigned int dma_size; /* in frames */
431 unsigned int shift;
432 unsigned int ch; /* channel (0/1) */
433 unsigned int offset; /* physical address of the buffer */
434};
435
436/* mixer elements toggled/resumed during ac3 playback */
437struct cmipci_mixer_auto_switches {
438 const char *name; /* switch to toggle */
439 int toggle_on; /* value to change when ac3 mode */
440};
441static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
442 {"PCM Playback Switch", 0},
443 {"IEC958 Output Switch", 1},
444 {"IEC958 Mix Analog", 0},
445 // {"IEC958 Out To DAC", 1}, // no longer used
446 {"IEC958 Loop", 0},
447};
448#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
449
450struct cmipci {
451 struct snd_card *card;
452
453 struct pci_dev *pci;
454 unsigned int device; /* device ID */
455 int irq;
456
457 unsigned long iobase;
458 unsigned int ctrl; /* FUNCTRL0 current value */
459
460 struct snd_pcm *pcm; /* DAC/ADC PCM */
461 struct snd_pcm *pcm2; /* 2nd DAC */
462 struct snd_pcm *pcm_spdif; /* SPDIF */
463
464 int chip_version;
465 int max_channels;
466 unsigned int can_ac3_sw: 1;
467 unsigned int can_ac3_hw: 1;
468 unsigned int can_multi_ch: 1;
469 unsigned int can_96k: 1; /* samplerate above 48k */
470 unsigned int do_soft_ac3: 1;
471
472 unsigned int spdif_playback_avail: 1; /* spdif ready? */
473 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
474 int spdif_counter; /* for software AC3 */
475
476 unsigned int dig_status;
477 unsigned int dig_pcm_status;
478
479 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
480
481 int opened[2]; /* open mode */
482 struct mutex open_mutex;
483
484 unsigned int mixer_insensitive: 1;
485 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
486 int mixer_res_status[CM_SAVED_MIXERS];
487
488 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
489
490 /* external MIDI */
491 struct snd_rawmidi *rmidi;
492
493#ifdef SUPPORT_JOYSTICK
494 struct gameport *gameport;
495#endif
496
497 spinlock_t reg_lock;
498
499#ifdef CONFIG_PM_SLEEP
500 unsigned int saved_regs[0x20];
501 unsigned char saved_mixers[0x20];
502#endif
503};
504
505
506/* read/write operations for dword register */
507static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
508{
509 outl(data, cm->iobase + cmd);
510}
511
512static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
513{
514 return inl(cm->iobase + cmd);
515}
516
517/* read/write operations for word register */
518static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
519{
520 outw(data, cm->iobase + cmd);
521}
522
523static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
524{
525 return inw(cm->iobase + cmd);
526}
527
528/* read/write operations for byte register */
529static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
530{
531 outb(data, cm->iobase + cmd);
532}
533
534static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
535{
536 return inb(cm->iobase + cmd);
537}
538
539/* bit operations for dword register */
540static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
541{
542 unsigned int val, oval;
543 val = oval = inl(cm->iobase + cmd);
544 val |= flag;
545 if (val == oval)
546 return 0;
547 outl(val, cm->iobase + cmd);
548 return 1;
549}
550
551static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
552{
553 unsigned int val, oval;
554 val = oval = inl(cm->iobase + cmd);
555 val &= ~flag;
556 if (val == oval)
557 return 0;
558 outl(val, cm->iobase + cmd);
559 return 1;
560}
561
562/* bit operations for byte register */
563static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
564{
565 unsigned char val, oval;
566 val = oval = inb(cm->iobase + cmd);
567 val |= flag;
568 if (val == oval)
569 return 0;
570 outb(val, cm->iobase + cmd);
571 return 1;
572}
573
574static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
575{
576 unsigned char val, oval;
577 val = oval = inb(cm->iobase + cmd);
578 val &= ~flag;
579 if (val == oval)
580 return 0;
581 outb(val, cm->iobase + cmd);
582 return 1;
583}
584
585
586/*
587 * PCM interface
588 */
589
590/*
591 * calculate frequency
592 */
593
594static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
595
596static unsigned int snd_cmipci_rate_freq(unsigned int rate)
597{
598 unsigned int i;
599
600 for (i = 0; i < ARRAY_SIZE(rates); i++) {
601 if (rates[i] == rate)
602 return i;
603 }
604 snd_BUG();
605 return 0;
606}
607
608#ifdef USE_VAR48KRATE
609/*
610 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
611 * does it this way .. maybe not. Never get any information from C-Media about
612 * that <werner@suse.de>.
613 */
614static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
615{
616 unsigned int delta, tolerance;
617 int xm, xn, xr;
618
619 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
620 rate <<= 1;
621 *n = -1;
622 if (*r > 0xff)
623 goto out;
624 tolerance = rate*CM_TOLERANCE_RATE;
625
626 for (xn = (1+2); xn < (0x1f+2); xn++) {
627 for (xm = (1+2); xm < (0xff+2); xm++) {
628 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
629
630 if (xr < rate)
631 delta = rate - xr;
632 else
633 delta = xr - rate;
634
635 /*
636 * If we found one, remember this,
637 * and try to find a closer one
638 */
639 if (delta < tolerance) {
640 tolerance = delta;
641 *m = xm - 2;
642 *n = xn - 2;
643 }
644 }
645 }
646out:
647 return (*n > -1);
648}
649
650/*
651 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
652 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
653 * at the register CM_REG_FUNCTRL1 (0x04).
654 * Problem: other ways are also possible (any information about that?)
655 */
656static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
657{
658 unsigned int reg = CM_REG_PLL + slot;
659 /*
660 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
661 * for DSFC/ASFC (000 up to 111).
662 */
663
664 /* FIXME: Init (Do we've to set an other register first before programming?) */
665
666 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
667 snd_cmipci_write_b(cm, reg, rate>>8);
668 snd_cmipci_write_b(cm, reg, rate&0xff);
669
670 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
671}
672#endif /* USE_VAR48KRATE */
673
674static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
675 struct snd_pcm_hw_params *hw_params)
676{
677 struct cmipci *cm = snd_pcm_substream_chip(substream);
678 if (params_channels(hw_params) > 2) {
679 mutex_lock(&cm->open_mutex);
680 if (cm->opened[CM_CH_PLAY]) {
681 mutex_unlock(&cm->open_mutex);
682 return -EBUSY;
683 }
684 /* reserve the channel A */
685 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
686 mutex_unlock(&cm->open_mutex);
687 }
688 return 0;
689}
690
691static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
692{
693 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
694 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
695 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
696 udelay(10);
697}
698
699
700/*
701 */
702
703static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
704static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
705 .count = 3,
706 .list = hw_channels,
707 .mask = 0,
708};
709static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
710 .count = 4,
711 .list = hw_channels,
712 .mask = 0,
713};
714static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
715 .count = 5,
716 .list = hw_channels,
717 .mask = 0,
718};
719
720static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
721{
722 if (channels > 2) {
723 if (!cm->can_multi_ch || !rec->ch)
724 return -EINVAL;
725 if (rec->fmt != 0x03) /* stereo 16bit only */
726 return -EINVAL;
727 }
728
729 if (cm->can_multi_ch) {
730 spin_lock_irq(&cm->reg_lock);
731 if (channels > 2) {
732 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
733 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
734 } else {
735 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
736 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
737 }
738 if (channels == 8)
739 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
740 else
741 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
742 if (channels == 6) {
743 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
744 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
745 } else {
746 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
747 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
748 }
749 if (channels == 4)
750 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
751 else
752 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
753 spin_unlock_irq(&cm->reg_lock);
754 }
755 return 0;
756}
757
758
759/*
760 * prepare playback/capture channel
761 * channel to be used must have been set in rec->ch.
762 */
763static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
764 struct snd_pcm_substream *substream)
765{
766 unsigned int reg, freq, freq_ext, val;
767 unsigned int period_size;
768 struct snd_pcm_runtime *runtime = substream->runtime;
769
770 rec->fmt = 0;
771 rec->shift = 0;
772 if (snd_pcm_format_width(runtime->format) >= 16) {
773 rec->fmt |= 0x02;
774 if (snd_pcm_format_width(runtime->format) > 16)
775 rec->shift++; /* 24/32bit */
776 }
777 if (runtime->channels > 1)
778 rec->fmt |= 0x01;
779 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
780 dev_dbg(cm->card->dev, "cannot set dac channels\n");
781 return -EINVAL;
782 }
783
784 rec->offset = runtime->dma_addr;
785 /* buffer and period sizes in frame */
786 rec->dma_size = runtime->buffer_size << rec->shift;
787 period_size = runtime->period_size << rec->shift;
788 if (runtime->channels > 2) {
789 /* multi-channels */
790 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
791 period_size = (period_size * runtime->channels) / 2;
792 }
793
794 spin_lock_irq(&cm->reg_lock);
795
796 /* set buffer address */
797 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
798 snd_cmipci_write(cm, reg, rec->offset);
799 /* program sample counts */
800 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
801 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
802 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
803
804 /* set adc/dac flag */
805 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
806 if (rec->is_dac)
807 cm->ctrl &= ~val;
808 else
809 cm->ctrl |= val;
810 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
811 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
812
813 /* set sample rate */
814 freq = 0;
815 freq_ext = 0;
816 if (runtime->rate > 48000)
817 switch (runtime->rate) {
818 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
819 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
820 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
821 default: snd_BUG(); break;
822 }
823 else
824 freq = snd_cmipci_rate_freq(runtime->rate);
825 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
826 if (rec->ch) {
827 val &= ~CM_DSFC_MASK;
828 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
829 } else {
830 val &= ~CM_ASFC_MASK;
831 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
832 }
833 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
834 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
835
836 /* set format */
837 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
838 if (rec->ch) {
839 val &= ~CM_CH1FMT_MASK;
840 val |= rec->fmt << CM_CH1FMT_SHIFT;
841 } else {
842 val &= ~CM_CH0FMT_MASK;
843 val |= rec->fmt << CM_CH0FMT_SHIFT;
844 }
845 if (cm->can_96k) {
846 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
847 val |= freq_ext << (rec->ch * 2);
848 }
849 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
850 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
851
852 if (!rec->is_dac && cm->chip_version) {
853 if (runtime->rate > 44100)
854 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
855 else
856 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
857 }
858
859 rec->running = 0;
860 spin_unlock_irq(&cm->reg_lock);
861
862 return 0;
863}
864
865/*
866 * PCM trigger/stop
867 */
868static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
869 int cmd)
870{
871 unsigned int inthld, chen, reset, pause;
872 int result = 0;
873
874 inthld = CM_CH0_INT_EN << rec->ch;
875 chen = CM_CHEN0 << rec->ch;
876 reset = CM_RST_CH0 << rec->ch;
877 pause = CM_PAUSE0 << rec->ch;
878
879 spin_lock(&cm->reg_lock);
880 switch (cmd) {
881 case SNDRV_PCM_TRIGGER_START:
882 rec->running = 1;
883 /* set interrupt */
884 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
885 cm->ctrl |= chen;
886 /* enable channel */
887 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
888 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
889 break;
890 case SNDRV_PCM_TRIGGER_STOP:
891 rec->running = 0;
892 /* disable interrupt */
893 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
894 /* reset */
895 cm->ctrl &= ~chen;
896 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
897 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
898 rec->needs_silencing = rec->is_dac;
899 break;
900 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
901 case SNDRV_PCM_TRIGGER_SUSPEND:
902 cm->ctrl |= pause;
903 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
904 break;
905 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
906 case SNDRV_PCM_TRIGGER_RESUME:
907 cm->ctrl &= ~pause;
908 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
909 break;
910 default:
911 result = -EINVAL;
912 break;
913 }
914 spin_unlock(&cm->reg_lock);
915 return result;
916}
917
918/*
919 * return the current pointer
920 */
921static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
922 struct snd_pcm_substream *substream)
923{
924 size_t ptr;
925 unsigned int reg, rem, tries;
926
927 if (!rec->running)
928 return 0;
929#if 1 // this seems better..
930 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
931 for (tries = 0; tries < 3; tries++) {
932 rem = snd_cmipci_read_w(cm, reg);
933 if (rem < rec->dma_size)
934 goto ok;
935 }
936 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
937 return SNDRV_PCM_POS_XRUN;
938ok:
939 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
940#else
941 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
942 ptr = snd_cmipci_read(cm, reg) - rec->offset;
943 ptr = bytes_to_frames(substream->runtime, ptr);
944#endif
945 if (substream->runtime->channels > 2)
946 ptr = (ptr * 2) / substream->runtime->channels;
947 return ptr;
948}
949
950/*
951 * playback
952 */
953
954static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
955 int cmd)
956{
957 struct cmipci *cm = snd_pcm_substream_chip(substream);
958 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
959}
960
961static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
962{
963 struct cmipci *cm = snd_pcm_substream_chip(substream);
964 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
965}
966
967
968
969/*
970 * capture
971 */
972
973static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
974 int cmd)
975{
976 struct cmipci *cm = snd_pcm_substream_chip(substream);
977 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
978}
979
980static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
981{
982 struct cmipci *cm = snd_pcm_substream_chip(substream);
983 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
984}
985
986
987/*
988 * hw preparation for spdif
989 */
990
991static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
992 struct snd_ctl_elem_info *uinfo)
993{
994 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
995 uinfo->count = 1;
996 return 0;
997}
998
999static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1003 int i;
1004
1005 spin_lock_irq(&chip->reg_lock);
1006 for (i = 0; i < 4; i++)
1007 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1008 spin_unlock_irq(&chip->reg_lock);
1009 return 0;
1010}
1011
1012static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1013 struct snd_ctl_elem_value *ucontrol)
1014{
1015 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1016 int i, change;
1017 unsigned int val;
1018
1019 val = 0;
1020 spin_lock_irq(&chip->reg_lock);
1021 for (i = 0; i < 4; i++)
1022 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1023 change = val != chip->dig_status;
1024 chip->dig_status = val;
1025 spin_unlock_irq(&chip->reg_lock);
1026 return change;
1027}
1028
1029static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1030{
1031 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1032 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1033 .info = snd_cmipci_spdif_default_info,
1034 .get = snd_cmipci_spdif_default_get,
1035 .put = snd_cmipci_spdif_default_put
1036};
1037
1038static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_info *uinfo)
1040{
1041 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1042 uinfo->count = 1;
1043 return 0;
1044}
1045
1046static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1048{
1049 ucontrol->value.iec958.status[0] = 0xff;
1050 ucontrol->value.iec958.status[1] = 0xff;
1051 ucontrol->value.iec958.status[2] = 0xff;
1052 ucontrol->value.iec958.status[3] = 0xff;
1053 return 0;
1054}
1055
1056static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1057{
1058 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1059 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1060 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1061 .info = snd_cmipci_spdif_mask_info,
1062 .get = snd_cmipci_spdif_mask_get,
1063};
1064
1065static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1066 struct snd_ctl_elem_info *uinfo)
1067{
1068 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1069 uinfo->count = 1;
1070 return 0;
1071}
1072
1073static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1074 struct snd_ctl_elem_value *ucontrol)
1075{
1076 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1077 int i;
1078
1079 spin_lock_irq(&chip->reg_lock);
1080 for (i = 0; i < 4; i++)
1081 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1082 spin_unlock_irq(&chip->reg_lock);
1083 return 0;
1084}
1085
1086static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1087 struct snd_ctl_elem_value *ucontrol)
1088{
1089 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1090 int i, change;
1091 unsigned int val;
1092
1093 val = 0;
1094 spin_lock_irq(&chip->reg_lock);
1095 for (i = 0; i < 4; i++)
1096 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1097 change = val != chip->dig_pcm_status;
1098 chip->dig_pcm_status = val;
1099 spin_unlock_irq(&chip->reg_lock);
1100 return change;
1101}
1102
1103static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1104{
1105 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1106 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1107 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1108 .info = snd_cmipci_spdif_stream_info,
1109 .get = snd_cmipci_spdif_stream_get,
1110 .put = snd_cmipci_spdif_stream_put
1111};
1112
1113/*
1114 */
1115
1116/* save mixer setting and mute for AC3 playback */
1117static int save_mixer_state(struct cmipci *cm)
1118{
1119 if (! cm->mixer_insensitive) {
1120 struct snd_ctl_elem_value *val;
1121 unsigned int i;
1122
1123 val = kmalloc(sizeof(*val), GFP_KERNEL);
1124 if (!val)
1125 return -ENOMEM;
1126 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1127 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1128 if (ctl) {
1129 int event;
1130 memset(val, 0, sizeof(*val));
1131 ctl->get(ctl, val);
1132 cm->mixer_res_status[i] = val->value.integer.value[0];
1133 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1134 event = SNDRV_CTL_EVENT_MASK_INFO;
1135 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1136 ctl->put(ctl, val); /* toggle */
1137 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1138 }
1139 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1140 snd_ctl_notify(cm->card, event, &ctl->id);
1141 }
1142 }
1143 kfree(val);
1144 cm->mixer_insensitive = 1;
1145 }
1146 return 0;
1147}
1148
1149
1150/* restore the previously saved mixer status */
1151static void restore_mixer_state(struct cmipci *cm)
1152{
1153 if (cm->mixer_insensitive) {
1154 struct snd_ctl_elem_value *val;
1155 unsigned int i;
1156
1157 val = kmalloc(sizeof(*val), GFP_KERNEL);
1158 if (!val)
1159 return;
1160 cm->mixer_insensitive = 0; /* at first clear this;
1161 otherwise the changes will be ignored */
1162 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1163 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1164 if (ctl) {
1165 int event;
1166
1167 memset(val, 0, sizeof(*val));
1168 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1169 ctl->get(ctl, val);
1170 event = SNDRV_CTL_EVENT_MASK_INFO;
1171 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1172 val->value.integer.value[0] = cm->mixer_res_status[i];
1173 ctl->put(ctl, val);
1174 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1175 }
1176 snd_ctl_notify(cm->card, event, &ctl->id);
1177 }
1178 }
1179 kfree(val);
1180 }
1181}
1182
1183/* spinlock held! */
1184static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1185{
1186 if (do_ac3) {
1187 /* AC3EN for 037 */
1188 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1189 /* AC3EN for 039 */
1190 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1191
1192 if (cm->can_ac3_hw) {
1193 /* SPD24SEL for 037, 0x02 */
1194 /* SPD24SEL for 039, 0x20, but cannot be set */
1195 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1196 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1197 } else { /* can_ac3_sw */
1198 /* SPD32SEL for 037 & 039, 0x20 */
1199 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1200 /* set 176K sample rate to fix 033 HW bug */
1201 if (cm->chip_version == 33) {
1202 if (rate >= 48000) {
1203 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1204 } else {
1205 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1206 }
1207 }
1208 }
1209
1210 } else {
1211 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1212 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1213
1214 if (cm->can_ac3_hw) {
1215 /* chip model >= 37 */
1216 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1217 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1218 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1219 } else {
1220 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1222 }
1223 } else {
1224 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1225 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1226 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1227 }
1228 }
1229}
1230
1231static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1232{
1233 int rate, err;
1234
1235 rate = subs->runtime->rate;
1236
1237 if (up && do_ac3) {
1238 err = save_mixer_state(cm);
1239 if (err < 0)
1240 return err;
1241 }
1242
1243 spin_lock_irq(&cm->reg_lock);
1244 cm->spdif_playback_avail = up;
1245 if (up) {
1246 /* they are controlled via "IEC958 Output Switch" */
1247 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1248 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1249 if (cm->spdif_playback_enabled)
1250 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1251 setup_ac3(cm, subs, do_ac3, rate);
1252
1253 if (rate == 48000 || rate == 96000)
1254 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1255 else
1256 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1257 if (rate > 48000)
1258 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1259 else
1260 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1261 } else {
1262 /* they are controlled via "IEC958 Output Switch" */
1263 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1264 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1265 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1266 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1267 setup_ac3(cm, subs, 0, 0);
1268 }
1269 spin_unlock_irq(&cm->reg_lock);
1270 return 0;
1271}
1272
1273
1274/*
1275 * preparation
1276 */
1277
1278/* playback - enable spdif only on the certain condition */
1279static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1280{
1281 struct cmipci *cm = snd_pcm_substream_chip(substream);
1282 int rate = substream->runtime->rate;
1283 int err, do_spdif, do_ac3 = 0;
1284
1285 do_spdif = (rate >= 44100 && rate <= 96000 &&
1286 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1287 substream->runtime->channels == 2);
1288 if (do_spdif && cm->can_ac3_hw)
1289 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1290 err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1291 if (err < 0)
1292 return err;
1293 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1294}
1295
1296/* playback (via device #2) - enable spdif always */
1297static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1298{
1299 struct cmipci *cm = snd_pcm_substream_chip(substream);
1300 int err, do_ac3;
1301
1302 if (cm->can_ac3_hw)
1303 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1304 else
1305 do_ac3 = 1; /* doesn't matter */
1306 err = setup_spdif_playback(cm, substream, 1, do_ac3);
1307 if (err < 0)
1308 return err;
1309 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1310}
1311
1312/*
1313 * Apparently, the samples last played on channel A stay in some buffer, even
1314 * after the channel is reset, and get added to the data for the rear DACs when
1315 * playing a multichannel stream on channel B. This is likely to generate
1316 * wraparounds and thus distortions.
1317 * To avoid this, we play at least one zero sample after the actual stream has
1318 * stopped.
1319 */
1320static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1321{
1322 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1323 unsigned int reg, val;
1324
1325 if (rec->needs_silencing && runtime && runtime->dma_area) {
1326 /* set up a small silence buffer */
1327 memset(runtime->dma_area, 0, PAGE_SIZE);
1328 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1329 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1330 snd_cmipci_write(cm, reg, val);
1331
1332 /* configure for 16 bits, 2 channels, 8 kHz */
1333 if (runtime->channels > 2)
1334 set_dac_channels(cm, rec, 2);
1335 spin_lock_irq(&cm->reg_lock);
1336 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1337 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1338 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1339 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1340 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1341 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1342 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1343 if (cm->can_96k)
1344 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1345 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1346
1347 /* start stream (we don't need interrupts) */
1348 cm->ctrl |= CM_CHEN0 << rec->ch;
1349 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1350 spin_unlock_irq(&cm->reg_lock);
1351
1352 msleep(1);
1353
1354 /* stop and reset stream */
1355 spin_lock_irq(&cm->reg_lock);
1356 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1357 val = CM_RST_CH0 << rec->ch;
1358 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1359 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1360 spin_unlock_irq(&cm->reg_lock);
1361
1362 rec->needs_silencing = 0;
1363 }
1364}
1365
1366static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1367{
1368 struct cmipci *cm = snd_pcm_substream_chip(substream);
1369 setup_spdif_playback(cm, substream, 0, 0);
1370 restore_mixer_state(cm);
1371 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1372 return 0;
1373}
1374
1375static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1376{
1377 struct cmipci *cm = snd_pcm_substream_chip(substream);
1378 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1379 return 0;
1380}
1381
1382/* capture */
1383static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1384{
1385 struct cmipci *cm = snd_pcm_substream_chip(substream);
1386 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1387}
1388
1389/* capture with spdif (via device #2) */
1390static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1391{
1392 struct cmipci *cm = snd_pcm_substream_chip(substream);
1393
1394 spin_lock_irq(&cm->reg_lock);
1395 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1396 if (cm->can_96k) {
1397 if (substream->runtime->rate > 48000)
1398 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1399 else
1400 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1401 }
1402 if (snd_pcm_format_width(substream->runtime->format) > 16)
1403 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1404 else
1405 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1406
1407 spin_unlock_irq(&cm->reg_lock);
1408
1409 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1410}
1411
1412static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1413{
1414 struct cmipci *cm = snd_pcm_substream_chip(subs);
1415
1416 spin_lock_irq(&cm->reg_lock);
1417 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1418 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1419 spin_unlock_irq(&cm->reg_lock);
1420
1421 return 0;
1422}
1423
1424
1425/*
1426 * interrupt handler
1427 */
1428static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1429{
1430 struct cmipci *cm = dev_id;
1431 unsigned int status, mask = 0;
1432
1433 /* fastpath out, to ease interrupt sharing */
1434 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1435 if (!(status & CM_INTR))
1436 return IRQ_NONE;
1437
1438 /* acknowledge interrupt */
1439 spin_lock(&cm->reg_lock);
1440 if (status & CM_CHINT0)
1441 mask |= CM_CH0_INT_EN;
1442 if (status & CM_CHINT1)
1443 mask |= CM_CH1_INT_EN;
1444 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1445 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1446 spin_unlock(&cm->reg_lock);
1447
1448 if (cm->rmidi && (status & CM_UARTINT))
1449 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1450
1451 if (cm->pcm) {
1452 if ((status & CM_CHINT0) && cm->channel[0].running)
1453 snd_pcm_period_elapsed(cm->channel[0].substream);
1454 if ((status & CM_CHINT1) && cm->channel[1].running)
1455 snd_pcm_period_elapsed(cm->channel[1].substream);
1456 }
1457 return IRQ_HANDLED;
1458}
1459
1460/*
1461 * h/w infos
1462 */
1463
1464/* playback on channel A */
1465static const struct snd_pcm_hardware snd_cmipci_playback =
1466{
1467 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1468 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1469 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1470 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1471 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1472 .rate_min = 5512,
1473 .rate_max = 48000,
1474 .channels_min = 1,
1475 .channels_max = 2,
1476 .buffer_bytes_max = (128*1024),
1477 .period_bytes_min = 64,
1478 .period_bytes_max = (128*1024),
1479 .periods_min = 2,
1480 .periods_max = 1024,
1481 .fifo_size = 0,
1482};
1483
1484/* capture on channel B */
1485static const struct snd_pcm_hardware snd_cmipci_capture =
1486{
1487 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1488 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1489 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1490 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1491 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1492 .rate_min = 5512,
1493 .rate_max = 48000,
1494 .channels_min = 1,
1495 .channels_max = 2,
1496 .buffer_bytes_max = (128*1024),
1497 .period_bytes_min = 64,
1498 .period_bytes_max = (128*1024),
1499 .periods_min = 2,
1500 .periods_max = 1024,
1501 .fifo_size = 0,
1502};
1503
1504/* playback on channel B - stereo 16bit only? */
1505static const struct snd_pcm_hardware snd_cmipci_playback2 =
1506{
1507 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1508 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1509 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1510 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1511 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1512 .rate_min = 5512,
1513 .rate_max = 48000,
1514 .channels_min = 2,
1515 .channels_max = 2,
1516 .buffer_bytes_max = (128*1024),
1517 .period_bytes_min = 64,
1518 .period_bytes_max = (128*1024),
1519 .periods_min = 2,
1520 .periods_max = 1024,
1521 .fifo_size = 0,
1522};
1523
1524/* spdif playback on channel A */
1525static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1526{
1527 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1528 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1529 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1530 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1531 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1532 .rate_min = 44100,
1533 .rate_max = 48000,
1534 .channels_min = 2,
1535 .channels_max = 2,
1536 .buffer_bytes_max = (128*1024),
1537 .period_bytes_min = 64,
1538 .period_bytes_max = (128*1024),
1539 .periods_min = 2,
1540 .periods_max = 1024,
1541 .fifo_size = 0,
1542};
1543
1544/* spdif playback on channel A (32bit, IEC958 subframes) */
1545static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1546{
1547 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1548 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1549 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1550 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1551 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1552 .rate_min = 44100,
1553 .rate_max = 48000,
1554 .channels_min = 2,
1555 .channels_max = 2,
1556 .buffer_bytes_max = (128*1024),
1557 .period_bytes_min = 64,
1558 .period_bytes_max = (128*1024),
1559 .periods_min = 2,
1560 .periods_max = 1024,
1561 .fifo_size = 0,
1562};
1563
1564/* spdif capture on channel B */
1565static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1566{
1567 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1568 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1569 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1570 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1571 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1572 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1573 .rate_min = 44100,
1574 .rate_max = 48000,
1575 .channels_min = 2,
1576 .channels_max = 2,
1577 .buffer_bytes_max = (128*1024),
1578 .period_bytes_min = 64,
1579 .period_bytes_max = (128*1024),
1580 .periods_min = 2,
1581 .periods_max = 1024,
1582 .fifo_size = 0,
1583};
1584
1585static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1586 32000, 44100, 48000, 88200, 96000, 128000 };
1587static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1588 .count = ARRAY_SIZE(rate_constraints),
1589 .list = rate_constraints,
1590 .mask = 0,
1591};
1592
1593/*
1594 * check device open/close
1595 */
1596static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1597{
1598 int ch = mode & CM_OPEN_CH_MASK;
1599
1600 /* FIXME: a file should wait until the device becomes free
1601 * when it's opened on blocking mode. however, since the current
1602 * pcm framework doesn't pass file pointer before actually opened,
1603 * we can't know whether blocking mode or not in open callback..
1604 */
1605 mutex_lock(&cm->open_mutex);
1606 if (cm->opened[ch]) {
1607 mutex_unlock(&cm->open_mutex);
1608 return -EBUSY;
1609 }
1610 cm->opened[ch] = mode;
1611 cm->channel[ch].substream = subs;
1612 if (! (mode & CM_OPEN_DAC)) {
1613 /* disable dual DAC mode */
1614 cm->channel[ch].is_dac = 0;
1615 spin_lock_irq(&cm->reg_lock);
1616 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1617 spin_unlock_irq(&cm->reg_lock);
1618 }
1619 mutex_unlock(&cm->open_mutex);
1620 return 0;
1621}
1622
1623static void close_device_check(struct cmipci *cm, int mode)
1624{
1625 int ch = mode & CM_OPEN_CH_MASK;
1626
1627 mutex_lock(&cm->open_mutex);
1628 if (cm->opened[ch] == mode) {
1629 if (cm->channel[ch].substream) {
1630 snd_cmipci_ch_reset(cm, ch);
1631 cm->channel[ch].running = 0;
1632 cm->channel[ch].substream = NULL;
1633 }
1634 cm->opened[ch] = 0;
1635 if (! cm->channel[ch].is_dac) {
1636 /* enable dual DAC mode again */
1637 cm->channel[ch].is_dac = 1;
1638 spin_lock_irq(&cm->reg_lock);
1639 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1640 spin_unlock_irq(&cm->reg_lock);
1641 }
1642 }
1643 mutex_unlock(&cm->open_mutex);
1644}
1645
1646/*
1647 */
1648
1649static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1650{
1651 struct cmipci *cm = snd_pcm_substream_chip(substream);
1652 struct snd_pcm_runtime *runtime = substream->runtime;
1653 int err;
1654
1655 err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1656 if (err < 0)
1657 return err;
1658 runtime->hw = snd_cmipci_playback;
1659 if (cm->chip_version == 68) {
1660 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1661 SNDRV_PCM_RATE_96000;
1662 runtime->hw.rate_max = 96000;
1663 } else if (cm->chip_version == 55) {
1664 err = snd_pcm_hw_constraint_list(runtime, 0,
1665 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1666 if (err < 0)
1667 return err;
1668 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1669 runtime->hw.rate_max = 128000;
1670 }
1671 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1672 cm->dig_pcm_status = cm->dig_status;
1673 return 0;
1674}
1675
1676static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1677{
1678 struct cmipci *cm = snd_pcm_substream_chip(substream);
1679 struct snd_pcm_runtime *runtime = substream->runtime;
1680 int err;
1681
1682 err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1683 if (err < 0)
1684 return err;
1685 runtime->hw = snd_cmipci_capture;
1686 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1687 runtime->hw.rate_min = 41000;
1688 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1689 } else if (cm->chip_version == 55) {
1690 err = snd_pcm_hw_constraint_list(runtime, 0,
1691 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1692 if (err < 0)
1693 return err;
1694 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1695 runtime->hw.rate_max = 128000;
1696 }
1697 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1698 return 0;
1699}
1700
1701static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1702{
1703 struct cmipci *cm = snd_pcm_substream_chip(substream);
1704 struct snd_pcm_runtime *runtime = substream->runtime;
1705 int err;
1706
1707 /* use channel B */
1708 err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1709 if (err < 0)
1710 return err;
1711 runtime->hw = snd_cmipci_playback2;
1712 mutex_lock(&cm->open_mutex);
1713 if (! cm->opened[CM_CH_PLAY]) {
1714 if (cm->can_multi_ch) {
1715 runtime->hw.channels_max = cm->max_channels;
1716 if (cm->max_channels == 4)
1717 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1718 else if (cm->max_channels == 6)
1719 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1720 else if (cm->max_channels == 8)
1721 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1722 }
1723 }
1724 mutex_unlock(&cm->open_mutex);
1725 if (cm->chip_version == 68) {
1726 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1727 SNDRV_PCM_RATE_96000;
1728 runtime->hw.rate_max = 96000;
1729 } else if (cm->chip_version == 55) {
1730 err = snd_pcm_hw_constraint_list(runtime, 0,
1731 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1732 if (err < 0)
1733 return err;
1734 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1735 runtime->hw.rate_max = 128000;
1736 }
1737 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1738 return 0;
1739}
1740
1741static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1742{
1743 struct cmipci *cm = snd_pcm_substream_chip(substream);
1744 struct snd_pcm_runtime *runtime = substream->runtime;
1745 int err;
1746
1747 /* use channel A */
1748 err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1749 if (err < 0)
1750 return err;
1751 if (cm->can_ac3_hw) {
1752 runtime->hw = snd_cmipci_playback_spdif;
1753 if (cm->chip_version >= 37) {
1754 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1755 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1756 }
1757 if (cm->can_96k) {
1758 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1759 SNDRV_PCM_RATE_96000;
1760 runtime->hw.rate_max = 96000;
1761 }
1762 } else {
1763 runtime->hw = snd_cmipci_playback_iec958_subframe;
1764 }
1765 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1766 cm->dig_pcm_status = cm->dig_status;
1767 return 0;
1768}
1769
1770static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1771{
1772 struct cmipci *cm = snd_pcm_substream_chip(substream);
1773 struct snd_pcm_runtime *runtime = substream->runtime;
1774 int err;
1775
1776 /* use channel B */
1777 err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1778 if (err < 0)
1779 return err;
1780 runtime->hw = snd_cmipci_capture_spdif;
1781 if (cm->can_96k && !(cm->chip_version == 68)) {
1782 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1783 SNDRV_PCM_RATE_96000;
1784 runtime->hw.rate_max = 96000;
1785 }
1786 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1787 return 0;
1788}
1789
1790
1791/*
1792 */
1793
1794static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1795{
1796 struct cmipci *cm = snd_pcm_substream_chip(substream);
1797 close_device_check(cm, CM_OPEN_PLAYBACK);
1798 return 0;
1799}
1800
1801static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1802{
1803 struct cmipci *cm = snd_pcm_substream_chip(substream);
1804 close_device_check(cm, CM_OPEN_CAPTURE);
1805 return 0;
1806}
1807
1808static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1809{
1810 struct cmipci *cm = snd_pcm_substream_chip(substream);
1811 close_device_check(cm, CM_OPEN_PLAYBACK2);
1812 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1813 return 0;
1814}
1815
1816static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1817{
1818 struct cmipci *cm = snd_pcm_substream_chip(substream);
1819 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1820 return 0;
1821}
1822
1823static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1824{
1825 struct cmipci *cm = snd_pcm_substream_chip(substream);
1826 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1827 return 0;
1828}
1829
1830
1831/*
1832 */
1833
1834static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1835 .open = snd_cmipci_playback_open,
1836 .close = snd_cmipci_playback_close,
1837 .hw_free = snd_cmipci_playback_hw_free,
1838 .prepare = snd_cmipci_playback_prepare,
1839 .trigger = snd_cmipci_playback_trigger,
1840 .pointer = snd_cmipci_playback_pointer,
1841};
1842
1843static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1844 .open = snd_cmipci_capture_open,
1845 .close = snd_cmipci_capture_close,
1846 .prepare = snd_cmipci_capture_prepare,
1847 .trigger = snd_cmipci_capture_trigger,
1848 .pointer = snd_cmipci_capture_pointer,
1849};
1850
1851static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1852 .open = snd_cmipci_playback2_open,
1853 .close = snd_cmipci_playback2_close,
1854 .hw_params = snd_cmipci_playback2_hw_params,
1855 .hw_free = snd_cmipci_playback2_hw_free,
1856 .prepare = snd_cmipci_capture_prepare, /* channel B */
1857 .trigger = snd_cmipci_capture_trigger, /* channel B */
1858 .pointer = snd_cmipci_capture_pointer, /* channel B */
1859};
1860
1861static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1862 .open = snd_cmipci_playback_spdif_open,
1863 .close = snd_cmipci_playback_spdif_close,
1864 .hw_free = snd_cmipci_playback_hw_free,
1865 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1866 .trigger = snd_cmipci_playback_trigger,
1867 .pointer = snd_cmipci_playback_pointer,
1868};
1869
1870static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1871 .open = snd_cmipci_capture_spdif_open,
1872 .close = snd_cmipci_capture_spdif_close,
1873 .hw_free = snd_cmipci_capture_spdif_hw_free,
1874 .prepare = snd_cmipci_capture_spdif_prepare,
1875 .trigger = snd_cmipci_capture_trigger,
1876 .pointer = snd_cmipci_capture_pointer,
1877};
1878
1879
1880/*
1881 */
1882
1883static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1884{
1885 struct snd_pcm *pcm;
1886 int err;
1887
1888 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1889 if (err < 0)
1890 return err;
1891
1892 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1893 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1894
1895 pcm->private_data = cm;
1896 pcm->info_flags = 0;
1897 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1898 cm->pcm = pcm;
1899
1900 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1901 &cm->pci->dev, 64*1024, 128*1024);
1902
1903 return 0;
1904}
1905
1906static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1907{
1908 struct snd_pcm *pcm;
1909 int err;
1910
1911 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1912 if (err < 0)
1913 return err;
1914
1915 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1916
1917 pcm->private_data = cm;
1918 pcm->info_flags = 0;
1919 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1920 cm->pcm2 = pcm;
1921
1922 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1923 &cm->pci->dev, 64*1024, 128*1024);
1924
1925 return 0;
1926}
1927
1928static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1929{
1930 struct snd_pcm *pcm;
1931 int err;
1932
1933 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1934 if (err < 0)
1935 return err;
1936
1937 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1938 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1939
1940 pcm->private_data = cm;
1941 pcm->info_flags = 0;
1942 strcpy(pcm->name, "C-Media PCI IEC958");
1943 cm->pcm_spdif = pcm;
1944
1945 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1946 &cm->pci->dev, 64*1024, 128*1024);
1947
1948 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1949 snd_pcm_alt_chmaps, cm->max_channels, 0,
1950 NULL);
1951 if (err < 0)
1952 return err;
1953
1954 return 0;
1955}
1956
1957/*
1958 * mixer interface:
1959 * - CM8338/8738 has a compatible mixer interface with SB16, but
1960 * lack of some elements like tone control, i/o gain and AGC.
1961 * - Access to native registers:
1962 * - A 3D switch
1963 * - Output mute switches
1964 */
1965
1966static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1967{
1968 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1969 outb(data, s->iobase + CM_REG_SB16_DATA);
1970}
1971
1972static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1973{
1974 unsigned char v;
1975
1976 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1977 v = inb(s->iobase + CM_REG_SB16_DATA);
1978 return v;
1979}
1980
1981/*
1982 * general mixer element
1983 */
1984struct cmipci_sb_reg {
1985 unsigned int left_reg, right_reg;
1986 unsigned int left_shift, right_shift;
1987 unsigned int mask;
1988 unsigned int invert: 1;
1989 unsigned int stereo: 1;
1990};
1991
1992#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1993 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1994
1995#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1996{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1997 .info = snd_cmipci_info_volume, \
1998 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1999 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2000}
2001
2002#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2003#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2004#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2005#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2006
2007static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2008{
2009 r->left_reg = val & 0xff;
2010 r->right_reg = (val >> 8) & 0xff;
2011 r->left_shift = (val >> 16) & 0x07;
2012 r->right_shift = (val >> 19) & 0x07;
2013 r->invert = (val >> 22) & 1;
2014 r->stereo = (val >> 23) & 1;
2015 r->mask = (val >> 24) & 0xff;
2016}
2017
2018static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_info *uinfo)
2020{
2021 struct cmipci_sb_reg reg;
2022
2023 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2024 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2025 uinfo->count = reg.stereo + 1;
2026 uinfo->value.integer.min = 0;
2027 uinfo->value.integer.max = reg.mask;
2028 return 0;
2029}
2030
2031static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2032 struct snd_ctl_elem_value *ucontrol)
2033{
2034 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2035 struct cmipci_sb_reg reg;
2036 int val;
2037
2038 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2039 spin_lock_irq(&cm->reg_lock);
2040 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2041 if (reg.invert)
2042 val = reg.mask - val;
2043 ucontrol->value.integer.value[0] = val;
2044 if (reg.stereo) {
2045 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2046 if (reg.invert)
2047 val = reg.mask - val;
2048 ucontrol->value.integer.value[1] = val;
2049 }
2050 spin_unlock_irq(&cm->reg_lock);
2051 return 0;
2052}
2053
2054static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2055 struct snd_ctl_elem_value *ucontrol)
2056{
2057 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2058 struct cmipci_sb_reg reg;
2059 int change;
2060 int left, right, oleft, oright;
2061
2062 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2063 left = ucontrol->value.integer.value[0] & reg.mask;
2064 if (reg.invert)
2065 left = reg.mask - left;
2066 left <<= reg.left_shift;
2067 if (reg.stereo) {
2068 right = ucontrol->value.integer.value[1] & reg.mask;
2069 if (reg.invert)
2070 right = reg.mask - right;
2071 right <<= reg.right_shift;
2072 } else
2073 right = 0;
2074 spin_lock_irq(&cm->reg_lock);
2075 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2076 left |= oleft & ~(reg.mask << reg.left_shift);
2077 change = left != oleft;
2078 if (reg.stereo) {
2079 if (reg.left_reg != reg.right_reg) {
2080 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2081 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2082 } else
2083 oright = left;
2084 right |= oright & ~(reg.mask << reg.right_shift);
2085 change |= right != oright;
2086 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2087 } else
2088 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2089 spin_unlock_irq(&cm->reg_lock);
2090 return change;
2091}
2092
2093/*
2094 * input route (left,right) -> (left,right)
2095 */
2096#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2097{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2098 .info = snd_cmipci_info_input_sw, \
2099 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2100 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2101}
2102
2103static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2104 struct snd_ctl_elem_info *uinfo)
2105{
2106 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2107 uinfo->count = 4;
2108 uinfo->value.integer.min = 0;
2109 uinfo->value.integer.max = 1;
2110 return 0;
2111}
2112
2113static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2114 struct snd_ctl_elem_value *ucontrol)
2115{
2116 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2117 struct cmipci_sb_reg reg;
2118 int val1, val2;
2119
2120 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2121 spin_lock_irq(&cm->reg_lock);
2122 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2123 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2124 spin_unlock_irq(&cm->reg_lock);
2125 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2126 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2127 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2128 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2129 return 0;
2130}
2131
2132static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2133 struct snd_ctl_elem_value *ucontrol)
2134{
2135 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2136 struct cmipci_sb_reg reg;
2137 int change;
2138 int val1, val2, oval1, oval2;
2139
2140 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2141 spin_lock_irq(&cm->reg_lock);
2142 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2143 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2144 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2145 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2146 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2147 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2148 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2149 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2150 change = val1 != oval1 || val2 != oval2;
2151 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2152 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2153 spin_unlock_irq(&cm->reg_lock);
2154 return change;
2155}
2156
2157/*
2158 * native mixer switches/volumes
2159 */
2160
2161#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2162{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2163 .info = snd_cmipci_info_native_mixer, \
2164 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2165 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2166}
2167
2168#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2169{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2170 .info = snd_cmipci_info_native_mixer, \
2171 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2172 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2173}
2174
2175#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2176{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2177 .info = snd_cmipci_info_native_mixer, \
2178 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2179 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2180}
2181
2182#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2183{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2184 .info = snd_cmipci_info_native_mixer, \
2185 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2186 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2187}
2188
2189static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2190 struct snd_ctl_elem_info *uinfo)
2191{
2192 struct cmipci_sb_reg reg;
2193
2194 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2195 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2196 uinfo->count = reg.stereo + 1;
2197 uinfo->value.integer.min = 0;
2198 uinfo->value.integer.max = reg.mask;
2199 return 0;
2200
2201}
2202
2203static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2204 struct snd_ctl_elem_value *ucontrol)
2205{
2206 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2207 struct cmipci_sb_reg reg;
2208 unsigned char oreg, val;
2209
2210 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2211 spin_lock_irq(&cm->reg_lock);
2212 oreg = inb(cm->iobase + reg.left_reg);
2213 val = (oreg >> reg.left_shift) & reg.mask;
2214 if (reg.invert)
2215 val = reg.mask - val;
2216 ucontrol->value.integer.value[0] = val;
2217 if (reg.stereo) {
2218 val = (oreg >> reg.right_shift) & reg.mask;
2219 if (reg.invert)
2220 val = reg.mask - val;
2221 ucontrol->value.integer.value[1] = val;
2222 }
2223 spin_unlock_irq(&cm->reg_lock);
2224 return 0;
2225}
2226
2227static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2228 struct snd_ctl_elem_value *ucontrol)
2229{
2230 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2231 struct cmipci_sb_reg reg;
2232 unsigned char oreg, nreg, val;
2233
2234 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2235 spin_lock_irq(&cm->reg_lock);
2236 oreg = inb(cm->iobase + reg.left_reg);
2237 val = ucontrol->value.integer.value[0] & reg.mask;
2238 if (reg.invert)
2239 val = reg.mask - val;
2240 nreg = oreg & ~(reg.mask << reg.left_shift);
2241 nreg |= (val << reg.left_shift);
2242 if (reg.stereo) {
2243 val = ucontrol->value.integer.value[1] & reg.mask;
2244 if (reg.invert)
2245 val = reg.mask - val;
2246 nreg &= ~(reg.mask << reg.right_shift);
2247 nreg |= (val << reg.right_shift);
2248 }
2249 outb(nreg, cm->iobase + reg.left_reg);
2250 spin_unlock_irq(&cm->reg_lock);
2251 return (nreg != oreg);
2252}
2253
2254/*
2255 * special case - check mixer sensitivity
2256 */
2257static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2258 struct snd_ctl_elem_value *ucontrol)
2259{
2260 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2261 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2262}
2263
2264static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2265 struct snd_ctl_elem_value *ucontrol)
2266{
2267 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2268 if (cm->mixer_insensitive) {
2269 /* ignored */
2270 return 0;
2271 }
2272 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2273}
2274
2275
2276static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2277 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2278 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2279 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2280 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2281 { /* switch with sensitivity */
2282 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2283 .name = "PCM Playback Switch",
2284 .info = snd_cmipci_info_native_mixer,
2285 .get = snd_cmipci_get_native_mixer_sensitive,
2286 .put = snd_cmipci_put_native_mixer_sensitive,
2287 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2288 },
2289 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2290 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2291 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2292 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2293 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2294 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2295 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2296 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2297 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2298 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2299 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2300 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2301 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2302 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2303 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2304 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2305 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2306 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2307 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2308 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2309 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2310 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2311 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2312};
2313
2314/*
2315 * other switches
2316 */
2317
2318struct cmipci_switch_args {
2319 int reg; /* register index */
2320 unsigned int mask; /* mask bits */
2321 unsigned int mask_on; /* mask bits to turn on */
2322 unsigned int is_byte: 1; /* byte access? */
2323 unsigned int ac3_sensitive: 1; /* access forbidden during
2324 * non-audio operation?
2325 */
2326};
2327
2328#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2329
2330static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2331 struct snd_ctl_elem_value *ucontrol,
2332 struct cmipci_switch_args *args)
2333{
2334 unsigned int val;
2335 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2336
2337 spin_lock_irq(&cm->reg_lock);
2338 if (args->ac3_sensitive && cm->mixer_insensitive) {
2339 ucontrol->value.integer.value[0] = 0;
2340 spin_unlock_irq(&cm->reg_lock);
2341 return 0;
2342 }
2343 if (args->is_byte)
2344 val = inb(cm->iobase + args->reg);
2345 else
2346 val = snd_cmipci_read(cm, args->reg);
2347 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2348 spin_unlock_irq(&cm->reg_lock);
2349 return 0;
2350}
2351
2352static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2353 struct snd_ctl_elem_value *ucontrol)
2354{
2355 struct cmipci_switch_args *args;
2356 args = (struct cmipci_switch_args *)kcontrol->private_value;
2357 if (snd_BUG_ON(!args))
2358 return -EINVAL;
2359 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2360}
2361
2362static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2363 struct snd_ctl_elem_value *ucontrol,
2364 struct cmipci_switch_args *args)
2365{
2366 unsigned int val;
2367 int change;
2368 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2369
2370 spin_lock_irq(&cm->reg_lock);
2371 if (args->ac3_sensitive && cm->mixer_insensitive) {
2372 /* ignored */
2373 spin_unlock_irq(&cm->reg_lock);
2374 return 0;
2375 }
2376 if (args->is_byte)
2377 val = inb(cm->iobase + args->reg);
2378 else
2379 val = snd_cmipci_read(cm, args->reg);
2380 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2381 args->mask_on : (args->mask & ~args->mask_on));
2382 if (change) {
2383 val &= ~args->mask;
2384 if (ucontrol->value.integer.value[0])
2385 val |= args->mask_on;
2386 else
2387 val |= (args->mask & ~args->mask_on);
2388 if (args->is_byte)
2389 outb((unsigned char)val, cm->iobase + args->reg);
2390 else
2391 snd_cmipci_write(cm, args->reg, val);
2392 }
2393 spin_unlock_irq(&cm->reg_lock);
2394 return change;
2395}
2396
2397static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2398 struct snd_ctl_elem_value *ucontrol)
2399{
2400 struct cmipci_switch_args *args;
2401 args = (struct cmipci_switch_args *)kcontrol->private_value;
2402 if (snd_BUG_ON(!args))
2403 return -EINVAL;
2404 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2405}
2406
2407#ifndef TARGET_OS2
2408#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2409static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2410 .reg = xreg, \
2411 .mask = xmask, \
2412 .mask_on = xmask_on, \
2413 .is_byte = xis_byte, \
2414 .ac3_sensitive = xac3, \
2415}
2416#else
2417#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2418 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2419 xreg, \
2420 xmask, \
2421 xmask_on, \
2422 xis_byte, \
2423 xac3, \
2424 }
2425#endif
2426
2427#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2428 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2429
2430#if 0 /* these will be controlled in pcm device */
2431DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2432DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2433#endif
2434DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2435DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2436DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2437DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2438DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2439DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2440DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2441DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2442// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2443DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2444DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2445/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2446DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2447DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2448#if CM_CH_PLAY == 1
2449DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2450#else
2451DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2452#endif
2453DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2454// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2455// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2456// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2457DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2458
2459#define DEFINE_SWITCH(sname, stype, sarg) \
2460{ .name = sname, \
2461 .iface = stype, \
2462 .info = snd_cmipci_uswitch_info, \
2463 .get = snd_cmipci_uswitch_get, \
2464 .put = snd_cmipci_uswitch_put, \
2465 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2466}
2467
2468#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2469#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2470
2471
2472/*
2473 * callbacks for spdif output switch
2474 * needs toggle two registers..
2475 */
2476static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2477 struct snd_ctl_elem_value *ucontrol)
2478{
2479 int changed;
2480 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2481 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2482 return changed;
2483}
2484
2485static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2486 struct snd_ctl_elem_value *ucontrol)
2487{
2488 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2489 int changed;
2490 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2491 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2492 if (changed) {
2493 if (ucontrol->value.integer.value[0]) {
2494 if (chip->spdif_playback_avail)
2495 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2496 } else {
2497 if (chip->spdif_playback_avail)
2498 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2499 }
2500 }
2501 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2502 return changed;
2503}
2504
2505
2506static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2507 struct snd_ctl_elem_info *uinfo)
2508{
2509 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2510 static const char *const texts[3] = {
2511 "Line-In", "Rear Output", "Bass Output"
2512 };
2513
2514 return snd_ctl_enum_info(uinfo, 1,
2515 cm->chip_version >= 39 ? 3 : 2, texts);
2516}
2517
2518static inline unsigned int get_line_in_mode(struct cmipci *cm)
2519{
2520 unsigned int val;
2521 if (cm->chip_version >= 39) {
2522 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2523 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2524 return 2;
2525 }
2526 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2527 if (val & CM_REAR2LIN)
2528 return 1;
2529 return 0;
2530}
2531
2532static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2533 struct snd_ctl_elem_value *ucontrol)
2534{
2535 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2536
2537 spin_lock_irq(&cm->reg_lock);
2538 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2539 spin_unlock_irq(&cm->reg_lock);
2540 return 0;
2541}
2542
2543static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2544 struct snd_ctl_elem_value *ucontrol)
2545{
2546 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2547 int change;
2548
2549 spin_lock_irq(&cm->reg_lock);
2550 if (ucontrol->value.enumerated.item[0] == 2)
2551 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2552 else
2553 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2554 if (ucontrol->value.enumerated.item[0] == 1)
2555 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2556 else
2557 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2558 spin_unlock_irq(&cm->reg_lock);
2559 return change;
2560}
2561
2562static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2563 struct snd_ctl_elem_info *uinfo)
2564{
2565 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2566
2567 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2568}
2569
2570static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2571 struct snd_ctl_elem_value *ucontrol)
2572{
2573 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2574 /* same bit as spdi_phase */
2575 spin_lock_irq(&cm->reg_lock);
2576 ucontrol->value.enumerated.item[0] =
2577 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2578 spin_unlock_irq(&cm->reg_lock);
2579 return 0;
2580}
2581
2582static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2583 struct snd_ctl_elem_value *ucontrol)
2584{
2585 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2586 int change;
2587
2588 spin_lock_irq(&cm->reg_lock);
2589 if (ucontrol->value.enumerated.item[0])
2590 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2591 else
2592 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2593 spin_unlock_irq(&cm->reg_lock);
2594 return change;
2595}
2596
2597/* both for CM8338/8738 */
2598static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2599 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2600 {
2601 .name = "Line-In Mode",
2602 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2603 .info = snd_cmipci_line_in_mode_info,
2604 .get = snd_cmipci_line_in_mode_get,
2605 .put = snd_cmipci_line_in_mode_put,
2606 },
2607};
2608
2609/* for non-multichannel chips */
2610static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2611DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2612
2613/* only for CM8738 */
2614static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2615#if 0 /* controlled in pcm device */
2616 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2617 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2618 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2619#endif
2620 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2621 { .name = "IEC958 Output Switch",
2622 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2623 .info = snd_cmipci_uswitch_info,
2624 .get = snd_cmipci_spdout_enable_get,
2625 .put = snd_cmipci_spdout_enable_put,
2626 },
2627 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2628 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2629 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2630// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2631 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2632 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2633};
2634
2635/* only for model 033/037 */
2636static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2637 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2638 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2639 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2640};
2641
2642/* only for model 039 or later */
2643static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2644 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2645 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2646 {
2647 .name = "Mic-In Mode",
2648 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2649 .info = snd_cmipci_mic_in_mode_info,
2650 .get = snd_cmipci_mic_in_mode_get,
2651 .put = snd_cmipci_mic_in_mode_put,
2652 }
2653};
2654
2655/* card control switches */
2656static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2657DEFINE_CARD_SWITCH("Modem", modem);
2658
2659
2660static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2661{
2662 struct snd_card *card;
2663 const struct snd_kcontrol_new *sw;
2664 struct snd_kcontrol *kctl;
2665 unsigned int idx;
2666 int err;
2667
2668 if (snd_BUG_ON(!cm || !cm->card))
2669 return -EINVAL;
2670
2671 card = cm->card;
2672
2673 strcpy(card->mixername, "CMedia PCI");
2674
2675 spin_lock_irq(&cm->reg_lock);
2676 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2677 spin_unlock_irq(&cm->reg_lock);
2678
2679 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2680 if (cm->chip_version == 68) { // 8768 has no PCM volume
2681 if (!strcmp(snd_cmipci_mixers[idx].name,
2682 "PCM Playback Volume"))
2683 continue;
2684 }
2685 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2686 if (err < 0)
2687 return err;
2688 }
2689
2690 /* mixer switches */
2691 sw = snd_cmipci_mixer_switches;
2692 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2693 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2694 if (err < 0)
2695 return err;
2696 }
2697 if (! cm->can_multi_ch) {
2698 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2699 if (err < 0)
2700 return err;
2701 }
2702 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2703 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2704 sw = snd_cmipci_8738_mixer_switches;
2705 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2706 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2707 if (err < 0)
2708 return err;
2709 }
2710 if (cm->can_ac3_hw) {
2711 kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2712 err = snd_ctl_add(card, kctl);
2713 if (err < 0)
2714 return err;
2715 kctl->id.device = pcm_spdif_device;
2716 kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2717 err = snd_ctl_add(card, kctl);
2718 if (err < 0)
2719 return err;
2720 kctl->id.device = pcm_spdif_device;
2721 kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2722 err = snd_ctl_add(card, kctl);
2723 if (err < 0)
2724 return err;
2725 kctl->id.device = pcm_spdif_device;
2726 }
2727 if (cm->chip_version <= 37) {
2728 sw = snd_cmipci_old_mixer_switches;
2729 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2730 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2731 if (err < 0)
2732 return err;
2733 }
2734 }
2735 }
2736 if (cm->chip_version >= 39) {
2737 sw = snd_cmipci_extra_mixer_switches;
2738 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2739 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2740 if (err < 0)
2741 return err;
2742 }
2743 }
2744
2745 /* card switches */
2746 /*
2747 * newer chips don't have the register bits to force modem link
2748 * detection; the bit that was FLINKON now mutes CH1
2749 */
2750 if (cm->chip_version < 39) {
2751 err = snd_ctl_add(cm->card,
2752 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2753 if (err < 0)
2754 return err;
2755 }
2756
2757 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2758 struct snd_ctl_elem_id elem_id;
2759 struct snd_kcontrol *ctl;
2760 memset(&elem_id, 0, sizeof(elem_id));
2761 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2762 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2763 ctl = snd_ctl_find_id(cm->card, &elem_id);
2764 if (ctl)
2765 cm->mixer_res_ctl[idx] = ctl;
2766 }
2767
2768 return 0;
2769}
2770
2771
2772/*
2773 * proc interface
2774 */
2775
2776static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2777 struct snd_info_buffer *buffer)
2778{
2779 struct cmipci *cm = entry->private_data;
2780 int i, v;
2781
2782 snd_iprintf(buffer, "%s\n", cm->card->longname);
2783 for (i = 0; i < 0x94; i++) {
2784 if (i == 0x28)
2785 i = 0x90;
2786 v = inb(cm->iobase + i);
2787 if (i % 4 == 0)
2788 snd_iprintf(buffer, "\n%02x:", i);
2789 snd_iprintf(buffer, " %02x", v);
2790 }
2791 snd_iprintf(buffer, "\n");
2792}
2793
2794static void snd_cmipci_proc_init(struct cmipci *cm)
2795{
2796 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2797}
2798
2799static const struct pci_device_id snd_cmipci_ids[] = {
2800 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2801 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2802 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2803 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2804 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2805 {0,},
2806};
2807
2808
2809/*
2810 * check chip version and capabilities
2811 * driver name is modified according to the chip model
2812 */
2813static void query_chip(struct cmipci *cm)
2814{
2815 unsigned int detect;
2816
2817 /* check reg 0Ch, bit 24-31 */
2818 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2819 if (! detect) {
2820 /* check reg 08h, bit 24-28 */
2821 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2822 switch (detect) {
2823 case 0:
2824 cm->chip_version = 33;
2825 if (cm->do_soft_ac3)
2826 cm->can_ac3_sw = 1;
2827 else
2828 cm->can_ac3_hw = 1;
2829 break;
2830 case CM_CHIP_037:
2831 cm->chip_version = 37;
2832 cm->can_ac3_hw = 1;
2833 break;
2834 default:
2835 cm->chip_version = 39;
2836 cm->can_ac3_hw = 1;
2837 break;
2838 }
2839 cm->max_channels = 2;
2840 } else {
2841 if (detect & CM_CHIP_039) {
2842 cm->chip_version = 39;
2843 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2844 cm->max_channels = 6;
2845 else
2846 cm->max_channels = 4;
2847 } else if (detect & CM_CHIP_8768) {
2848 cm->chip_version = 68;
2849 cm->max_channels = 8;
2850 cm->can_96k = 1;
2851 } else {
2852 cm->chip_version = 55;
2853 cm->max_channels = 6;
2854 cm->can_96k = 1;
2855 }
2856 cm->can_ac3_hw = 1;
2857 cm->can_multi_ch = 1;
2858 }
2859}
2860
2861#ifdef SUPPORT_JOYSTICK
2862static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2863{
2864 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2865 struct gameport *gp;
2866 struct resource *r = NULL;
2867 int i, io_port = 0;
2868
2869 if (joystick_port[dev] == 0)
2870 return -ENODEV;
2871
2872 if (joystick_port[dev] == 1) { /* auto-detect */
2873 for (i = 0; ports[i]; i++) {
2874 io_port = ports[i];
2875 r = request_region(io_port, 1, "CMIPCI gameport");
2876 if (r)
2877 break;
2878 }
2879 } else {
2880 io_port = joystick_port[dev];
2881 r = request_region(io_port, 1, "CMIPCI gameport");
2882 }
2883
2884 if (!r) {
2885 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2886 return -EBUSY;
2887 }
2888
2889 cm->gameport = gp = gameport_allocate_port();
2890 if (!gp) {
2891 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2892 release_and_free_resource(r);
2893 return -ENOMEM;
2894 }
2895 gameport_set_name(gp, "C-Media Gameport");
2896 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2897 gameport_set_dev_parent(gp, &cm->pci->dev);
2898 gp->io = io_port;
2899 gameport_set_port_data(gp, r);
2900
2901 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2902
2903 gameport_register_port(cm->gameport);
2904
2905 return 0;
2906}
2907
2908static void snd_cmipci_free_gameport(struct cmipci *cm)
2909{
2910 if (cm->gameport) {
2911 struct resource *r = gameport_get_port_data(cm->gameport);
2912
2913 gameport_unregister_port(cm->gameport);
2914 cm->gameport = NULL;
2915
2916 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2917 release_and_free_resource(r);
2918 }
2919}
2920#else
2921static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2922static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2923#endif
2924
2925static int snd_cmipci_free(struct cmipci *cm)
2926{
2927 if (cm->irq >= 0) {
2928 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2929 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2930 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2931 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2932 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2933 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2934 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2935
2936 /* reset mixer */
2937 snd_cmipci_mixer_write(cm, 0, 0);
2938
2939 free_irq(cm->irq, cm);
2940 }
2941
2942 snd_cmipci_free_gameport(cm);
2943 pci_release_regions(cm->pci);
2944 pci_disable_device(cm->pci);
2945 kfree(cm);
2946 return 0;
2947}
2948
2949static int snd_cmipci_dev_free(struct snd_device *device)
2950{
2951 struct cmipci *cm = device->device_data;
2952 return snd_cmipci_free(cm);
2953}
2954
2955static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2956{
2957 long iosynth;
2958 unsigned int val;
2959 struct snd_opl3 *opl3;
2960 int err;
2961
2962 if (!fm_port)
2963 goto disable_fm;
2964
2965 if (cm->chip_version >= 39) {
2966 /* first try FM regs in PCI port range */
2967 iosynth = cm->iobase + CM_REG_FM_PCI;
2968 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2969 OPL3_HW_OPL3, 1, &opl3);
2970 } else {
2971 err = -EIO;
2972 }
2973 if (err < 0) {
2974 /* then try legacy ports */
2975 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2976 iosynth = fm_port;
2977 switch (iosynth) {
2978 case 0x3E8: val |= CM_FMSEL_3E8; break;
2979 case 0x3E0: val |= CM_FMSEL_3E0; break;
2980 case 0x3C8: val |= CM_FMSEL_3C8; break;
2981 case 0x388: val |= CM_FMSEL_388; break;
2982 default:
2983 goto disable_fm;
2984 }
2985 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2986 /* enable FM */
2987 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2988
2989 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2990 OPL3_HW_OPL3, 0, &opl3) < 0) {
2991 dev_err(cm->card->dev,
2992 "no OPL device at %#lx, skipping...\n",
2993 iosynth);
2994 goto disable_fm;
2995 }
2996 }
2997 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2998 if (err < 0) {
2999 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
3000 return err;
3001 }
3002 return 0;
3003
3004 disable_fm:
3005 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3006 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3007 return 0;
3008}
3009
3010static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3011 int dev, struct cmipci **rcmipci)
3012{
3013 struct cmipci *cm;
3014 int err;
3015 static const struct snd_device_ops ops = {
3016 .dev_free = snd_cmipci_dev_free,
3017 };
3018 unsigned int val;
3019 long iomidi = 0;
3020 int integrated_midi = 0;
3021 char modelstr[16];
3022 int pcm_index, pcm_spdif_index;
3023 static const struct pci_device_id intel_82437vx[] = {
3024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3025 {0},
3026 };
3027
3028 *rcmipci = NULL;
3029
3030 err = pci_enable_device(pci);
3031 if (err < 0)
3032 return err;
3033
3034 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3035 if (cm == NULL) {
3036 pci_disable_device(pci);
3037 return -ENOMEM;
3038 }
3039
3040 spin_lock_init(&cm->reg_lock);
3041 mutex_init(&cm->open_mutex);
3042 cm->device = pci->device;
3043 cm->card = card;
3044 cm->pci = pci;
3045 cm->irq = -1;
3046 cm->channel[0].ch = 0;
3047 cm->channel[1].ch = 1;
3048 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3049
3050 err = pci_request_regions(pci, card->driver);
3051 if (err < 0) {
3052 kfree(cm);
3053 pci_disable_device(pci);
3054 return err;
3055 }
3056 cm->iobase = pci_resource_start(pci, 0);
3057
3058 if (request_irq(pci->irq, snd_cmipci_interrupt,
3059 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3060 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3061 snd_cmipci_free(cm);
3062 return -EBUSY;
3063 }
3064 cm->irq = pci->irq;
3065 card->sync_irq = cm->irq;
3066
3067 pci_set_master(cm->pci);
3068
3069 /*
3070 * check chip version, max channels and capabilities
3071 */
3072
3073 cm->chip_version = 0;
3074 cm->max_channels = 2;
3075 cm->do_soft_ac3 = soft_ac3[dev];
3076
3077 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3078 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3079 query_chip(cm);
3080 /* added -MCx suffix for chip supporting multi-channels */
3081 if (cm->can_multi_ch)
3082 sprintf(cm->card->driver + strlen(cm->card->driver),
3083 "-MC%d", cm->max_channels);
3084 else if (cm->can_ac3_sw)
3085 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3086
3087 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3088 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3089
3090#if CM_CH_PLAY == 1
3091 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3092#else
3093 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3094#endif
3095
3096 /* initialize codec registers */
3097 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3098 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3099 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3100 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3101 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3102 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3103 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3104
3105 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3106 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3107#if CM_CH_PLAY == 1
3108 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3109#else
3110 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3111#endif
3112 if (cm->chip_version) {
3113 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3114 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3115 }
3116 /* Set Bus Master Request */
3117 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3118
3119 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3120 switch (pci->device) {
3121 case PCI_DEVICE_ID_CMEDIA_CM8738:
3122 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3123 if (!pci_dev_present(intel_82437vx))
3124 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3125 break;
3126 default:
3127 break;
3128 }
3129
3130 if (cm->chip_version < 68) {
3131 val = pci->device < 0x110 ? 8338 : 8738;
3132 } else {
3133 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3134 case 0:
3135 val = 8769;
3136 break;
3137 case 2:
3138 val = 8762;
3139 break;
3140 default:
3141 switch ((pci->subsystem_vendor << 16) |
3142 pci->subsystem_device) {
3143 case 0x13f69761:
3144 case 0x584d3741:
3145 case 0x584d3751:
3146 case 0x584d3761:
3147 case 0x584d3771:
3148 case 0x72848384:
3149 val = 8770;
3150 break;
3151 default:
3152 val = 8768;
3153 break;
3154 }
3155 }
3156 }
3157 sprintf(card->shortname, "C-Media CMI%d", val);
3158 if (cm->chip_version < 68)
3159 sprintf(modelstr, " (model %d)", cm->chip_version);
3160 else
3161 modelstr[0] = '\0';
3162 sprintf(card->longname, "%s%s at %#lx, irq %i",
3163 card->shortname, modelstr, cm->iobase, cm->irq);
3164
3165 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops);
3166 if (err < 0) {
3167 snd_cmipci_free(cm);
3168 return err;
3169 }
3170
3171 if (cm->chip_version >= 39) {
3172 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3173 if (val != 0x00 && val != 0xff) {
3174 if (mpu_port[dev])
3175 iomidi = cm->iobase + CM_REG_MPU_PCI;
3176 integrated_midi = 1;
3177 }
3178 }
3179 if (!integrated_midi) {
3180 val = 0;
3181 iomidi = mpu_port[dev];
3182 switch (iomidi) {
3183 case 0x320: val = CM_VMPU_320; break;
3184 case 0x310: val = CM_VMPU_310; break;
3185 case 0x300: val = CM_VMPU_300; break;
3186 case 0x330: val = CM_VMPU_330; break;
3187 default:
3188 iomidi = 0; break;
3189 }
3190 if (iomidi > 0) {
3191 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3192 /* enable UART */
3193 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3194 if (inb(iomidi + 1) == 0xff) {
3195 dev_err(cm->card->dev,
3196 "cannot enable MPU-401 port at %#lx\n",
3197 iomidi);
3198 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3199 CM_UART_EN);
3200 iomidi = 0;
3201 }
3202 }
3203 }
3204
3205 if (cm->chip_version < 68) {
3206 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3207 if (err < 0)
3208 return err;
3209 }
3210
3211 /* reset mixer */
3212 snd_cmipci_mixer_write(cm, 0, 0);
3213
3214 snd_cmipci_proc_init(cm);
3215
3216 /* create pcm devices */
3217 pcm_index = pcm_spdif_index = 0;
3218 err = snd_cmipci_pcm_new(cm, pcm_index);
3219 if (err < 0)
3220 return err;
3221 pcm_index++;
3222 err = snd_cmipci_pcm2_new(cm, pcm_index);
3223 if (err < 0)
3224 return err;
3225 pcm_index++;
3226 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3227 pcm_spdif_index = pcm_index;
3228 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3229 if (err < 0)
3230 return err;
3231 }
3232
3233 /* create mixer interface & switches */
3234 err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3235 if (err < 0)
3236 return err;
3237
3238 if (iomidi > 0) {
3239 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3240 iomidi,
3241 (integrated_midi ?
3242 MPU401_INFO_INTEGRATED : 0) |
3243 MPU401_INFO_IRQ_HOOK,
3244 -1, &cm->rmidi);
3245 if (err < 0)
3246 dev_err(cm->card->dev,
3247 "no UART401 device at 0x%lx\n", iomidi);
3248 }
3249
3250#ifdef USE_VAR48KRATE
3251 for (val = 0; val < ARRAY_SIZE(rates); val++)
3252 snd_cmipci_set_pll(cm, rates[val], val);
3253
3254 /*
3255 * (Re-)Enable external switch spdo_48k
3256 */
3257 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3258#endif /* USE_VAR48KRATE */
3259
3260 if (snd_cmipci_create_gameport(cm, dev) < 0)
3261 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3262
3263 *rcmipci = cm;
3264 return 0;
3265}
3266
3267/*
3268 */
3269
3270MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3271
3272static int snd_cmipci_probe(struct pci_dev *pci,
3273 const struct pci_device_id *pci_id)
3274{
3275 static int dev;
3276 struct snd_card *card;
3277 struct cmipci *cm;
3278 int err;
3279
3280 if (dev >= SNDRV_CARDS)
3281 return -ENODEV;
3282 if (! enable[dev]) {
3283 dev++;
3284 return -ENOENT;
3285 }
3286
3287 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3288 0, &card);
3289 if (err < 0)
3290 return err;
3291
3292 switch (pci->device) {
3293 case PCI_DEVICE_ID_CMEDIA_CM8738:
3294 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3295 strcpy(card->driver, "CMI8738");
3296 break;
3297 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3298 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3299 strcpy(card->driver, "CMI8338");
3300 break;
3301 default:
3302 strcpy(card->driver, "CMIPCI");
3303 break;
3304 }
3305
3306 err = snd_cmipci_create(card, pci, dev, &cm);
3307 if (err < 0)
3308 goto free_card;
3309
3310 card->private_data = cm;
3311
3312 err = snd_card_register(card);
3313 if (err < 0)
3314 goto free_card;
3315
3316 pci_set_drvdata(pci, card);
3317 dev++;
3318 return 0;
3319
3320free_card:
3321 snd_card_free(card);
3322 return err;
3323}
3324
3325static void snd_cmipci_remove(struct pci_dev *pci)
3326{
3327 snd_card_free(pci_get_drvdata(pci));
3328}
3329
3330
3331#ifdef CONFIG_PM_SLEEP
3332/*
3333 * power management
3334 */
3335static const unsigned char saved_regs[] = {
3336 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3337 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3338 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3339 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3340 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3341};
3342
3343static const unsigned char saved_mixers[] = {
3344 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3345 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3346 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3347 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3348 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3349 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3350 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3351 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3352};
3353
3354static int snd_cmipci_suspend(struct device *dev)
3355{
3356 struct snd_card *card = dev_get_drvdata(dev);
3357 struct cmipci *cm = card->private_data;
3358 int i;
3359
3360 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3361
3362 /* save registers */
3363 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3364 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3365 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3366 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3367
3368 /* disable ints */
3369 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3370 return 0;
3371}
3372
3373static int snd_cmipci_resume(struct device *dev)
3374{
3375 struct snd_card *card = dev_get_drvdata(dev);
3376 struct cmipci *cm = card->private_data;
3377 int i;
3378
3379 /* reset / initialize to a sane state */
3380 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3381 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3382 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3383 snd_cmipci_mixer_write(cm, 0, 0);
3384
3385 /* restore registers */
3386 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3387 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3388 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3389 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3390
3391 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3392 return 0;
3393}
3394
3395static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3396#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3397#else
3398#define SND_CMIPCI_PM_OPS NULL
3399#endif /* CONFIG_PM_SLEEP */
3400
3401static struct pci_driver cmipci_driver = {
3402 .name = KBUILD_MODNAME,
3403 .id_table = snd_cmipci_ids,
3404 .probe = snd_cmipci_probe,
3405 .remove = snd_cmipci_remove,
3406 .driver = {
3407 .pm = SND_CMIPCI_PM_OPS,
3408 },
3409};
3410
3411module_pci_driver(cmipci_driver);
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