source: GPL/trunk/alsa-kernel/pci/cmipci.c@ 695

Last change on this file since 695 was 695, checked in by David Azarewicz, 4 years ago

Merge changes from next branch.
File size: 103.6 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 */
6
7/* Does not work. Warning may block system in capture mode */
8/* #define USE_VAR48KRATE */
9
10#include <linux/io.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/gameport.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <sound/core.h>
20#include <sound/info.h>
21#include <sound/control.h>
22#include <sound/pcm.h>
23#include <sound/rawmidi.h>
24#include <sound/mpu401.h>
25#include <sound/opl3.h>
26#include <sound/sb.h>
27#include <sound/asoundef.h>
28#include <sound/initval.h>
29
30#ifdef TARGET_OS2
31#define KBUILD_MODNAME "cmipci"
32#endif
33MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
34MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
35MODULE_LICENSE("GPL");
36
37#if IS_REACHABLE(CONFIG_GAMEPORT)
38#define SUPPORT_JOYSTICK 1
39#endif
40
41static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
43static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
44#ifndef TARGET_OS2
45static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
46static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
47static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
48#else
49static long mpu_port[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
50static long fm_port[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
51static bool soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
52#endif
53#ifdef SUPPORT_JOYSTICK
54static int joystick_port[SNDRV_CARDS];
55#endif
56
57module_param_array(index, int, NULL, 0444);
58MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
59module_param_array(id, charp, NULL, 0444);
60MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
61module_param_array(enable, bool, NULL, 0444);
62MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
63module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
64MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
65module_param_hw_array(fm_port, long, ioport, NULL, 0444);
66MODULE_PARM_DESC(fm_port, "FM port.");
67module_param_array(soft_ac3, bool, NULL, 0444);
68MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
69#ifdef SUPPORT_JOYSTICK
70module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
71MODULE_PARM_DESC(joystick_port, "Joystick port address.");
72#endif
73
74/*
75 * CM8x38 registers definition
76 */
77
78#define CM_REG_FUNCTRL0 0x00
79#define CM_RST_CH1 0x00080000
80#define CM_RST_CH0 0x00040000
81#define CM_CHEN1 0x00020000 /* ch1: enable */
82#define CM_CHEN0 0x00010000 /* ch0: enable */
83#define CM_PAUSE1 0x00000008 /* ch1: pause */
84#define CM_PAUSE0 0x00000004 /* ch0: pause */
85#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
86#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
87
88#define CM_REG_FUNCTRL1 0x04
89#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
90#define CM_DSFC_SHIFT 13
91#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
92#define CM_ASFC_SHIFT 10
93#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
94#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
95#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
96#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
97#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
98#define CM_BREQ 0x00000010 /* bus master enabled */
99#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
100#define CM_UART_EN 0x00000004 /* legacy UART */
101#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
102#define CM_ZVPORT 0x00000001 /* ZVPORT */
103
104#define CM_REG_CHFORMAT 0x08
105
106#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
107#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
108#define CM_CHB3D 0x20000000 /* 4 channels */
109
110#define CM_CHIP_MASK1 0x1f000000
111#define CM_CHIP_037 0x01000000
112#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
113#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
114#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
115#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
116#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
117#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
118/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
119
120#define CM_ADCBITLEN_MASK 0x0000C000
121#define CM_ADCBITLEN_16 0x00000000
122#define CM_ADCBITLEN_15 0x00004000
123#define CM_ADCBITLEN_14 0x00008000
124#define CM_ADCBITLEN_13 0x0000C000
125
126#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
127#define CM_ADCDACLEN_060 0x00000000
128#define CM_ADCDACLEN_066 0x00001000
129#define CM_ADCDACLEN_130 0x00002000
130#define CM_ADCDACLEN_280 0x00003000
131
132#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
133#define CM_ADCDLEN_ORIGINAL 0x00000000
134#define CM_ADCDLEN_EXTRA 0x00001000
135#define CM_ADCDLEN_24K 0x00002000
136#define CM_ADCDLEN_WEIGHT 0x00003000
137
138#define CM_CH1_SRATE_176K 0x00000800
139#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
140#define CM_CH1_SRATE_88K 0x00000400
141#define CM_CH0_SRATE_176K 0x00000200
142#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
143#define CM_CH0_SRATE_88K 0x00000100
144#define CM_CH0_SRATE_128K 0x00000300
145#define CM_CH0_SRATE_MASK 0x00000300
146
147#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
148#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
149#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
150#define CM_SPDLOCKED 0x00000010
151
152#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
153#define CM_CH1FMT_SHIFT 2
154#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
155#define CM_CH0FMT_SHIFT 0
156
157#define CM_REG_INT_HLDCLR 0x0C
158#define CM_CHIP_MASK2 0xff000000
159#define CM_CHIP_8768 0x20000000
160#define CM_CHIP_055 0x08000000
161#define CM_CHIP_039 0x04000000
162#define CM_CHIP_039_6CH 0x01000000
163#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
164#define CM_TDMA_INT_EN 0x00040000
165#define CM_CH1_INT_EN 0x00020000
166#define CM_CH0_INT_EN 0x00010000
167
168#define CM_REG_INT_STATUS 0x10
169#define CM_INTR 0x80000000
170#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
171#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
172#define CM_UARTINT 0x00010000
173#define CM_LTDMAINT 0x00008000
174#define CM_HTDMAINT 0x00004000
175#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
176#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
177#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
178#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
179#define CM_CH1BUSY 0x00000008
180#define CM_CH0BUSY 0x00000004
181#define CM_CHINT1 0x00000002
182#define CM_CHINT0 0x00000001
183
184#define CM_REG_LEGACY_CTRL 0x14
185#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
186#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
187#define CM_VMPU_330 0x00000000
188#define CM_VMPU_320 0x20000000
189#define CM_VMPU_310 0x40000000
190#define CM_VMPU_300 0x60000000
191#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
192#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
193#define CM_VSBSEL_220 0x00000000
194#define CM_VSBSEL_240 0x04000000
195#define CM_VSBSEL_260 0x08000000
196#define CM_VSBSEL_280 0x0C000000
197#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
198#define CM_FMSEL_388 0x00000000
199#define CM_FMSEL_3C8 0x01000000
200#define CM_FMSEL_3E0 0x02000000
201#define CM_FMSEL_3E8 0x03000000
202#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
203#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
204#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
205#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
206#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
207#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
208#define CM_C_EECS 0x00040000
209#define CM_C_EEDI46 0x00020000
210#define CM_C_EECK46 0x00010000
211#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
212#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
213#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
214#define CM_EXBASEN 0x00001000 /* external bass input enable */
215
216#define CM_REG_MISC_CTRL 0x18
217#define CM_PWD 0x80000000 /* power down */
218#define CM_RESET 0x40000000
219#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
220#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
221#define CM_TXVX 0x08000000 /* model 037? */
222#define CM_N4SPK3D 0x04000000 /* copy front to rear */
223#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
224#define CM_SPDIF48K 0x01000000 /* write */
225#define CM_SPATUS48K 0x01000000 /* read */
226#define CM_ENDBDAC 0x00800000 /* enable double dac */
227#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
228#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
229#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
230#define CM_FM_EN 0x00080000 /* enable legacy FM */
231#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
232#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
233#define CM_VIDWPDSB 0x00010000 /* model 037? */
234#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
235#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
236#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
237#define CM_VIDWPPRT 0x00002000 /* model 037? */
238#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
239#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
240#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
241#define CM_ENCENTER 0x00000080
242#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
243#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
244#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
245#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
246#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
247#define CM_UPDDMA_2048 0x00000000
248#define CM_UPDDMA_1024 0x00000004
249#define CM_UPDDMA_512 0x00000008
250#define CM_UPDDMA_256 0x0000000C
251#define CM_TWAIT_MASK 0x00000003 /* model 037 */
252#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
253#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
254
255#define CM_REG_TDMA_POSITION 0x1C
256#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
257#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
258
259 /* byte */
260#define CM_REG_MIXER0 0x20
261#define CM_REG_SBVR 0x20 /* write: sb16 version */
262#define CM_REG_DEV 0x20 /* read: hardware device version */
263
264#define CM_REG_MIXER21 0x21
265#define CM_UNKNOWN_21_MASK 0x78 /* ? */
266#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
267#define CM_PROINV 0x02 /* SBPro left/right channel switching */
268#define CM_X_SB16 0x01 /* SB16 compatible */
269
270#define CM_REG_SB16_DATA 0x22
271#define CM_REG_SB16_ADDR 0x23
272
273#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
274#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
275#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
276#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
277
278#define CM_REG_MIXER1 0x24
279#define CM_FMMUTE 0x80 /* mute FM */
280#define CM_FMMUTE_SHIFT 7
281#define CM_WSMUTE 0x40 /* mute PCM */
282#define CM_WSMUTE_SHIFT 6
283#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
284#define CM_REAR2LIN_SHIFT 5
285#define CM_REAR2FRONT 0x10 /* exchange rear/front */
286#define CM_REAR2FRONT_SHIFT 4
287#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
288#define CM_WAVEINL_SHIFT 3
289#define CM_WAVEINR 0x04 /* digical wave rec. right */
290#define CM_WAVEINR_SHIFT 2
291#define CM_X3DEN 0x02 /* 3D surround enable */
292#define CM_X3DEN_SHIFT 1
293#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
294#define CM_CDPLAY_SHIFT 0
295
296#define CM_REG_MIXER2 0x25
297#define CM_RAUXREN 0x80 /* AUX right capture */
298#define CM_RAUXREN_SHIFT 7
299#define CM_RAUXLEN 0x40 /* AUX left capture */
300#define CM_RAUXLEN_SHIFT 6
301#define CM_VAUXRM 0x20 /* AUX right mute */
302#define CM_VAUXRM_SHIFT 5
303#define CM_VAUXLM 0x10 /* AUX left mute */
304#define CM_VAUXLM_SHIFT 4
305#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
306#define CM_VADMIC_SHIFT 1
307#define CM_MICGAINZ 0x01 /* mic boost */
308#define CM_MICGAINZ_SHIFT 0
309
310#define CM_REG_MIXER3 0x24
311#define CM_REG_AUX_VOL 0x26
312#define CM_VAUXL_MASK 0xf0
313#define CM_VAUXR_MASK 0x0f
314
315#define CM_REG_MISC 0x27
316#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
317#define CM_XGPO1 0x20
318// #define CM_XGPBIO 0x04
319#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
320#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
321#define CM_SPDVALID 0x02 /* spdif input valid check */
322#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
323
324#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
325/*
326 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
327 * or identical with AC97 codec?
328 */
329#define CM_REG_EXTERN_CODEC CM_REG_AC97
330
331/*
332 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
333 */
334#define CM_REG_MPU_PCI 0x40
335
336/*
337 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
338 */
339#define CM_REG_FM_PCI 0x50
340
341/*
342 * access from SB-mixer port
343 */
344#define CM_REG_EXTENT_IND 0xf0
345#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
346#define CM_VPHONE_SHIFT 5
347#define CM_VPHOM 0x10 /* Phone mute control */
348#define CM_VSPKM 0x08 /* Speaker mute control, default high */
349#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
350#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
351#define CM_VADMIC3 0x01 /* Mic record boost */
352
353/*
354 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
355 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
356 * unit (readonly?).
357 */
358#define CM_REG_PLL 0xf8
359
360/*
361 * extended registers
362 */
363#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
364#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
365#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
366#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
367
368#define CM_REG_EXT_MISC 0x90
369#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
370#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
371#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
372#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
373#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
374#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
375#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
376#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
377
378/*
379 * size of i/o region
380 */
381#define CM_EXTENT_CODEC 0x100
382#define CM_EXTENT_MIDI 0x2
383#define CM_EXTENT_SYNTH 0x4
384
385
386/*
387 * channels for playback / capture
388 */
389#define CM_CH_PLAY 0
390#define CM_CH_CAPT 1
391
392/*
393 * flags to check device open/close
394 */
395#define CM_OPEN_NONE 0
396#define CM_OPEN_CH_MASK 0x01
397#define CM_OPEN_DAC 0x10
398#define CM_OPEN_ADC 0x20
399#define CM_OPEN_SPDIF 0x40
400#define CM_OPEN_MCHAN 0x80
401#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
402#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
403#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
404#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
405#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
406#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
407
408
409#if CM_CH_PLAY == 1
410#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
411#define CM_PLAYBACK_SPDF CM_SPDF_1
412#define CM_CAPTURE_SPDF CM_SPDF_0
413#else
414#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
415#define CM_PLAYBACK_SPDF CM_SPDF_0
416#define CM_CAPTURE_SPDF CM_SPDF_1
417#endif
418
419
420/*
421 * driver data
422 */
423
424struct cmipci_pcm {
425 struct snd_pcm_substream *substream;
426 u8 running; /* dac/adc running? */
427 u8 fmt; /* format bits */
428 u8 is_dac;
429 u8 needs_silencing;
430 unsigned int dma_size; /* in frames */
431 unsigned int shift;
432 unsigned int ch; /* channel (0/1) */
433 unsigned int offset; /* physical address of the buffer */
434};
435
436/* mixer elements toggled/resumed during ac3 playback */
437struct cmipci_mixer_auto_switches {
438 const char *name; /* switch to toggle */
439 int toggle_on; /* value to change when ac3 mode */
440};
441static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
442 {"PCM Playback Switch", 0},
443 {"IEC958 Output Switch", 1},
444 {"IEC958 Mix Analog", 0},
445 // {"IEC958 Out To DAC", 1}, // no longer used
446 {"IEC958 Loop", 0},
447};
448#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
449
450struct cmipci {
451 struct snd_card *card;
452
453 struct pci_dev *pci;
454 unsigned int device; /* device ID */
455 int irq;
456
457 unsigned long iobase;
458 unsigned int ctrl; /* FUNCTRL0 current value */
459
460 struct snd_pcm *pcm; /* DAC/ADC PCM */
461 struct snd_pcm *pcm2; /* 2nd DAC */
462 struct snd_pcm *pcm_spdif; /* SPDIF */
463
464 int chip_version;
465 int max_channels;
466 unsigned int can_ac3_sw: 1;
467 unsigned int can_ac3_hw: 1;
468 unsigned int can_multi_ch: 1;
469 unsigned int can_96k: 1; /* samplerate above 48k */
470 unsigned int do_soft_ac3: 1;
471
472 unsigned int spdif_playback_avail: 1; /* spdif ready? */
473 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
474 int spdif_counter; /* for software AC3 */
475
476 unsigned int dig_status;
477 unsigned int dig_pcm_status;
478
479 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
480
481 int opened[2]; /* open mode */
482 struct mutex open_mutex;
483
484 unsigned int mixer_insensitive: 1;
485 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
486 int mixer_res_status[CM_SAVED_MIXERS];
487
488 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
489
490 /* external MIDI */
491 struct snd_rawmidi *rmidi;
492
493#ifdef SUPPORT_JOYSTICK
494 struct gameport *gameport;
495#endif
496
497 spinlock_t reg_lock;
498
499#ifdef CONFIG_PM_SLEEP
500 unsigned int saved_regs[0x20];
501 unsigned char saved_mixers[0x20];
502#endif
503};
504
505
506/* read/write operations for dword register */
507static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
508{
509 outl(data, cm->iobase + cmd);
510}
511
512static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
513{
514 return inl(cm->iobase + cmd);
515}
516
517/* read/write operations for word register */
518static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
519{
520 outw(data, cm->iobase + cmd);
521}
522
523static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
524{
525 return inw(cm->iobase + cmd);
526}
527
528/* read/write operations for byte register */
529static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
530{
531 outb(data, cm->iobase + cmd);
532}
533
534static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
535{
536 return inb(cm->iobase + cmd);
537}
538
539/* bit operations for dword register */
540static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
541{
542 unsigned int val, oval;
543 val = oval = inl(cm->iobase + cmd);
544 val |= flag;
545 if (val == oval)
546 return 0;
547 outl(val, cm->iobase + cmd);
548 return 1;
549}
550
551static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
552{
553 unsigned int val, oval;
554 val = oval = inl(cm->iobase + cmd);
555 val &= ~flag;
556 if (val == oval)
557 return 0;
558 outl(val, cm->iobase + cmd);
559 return 1;
560}
561
562/* bit operations for byte register */
563static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
564{
565 unsigned char val, oval;
566 val = oval = inb(cm->iobase + cmd);
567 val |= flag;
568 if (val == oval)
569 return 0;
570 outb(val, cm->iobase + cmd);
571 return 1;
572}
573
574static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
575{
576 unsigned char val, oval;
577 val = oval = inb(cm->iobase + cmd);
578 val &= ~flag;
579 if (val == oval)
580 return 0;
581 outb(val, cm->iobase + cmd);
582 return 1;
583}
584
585
586/*
587 * PCM interface
588 */
589
590/*
591 * calculate frequency
592 */
593
594static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
595
596static unsigned int snd_cmipci_rate_freq(unsigned int rate)
597{
598 unsigned int i;
599
600 for (i = 0; i < ARRAY_SIZE(rates); i++) {
601 if (rates[i] == rate)
602 return i;
603 }
604 snd_BUG();
605 return 0;
606}
607
608#ifdef USE_VAR48KRATE
609/*
610 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
611 * does it this way .. maybe not. Never get any information from C-Media about
612 * that <werner@suse.de>.
613 */
614static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
615{
616 unsigned int delta, tolerance;
617 int xm, xn, xr;
618
619 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
620 rate <<= 1;
621 *n = -1;
622 if (*r > 0xff)
623 goto out;
624 tolerance = rate*CM_TOLERANCE_RATE;
625
626 for (xn = (1+2); xn < (0x1f+2); xn++) {
627 for (xm = (1+2); xm < (0xff+2); xm++) {
628 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
629
630 if (xr < rate)
631 delta = rate - xr;
632 else
633 delta = xr - rate;
634
635 /*
636 * If we found one, remember this,
637 * and try to find a closer one
638 */
639 if (delta < tolerance) {
640 tolerance = delta;
641 *m = xm - 2;
642 *n = xn - 2;
643 }
644 }
645 }
646out:
647 return (*n > -1);
648}
649
650/*
651 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
652 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
653 * at the register CM_REG_FUNCTRL1 (0x04).
654 * Problem: other ways are also possible (any information about that?)
655 */
656static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
657{
658 unsigned int reg = CM_REG_PLL + slot;
659 /*
660 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
661 * for DSFC/ASFC (000 up to 111).
662 */
663
664 /* FIXME: Init (Do we've to set an other register first before programming?) */
665
666 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
667 snd_cmipci_write_b(cm, reg, rate>>8);
668 snd_cmipci_write_b(cm, reg, rate&0xff);
669
670 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
671}
672#endif /* USE_VAR48KRATE */
673
674static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
675 struct snd_pcm_hw_params *hw_params)
676{
677 struct cmipci *cm = snd_pcm_substream_chip(substream);
678 if (params_channels(hw_params) > 2) {
679 mutex_lock(&cm->open_mutex);
680 if (cm->opened[CM_CH_PLAY]) {
681 mutex_unlock(&cm->open_mutex);
682 return -EBUSY;
683 }
684 /* reserve the channel A */
685 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
686 mutex_unlock(&cm->open_mutex);
687 }
688 return 0;
689}
690
691static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
692{
693 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
694 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
695 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
696 udelay(10);
697}
698
699
700/*
701 */
702
703static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
704static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
705 .count = 3,
706 .list = hw_channels,
707 .mask = 0,
708};
709static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
710 .count = 4,
711 .list = hw_channels,
712 .mask = 0,
713};
714static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
715 .count = 5,
716 .list = hw_channels,
717 .mask = 0,
718};
719
720static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
721{
722 if (channels > 2) {
723 if (!cm->can_multi_ch || !rec->ch)
724 return -EINVAL;
725 if (rec->fmt != 0x03) /* stereo 16bit only */
726 return -EINVAL;
727 }
728
729 if (cm->can_multi_ch) {
730 spin_lock_irq(&cm->reg_lock);
731 if (channels > 2) {
732 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
733 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
734 } else {
735 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
736 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
737 }
738 if (channels == 8)
739 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
740 else
741 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
742 if (channels == 6) {
743 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
744 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
745 } else {
746 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
747 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
748 }
749 if (channels == 4)
750 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
751 else
752 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
753 spin_unlock_irq(&cm->reg_lock);
754 }
755 return 0;
756}
757
758
759/*
760 * prepare playback/capture channel
761 * channel to be used must have been set in rec->ch.
762 */
763static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
764 struct snd_pcm_substream *substream)
765{
766 unsigned int reg, freq, freq_ext, val;
767 unsigned int period_size;
768 struct snd_pcm_runtime *runtime = substream->runtime;
769
770 rec->fmt = 0;
771 rec->shift = 0;
772 if (snd_pcm_format_width(runtime->format) >= 16) {
773 rec->fmt |= 0x02;
774 if (snd_pcm_format_width(runtime->format) > 16)
775 rec->shift++; /* 24/32bit */
776 }
777 if (runtime->channels > 1)
778 rec->fmt |= 0x01;
779 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
780 dev_dbg(cm->card->dev, "cannot set dac channels\n");
781 return -EINVAL;
782 }
783
784 rec->offset = runtime->dma_addr;
785 /* buffer and period sizes in frame */
786 rec->dma_size = runtime->buffer_size << rec->shift;
787 period_size = runtime->period_size << rec->shift;
788 if (runtime->channels > 2) {
789 /* multi-channels */
790 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
791 period_size = (period_size * runtime->channels) / 2;
792 }
793
794 spin_lock_irq(&cm->reg_lock);
795
796 /* set buffer address */
797 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
798 snd_cmipci_write(cm, reg, rec->offset);
799 /* program sample counts */
800 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
801 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
802 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
803
804 /* set adc/dac flag */
805 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
806 if (rec->is_dac)
807 cm->ctrl &= ~val;
808 else
809 cm->ctrl |= val;
810 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
811 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
812
813 /* set sample rate */
814 freq = 0;
815 freq_ext = 0;
816 if (runtime->rate > 48000)
817 switch (runtime->rate) {
818 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
819 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
820 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
821 default: snd_BUG(); break;
822 }
823 else
824 freq = snd_cmipci_rate_freq(runtime->rate);
825 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
826 if (rec->ch) {
827 val &= ~CM_DSFC_MASK;
828 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
829 } else {
830 val &= ~CM_ASFC_MASK;
831 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
832 }
833 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
834 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
835
836 /* set format */
837 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
838 if (rec->ch) {
839 val &= ~CM_CH1FMT_MASK;
840 val |= rec->fmt << CM_CH1FMT_SHIFT;
841 } else {
842 val &= ~CM_CH0FMT_MASK;
843 val |= rec->fmt << CM_CH0FMT_SHIFT;
844 }
845 if (cm->can_96k) {
846 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
847 val |= freq_ext << (rec->ch * 2);
848 }
849 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
850 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
851
852 if (!rec->is_dac && cm->chip_version) {
853 if (runtime->rate > 44100)
854 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
855 else
856 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
857 }
858
859 rec->running = 0;
860 spin_unlock_irq(&cm->reg_lock);
861
862 return 0;
863}
864
865/*
866 * PCM trigger/stop
867 */
868static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
869 int cmd)
870{
871 unsigned int inthld, chen, reset, pause;
872 int result = 0;
873
874 inthld = CM_CH0_INT_EN << rec->ch;
875 chen = CM_CHEN0 << rec->ch;
876 reset = CM_RST_CH0 << rec->ch;
877 pause = CM_PAUSE0 << rec->ch;
878
879 spin_lock(&cm->reg_lock);
880 switch (cmd) {
881 case SNDRV_PCM_TRIGGER_START:
882 rec->running = 1;
883 /* set interrupt */
884 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
885 cm->ctrl |= chen;
886 /* enable channel */
887 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
888 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
889 break;
890 case SNDRV_PCM_TRIGGER_STOP:
891 rec->running = 0;
892 /* disable interrupt */
893 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
894 /* reset */
895 cm->ctrl &= ~chen;
896 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
897 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
898 rec->needs_silencing = rec->is_dac;
899 break;
900 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
901 case SNDRV_PCM_TRIGGER_SUSPEND:
902 cm->ctrl |= pause;
903 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
904 break;
905 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
906 case SNDRV_PCM_TRIGGER_RESUME:
907 cm->ctrl &= ~pause;
908 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
909 break;
910 default:
911 result = -EINVAL;
912 break;
913 }
914 spin_unlock(&cm->reg_lock);
915 return result;
916}
917
918/*
919 * return the current pointer
920 */
921static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
922 struct snd_pcm_substream *substream)
923{
924 size_t ptr;
925 unsigned int reg, rem, tries;
926
927 if (!rec->running)
928 return 0;
929#if 1 // this seems better..
930 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
931 for (tries = 0; tries < 3; tries++) {
932 rem = snd_cmipci_read_w(cm, reg);
933 if (rem < rec->dma_size)
934 goto ok;
935 }
936 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
937 return SNDRV_PCM_POS_XRUN;
938ok:
939 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
940#else
941 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
942 ptr = snd_cmipci_read(cm, reg) - rec->offset;
943 ptr = bytes_to_frames(substream->runtime, ptr);
944#endif
945 if (substream->runtime->channels > 2)
946 ptr = (ptr * 2) / substream->runtime->channels;
947 return ptr;
948}
949
950/*
951 * playback
952 */
953
954static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
955 int cmd)
956{
957 struct cmipci *cm = snd_pcm_substream_chip(substream);
958 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
959}
960
961static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
962{
963 struct cmipci *cm = snd_pcm_substream_chip(substream);
964 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
965}
966
967
968
969/*
970 * capture
971 */
972
973static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
974 int cmd)
975{
976 struct cmipci *cm = snd_pcm_substream_chip(substream);
977 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
978}
979
980static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
981{
982 struct cmipci *cm = snd_pcm_substream_chip(substream);
983 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
984}
985
986
987/*
988 * hw preparation for spdif
989 */
990
991static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
992 struct snd_ctl_elem_info *uinfo)
993{
994 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
995 uinfo->count = 1;
996 return 0;
997}
998
999static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1003 int i;
1004
1005 spin_lock_irq(&chip->reg_lock);
1006 for (i = 0; i < 4; i++)
1007 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1008 spin_unlock_irq(&chip->reg_lock);
1009 return 0;
1010}
1011
1012static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1013 struct snd_ctl_elem_value *ucontrol)
1014{
1015 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1016 int i, change;
1017 unsigned int val;
1018
1019 val = 0;
1020 spin_lock_irq(&chip->reg_lock);
1021 for (i = 0; i < 4; i++)
1022 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1023 change = val != chip->dig_status;
1024 chip->dig_status = val;
1025 spin_unlock_irq(&chip->reg_lock);
1026 return change;
1027}
1028
1029static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1030{
1031 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1032 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1033 .info = snd_cmipci_spdif_default_info,
1034 .get = snd_cmipci_spdif_default_get,
1035 .put = snd_cmipci_spdif_default_put
1036};
1037
1038static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_info *uinfo)
1040{
1041 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1042 uinfo->count = 1;
1043 return 0;
1044}
1045
1046static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1048{
1049 ucontrol->value.iec958.status[0] = 0xff;
1050 ucontrol->value.iec958.status[1] = 0xff;
1051 ucontrol->value.iec958.status[2] = 0xff;
1052 ucontrol->value.iec958.status[3] = 0xff;
1053 return 0;
1054}
1055
1056static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1057{
1058 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1059 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1060 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1061 .info = snd_cmipci_spdif_mask_info,
1062 .get = snd_cmipci_spdif_mask_get,
1063};
1064
1065static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1066 struct snd_ctl_elem_info *uinfo)
1067{
1068 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1069 uinfo->count = 1;
1070 return 0;
1071}
1072
1073static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1074 struct snd_ctl_elem_value *ucontrol)
1075{
1076 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1077 int i;
1078
1079 spin_lock_irq(&chip->reg_lock);
1080 for (i = 0; i < 4; i++)
1081 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1082 spin_unlock_irq(&chip->reg_lock);
1083 return 0;
1084}
1085
1086static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1087 struct snd_ctl_elem_value *ucontrol)
1088{
1089 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1090 int i, change;
1091 unsigned int val;
1092
1093 val = 0;
1094 spin_lock_irq(&chip->reg_lock);
1095 for (i = 0; i < 4; i++)
1096 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1097 change = val != chip->dig_pcm_status;
1098 chip->dig_pcm_status = val;
1099 spin_unlock_irq(&chip->reg_lock);
1100 return change;
1101}
1102
1103static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1104{
1105 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1106 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1107 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1108 .info = snd_cmipci_spdif_stream_info,
1109 .get = snd_cmipci_spdif_stream_get,
1110 .put = snd_cmipci_spdif_stream_put
1111};
1112
1113/*
1114 */
1115
1116/* save mixer setting and mute for AC3 playback */
1117static int save_mixer_state(struct cmipci *cm)
1118{
1119 if (! cm->mixer_insensitive) {
1120 struct snd_ctl_elem_value *val;
1121 unsigned int i;
1122
1123 val = kmalloc(sizeof(*val), GFP_KERNEL);
1124 if (!val)
1125 return -ENOMEM;
1126 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1127 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1128 if (ctl) {
1129 int event;
1130 memset(val, 0, sizeof(*val));
1131 ctl->get(ctl, val);
1132 cm->mixer_res_status[i] = val->value.integer.value[0];
1133 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1134 event = SNDRV_CTL_EVENT_MASK_INFO;
1135 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1136 ctl->put(ctl, val); /* toggle */
1137 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1138 }
1139 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1140 snd_ctl_notify(cm->card, event, &ctl->id);
1141 }
1142 }
1143 kfree(val);
1144 cm->mixer_insensitive = 1;
1145 }
1146 return 0;
1147}
1148
1149
1150/* restore the previously saved mixer status */
1151static void restore_mixer_state(struct cmipci *cm)
1152{
1153 if (cm->mixer_insensitive) {
1154 struct snd_ctl_elem_value *val;
1155 unsigned int i;
1156
1157 val = kmalloc(sizeof(*val), GFP_KERNEL);
1158 if (!val)
1159 return;
1160 cm->mixer_insensitive = 0; /* at first clear this;
1161 otherwise the changes will be ignored */
1162 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1163 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1164 if (ctl) {
1165 int event;
1166
1167 memset(val, 0, sizeof(*val));
1168 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1169 ctl->get(ctl, val);
1170 event = SNDRV_CTL_EVENT_MASK_INFO;
1171 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1172 val->value.integer.value[0] = cm->mixer_res_status[i];
1173 ctl->put(ctl, val);
1174 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1175 }
1176 snd_ctl_notify(cm->card, event, &ctl->id);
1177 }
1178 }
1179 kfree(val);
1180 }
1181}
1182
1183/* spinlock held! */
1184static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1185{
1186 if (do_ac3) {
1187 /* AC3EN for 037 */
1188 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1189 /* AC3EN for 039 */
1190 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1191
1192 if (cm->can_ac3_hw) {
1193 /* SPD24SEL for 037, 0x02 */
1194 /* SPD24SEL for 039, 0x20, but cannot be set */
1195 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1196 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1197 } else { /* can_ac3_sw */
1198 /* SPD32SEL for 037 & 039, 0x20 */
1199 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1200 /* set 176K sample rate to fix 033 HW bug */
1201 if (cm->chip_version == 33) {
1202 if (rate >= 48000) {
1203 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1204 } else {
1205 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1206 }
1207 }
1208 }
1209
1210 } else {
1211 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1212 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1213
1214 if (cm->can_ac3_hw) {
1215 /* chip model >= 37 */
1216 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1217 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1218 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1219 } else {
1220 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1222 }
1223 } else {
1224 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1225 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1226 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1227 }
1228 }
1229}
1230
1231static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1232{
1233 int rate, err;
1234
1235 rate = subs->runtime->rate;
1236
1237 if (up && do_ac3)
1238 if ((err = save_mixer_state(cm)) < 0)
1239 return err;
1240
1241 spin_lock_irq(&cm->reg_lock);
1242 cm->spdif_playback_avail = up;
1243 if (up) {
1244 /* they are controlled via "IEC958 Output Switch" */
1245 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1246 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1247 if (cm->spdif_playback_enabled)
1248 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1249 setup_ac3(cm, subs, do_ac3, rate);
1250
1251 if (rate == 48000 || rate == 96000)
1252 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1253 else
1254 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1255 if (rate > 48000)
1256 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1257 else
1258 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1259 } else {
1260 /* they are controlled via "IEC958 Output Switch" */
1261 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1262 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1263 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1264 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1265 setup_ac3(cm, subs, 0, 0);
1266 }
1267 spin_unlock_irq(&cm->reg_lock);
1268 return 0;
1269}
1270
1271
1272/*
1273 * preparation
1274 */
1275
1276/* playback - enable spdif only on the certain condition */
1277static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1278{
1279 struct cmipci *cm = snd_pcm_substream_chip(substream);
1280 int rate = substream->runtime->rate;
1281 int err, do_spdif, do_ac3 = 0;
1282
1283 do_spdif = (rate >= 44100 && rate <= 96000 &&
1284 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1285 substream->runtime->channels == 2);
1286 if (do_spdif && cm->can_ac3_hw)
1287 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1288 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1289 return err;
1290 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1291}
1292
1293/* playback (via device #2) - enable spdif always */
1294static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1295{
1296 struct cmipci *cm = snd_pcm_substream_chip(substream);
1297 int err, do_ac3;
1298
1299 if (cm->can_ac3_hw)
1300 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1301 else
1302 do_ac3 = 1; /* doesn't matter */
1303 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1304 return err;
1305 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1306}
1307
1308/*
1309 * Apparently, the samples last played on channel A stay in some buffer, even
1310 * after the channel is reset, and get added to the data for the rear DACs when
1311 * playing a multichannel stream on channel B. This is likely to generate
1312 * wraparounds and thus distortions.
1313 * To avoid this, we play at least one zero sample after the actual stream has
1314 * stopped.
1315 */
1316static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1317{
1318 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1319 unsigned int reg, val;
1320
1321 if (rec->needs_silencing && runtime && runtime->dma_area) {
1322 /* set up a small silence buffer */
1323 memset(runtime->dma_area, 0, PAGE_SIZE);
1324 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1325 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1326 snd_cmipci_write(cm, reg, val);
1327
1328 /* configure for 16 bits, 2 channels, 8 kHz */
1329 if (runtime->channels > 2)
1330 set_dac_channels(cm, rec, 2);
1331 spin_lock_irq(&cm->reg_lock);
1332 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1333 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1334 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1335 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1336 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1337 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1338 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1339 if (cm->can_96k)
1340 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1341 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1342
1343 /* start stream (we don't need interrupts) */
1344 cm->ctrl |= CM_CHEN0 << rec->ch;
1345 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1346 spin_unlock_irq(&cm->reg_lock);
1347
1348 msleep(1);
1349
1350 /* stop and reset stream */
1351 spin_lock_irq(&cm->reg_lock);
1352 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1353 val = CM_RST_CH0 << rec->ch;
1354 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1355 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1356 spin_unlock_irq(&cm->reg_lock);
1357
1358 rec->needs_silencing = 0;
1359 }
1360}
1361
1362static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1363{
1364 struct cmipci *cm = snd_pcm_substream_chip(substream);
1365 setup_spdif_playback(cm, substream, 0, 0);
1366 restore_mixer_state(cm);
1367 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1368 return 0;
1369}
1370
1371static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1372{
1373 struct cmipci *cm = snd_pcm_substream_chip(substream);
1374 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1375 return 0;
1376}
1377
1378/* capture */
1379static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1380{
1381 struct cmipci *cm = snd_pcm_substream_chip(substream);
1382 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1383}
1384
1385/* capture with spdif (via device #2) */
1386static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1387{
1388 struct cmipci *cm = snd_pcm_substream_chip(substream);
1389
1390 spin_lock_irq(&cm->reg_lock);
1391 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1392 if (cm->can_96k) {
1393 if (substream->runtime->rate > 48000)
1394 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1395 else
1396 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1397 }
1398 if (snd_pcm_format_width(substream->runtime->format) > 16)
1399 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1400 else
1401 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1402
1403 spin_unlock_irq(&cm->reg_lock);
1404
1405 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1406}
1407
1408static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1409{
1410 struct cmipci *cm = snd_pcm_substream_chip(subs);
1411
1412 spin_lock_irq(&cm->reg_lock);
1413 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1414 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1415 spin_unlock_irq(&cm->reg_lock);
1416
1417 return 0;
1418}
1419
1420
1421/*
1422 * interrupt handler
1423 */
1424static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1425{
1426 struct cmipci *cm = dev_id;
1427 unsigned int status, mask = 0;
1428
1429 /* fastpath out, to ease interrupt sharing */
1430 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1431 if (!(status & CM_INTR))
1432 return IRQ_NONE;
1433
1434 /* acknowledge interrupt */
1435 spin_lock(&cm->reg_lock);
1436 if (status & CM_CHINT0)
1437 mask |= CM_CH0_INT_EN;
1438 if (status & CM_CHINT1)
1439 mask |= CM_CH1_INT_EN;
1440 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1441 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1442 spin_unlock(&cm->reg_lock);
1443
1444 if (cm->rmidi && (status & CM_UARTINT))
1445 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1446
1447 if (cm->pcm) {
1448 if ((status & CM_CHINT0) && cm->channel[0].running)
1449 snd_pcm_period_elapsed(cm->channel[0].substream);
1450 if ((status & CM_CHINT1) && cm->channel[1].running)
1451 snd_pcm_period_elapsed(cm->channel[1].substream);
1452 }
1453 return IRQ_HANDLED;
1454}
1455
1456/*
1457 * h/w infos
1458 */
1459
1460/* playback on channel A */
1461static const struct snd_pcm_hardware snd_cmipci_playback =
1462{
1463 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1464 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1465 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1466 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1467 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1468 .rate_min = 5512,
1469 .rate_max = 48000,
1470 .channels_min = 1,
1471 .channels_max = 2,
1472 .buffer_bytes_max = (128*1024),
1473 .period_bytes_min = 64,
1474 .period_bytes_max = (128*1024),
1475 .periods_min = 2,
1476 .periods_max = 1024,
1477 .fifo_size = 0,
1478};
1479
1480/* capture on channel B */
1481static const struct snd_pcm_hardware snd_cmipci_capture =
1482{
1483 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1484 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1485 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1486 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1487 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1488 .rate_min = 5512,
1489 .rate_max = 48000,
1490 .channels_min = 1,
1491 .channels_max = 2,
1492 .buffer_bytes_max = (128*1024),
1493 .period_bytes_min = 64,
1494 .period_bytes_max = (128*1024),
1495 .periods_min = 2,
1496 .periods_max = 1024,
1497 .fifo_size = 0,
1498};
1499
1500/* playback on channel B - stereo 16bit only? */
1501static const struct snd_pcm_hardware snd_cmipci_playback2 =
1502{
1503 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1504 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1505 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1506 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1507 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1508 .rate_min = 5512,
1509 .rate_max = 48000,
1510 .channels_min = 2,
1511 .channels_max = 2,
1512 .buffer_bytes_max = (128*1024),
1513 .period_bytes_min = 64,
1514 .period_bytes_max = (128*1024),
1515 .periods_min = 2,
1516 .periods_max = 1024,
1517 .fifo_size = 0,
1518};
1519
1520/* spdif playback on channel A */
1521static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1522{
1523 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1524 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1525 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1526 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1527 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1528 .rate_min = 44100,
1529 .rate_max = 48000,
1530 .channels_min = 2,
1531 .channels_max = 2,
1532 .buffer_bytes_max = (128*1024),
1533 .period_bytes_min = 64,
1534 .period_bytes_max = (128*1024),
1535 .periods_min = 2,
1536 .periods_max = 1024,
1537 .fifo_size = 0,
1538};
1539
1540/* spdif playback on channel A (32bit, IEC958 subframes) */
1541static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1542{
1543 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1544 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1545 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1546 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1547 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1548 .rate_min = 44100,
1549 .rate_max = 48000,
1550 .channels_min = 2,
1551 .channels_max = 2,
1552 .buffer_bytes_max = (128*1024),
1553 .period_bytes_min = 64,
1554 .period_bytes_max = (128*1024),
1555 .periods_min = 2,
1556 .periods_max = 1024,
1557 .fifo_size = 0,
1558};
1559
1560/* spdif capture on channel B */
1561static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1562{
1563 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1564 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1565 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1566 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1567 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1568 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1569 .rate_min = 44100,
1570 .rate_max = 48000,
1571 .channels_min = 2,
1572 .channels_max = 2,
1573 .buffer_bytes_max = (128*1024),
1574 .period_bytes_min = 64,
1575 .period_bytes_max = (128*1024),
1576 .periods_min = 2,
1577 .periods_max = 1024,
1578 .fifo_size = 0,
1579};
1580
1581static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1582 32000, 44100, 48000, 88200, 96000, 128000 };
1583static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1584 .count = ARRAY_SIZE(rate_constraints),
1585 .list = rate_constraints,
1586 .mask = 0,
1587};
1588
1589/*
1590 * check device open/close
1591 */
1592static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1593{
1594 int ch = mode & CM_OPEN_CH_MASK;
1595
1596 /* FIXME: a file should wait until the device becomes free
1597 * when it's opened on blocking mode. however, since the current
1598 * pcm framework doesn't pass file pointer before actually opened,
1599 * we can't know whether blocking mode or not in open callback..
1600 */
1601 mutex_lock(&cm->open_mutex);
1602 if (cm->opened[ch]) {
1603 mutex_unlock(&cm->open_mutex);
1604 return -EBUSY;
1605 }
1606 cm->opened[ch] = mode;
1607 cm->channel[ch].substream = subs;
1608 if (! (mode & CM_OPEN_DAC)) {
1609 /* disable dual DAC mode */
1610 cm->channel[ch].is_dac = 0;
1611 spin_lock_irq(&cm->reg_lock);
1612 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1613 spin_unlock_irq(&cm->reg_lock);
1614 }
1615 mutex_unlock(&cm->open_mutex);
1616 return 0;
1617}
1618
1619static void close_device_check(struct cmipci *cm, int mode)
1620{
1621 int ch = mode & CM_OPEN_CH_MASK;
1622
1623 mutex_lock(&cm->open_mutex);
1624 if (cm->opened[ch] == mode) {
1625 if (cm->channel[ch].substream) {
1626 snd_cmipci_ch_reset(cm, ch);
1627 cm->channel[ch].running = 0;
1628 cm->channel[ch].substream = NULL;
1629 }
1630 cm->opened[ch] = 0;
1631 if (! cm->channel[ch].is_dac) {
1632 /* enable dual DAC mode again */
1633 cm->channel[ch].is_dac = 1;
1634 spin_lock_irq(&cm->reg_lock);
1635 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1636 spin_unlock_irq(&cm->reg_lock);
1637 }
1638 }
1639 mutex_unlock(&cm->open_mutex);
1640}
1641
1642/*
1643 */
1644
1645static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1646{
1647 struct cmipci *cm = snd_pcm_substream_chip(substream);
1648 struct snd_pcm_runtime *runtime = substream->runtime;
1649 int err;
1650
1651 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1652 return err;
1653 runtime->hw = snd_cmipci_playback;
1654 if (cm->chip_version == 68) {
1655 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1656 SNDRV_PCM_RATE_96000;
1657 runtime->hw.rate_max = 96000;
1658 } else if (cm->chip_version == 55) {
1659 err = snd_pcm_hw_constraint_list(runtime, 0,
1660 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1661 if (err < 0)
1662 return err;
1663 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1664 runtime->hw.rate_max = 128000;
1665 }
1666 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1667 cm->dig_pcm_status = cm->dig_status;
1668 return 0;
1669}
1670
1671static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1672{
1673 struct cmipci *cm = snd_pcm_substream_chip(substream);
1674 struct snd_pcm_runtime *runtime = substream->runtime;
1675 int err;
1676
1677 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1678 return err;
1679 runtime->hw = snd_cmipci_capture;
1680 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1681 runtime->hw.rate_min = 41000;
1682 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1683 } else if (cm->chip_version == 55) {
1684 err = snd_pcm_hw_constraint_list(runtime, 0,
1685 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1686 if (err < 0)
1687 return err;
1688 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1689 runtime->hw.rate_max = 128000;
1690 }
1691 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1692 return 0;
1693}
1694
1695static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1696{
1697 struct cmipci *cm = snd_pcm_substream_chip(substream);
1698 struct snd_pcm_runtime *runtime = substream->runtime;
1699 int err;
1700
1701 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1702 return err;
1703 runtime->hw = snd_cmipci_playback2;
1704 mutex_lock(&cm->open_mutex);
1705 if (! cm->opened[CM_CH_PLAY]) {
1706 if (cm->can_multi_ch) {
1707 runtime->hw.channels_max = cm->max_channels;
1708 if (cm->max_channels == 4)
1709 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1710 else if (cm->max_channels == 6)
1711 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1712 else if (cm->max_channels == 8)
1713 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1714 }
1715 }
1716 mutex_unlock(&cm->open_mutex);
1717 if (cm->chip_version == 68) {
1718 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1719 SNDRV_PCM_RATE_96000;
1720 runtime->hw.rate_max = 96000;
1721 } else if (cm->chip_version == 55) {
1722 err = snd_pcm_hw_constraint_list(runtime, 0,
1723 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1724 if (err < 0)
1725 return err;
1726 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1727 runtime->hw.rate_max = 128000;
1728 }
1729 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1730 return 0;
1731}
1732
1733static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1734{
1735 struct cmipci *cm = snd_pcm_substream_chip(substream);
1736 struct snd_pcm_runtime *runtime = substream->runtime;
1737 int err;
1738
1739 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1740 return err;
1741 if (cm->can_ac3_hw) {
1742 runtime->hw = snd_cmipci_playback_spdif;
1743 if (cm->chip_version >= 37) {
1744 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1745 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1746 }
1747 if (cm->can_96k) {
1748 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1749 SNDRV_PCM_RATE_96000;
1750 runtime->hw.rate_max = 96000;
1751 }
1752 } else {
1753 runtime->hw = snd_cmipci_playback_iec958_subframe;
1754 }
1755 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1756 cm->dig_pcm_status = cm->dig_status;
1757 return 0;
1758}
1759
1760static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1761{
1762 struct cmipci *cm = snd_pcm_substream_chip(substream);
1763 struct snd_pcm_runtime *runtime = substream->runtime;
1764 int err;
1765
1766 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1767 return err;
1768 runtime->hw = snd_cmipci_capture_spdif;
1769 if (cm->can_96k && !(cm->chip_version == 68)) {
1770 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1771 SNDRV_PCM_RATE_96000;
1772 runtime->hw.rate_max = 96000;
1773 }
1774 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1775 return 0;
1776}
1777
1778
1779/*
1780 */
1781
1782static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1783{
1784 struct cmipci *cm = snd_pcm_substream_chip(substream);
1785 close_device_check(cm, CM_OPEN_PLAYBACK);
1786 return 0;
1787}
1788
1789static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1790{
1791 struct cmipci *cm = snd_pcm_substream_chip(substream);
1792 close_device_check(cm, CM_OPEN_CAPTURE);
1793 return 0;
1794}
1795
1796static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1797{
1798 struct cmipci *cm = snd_pcm_substream_chip(substream);
1799 close_device_check(cm, CM_OPEN_PLAYBACK2);
1800 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1801 return 0;
1802}
1803
1804static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1805{
1806 struct cmipci *cm = snd_pcm_substream_chip(substream);
1807 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1808 return 0;
1809}
1810
1811static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1812{
1813 struct cmipci *cm = snd_pcm_substream_chip(substream);
1814 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1815 return 0;
1816}
1817
1818
1819/*
1820 */
1821
1822static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1823 .open = snd_cmipci_playback_open,
1824 .close = snd_cmipci_playback_close,
1825 .hw_free = snd_cmipci_playback_hw_free,
1826 .prepare = snd_cmipci_playback_prepare,
1827 .trigger = snd_cmipci_playback_trigger,
1828 .pointer = snd_cmipci_playback_pointer,
1829};
1830
1831static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1832 .open = snd_cmipci_capture_open,
1833 .close = snd_cmipci_capture_close,
1834 .prepare = snd_cmipci_capture_prepare,
1835 .trigger = snd_cmipci_capture_trigger,
1836 .pointer = snd_cmipci_capture_pointer,
1837};
1838
1839static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1840 .open = snd_cmipci_playback2_open,
1841 .close = snd_cmipci_playback2_close,
1842 .hw_params = snd_cmipci_playback2_hw_params,
1843 .hw_free = snd_cmipci_playback2_hw_free,
1844 .prepare = snd_cmipci_capture_prepare, /* channel B */
1845 .trigger = snd_cmipci_capture_trigger, /* channel B */
1846 .pointer = snd_cmipci_capture_pointer, /* channel B */
1847};
1848
1849static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1850 .open = snd_cmipci_playback_spdif_open,
1851 .close = snd_cmipci_playback_spdif_close,
1852 .hw_free = snd_cmipci_playback_hw_free,
1853 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1854 .trigger = snd_cmipci_playback_trigger,
1855 .pointer = snd_cmipci_playback_pointer,
1856};
1857
1858static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1859 .open = snd_cmipci_capture_spdif_open,
1860 .close = snd_cmipci_capture_spdif_close,
1861 .hw_free = snd_cmipci_capture_spdif_hw_free,
1862 .prepare = snd_cmipci_capture_spdif_prepare,
1863 .trigger = snd_cmipci_capture_trigger,
1864 .pointer = snd_cmipci_capture_pointer,
1865};
1866
1867
1868/*
1869 */
1870
1871static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1872{
1873 struct snd_pcm *pcm;
1874 int err;
1875
1876 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1877 if (err < 0)
1878 return err;
1879
1880 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1881 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1882
1883 pcm->private_data = cm;
1884 pcm->info_flags = 0;
1885 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1886 cm->pcm = pcm;
1887
1888 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1889 &cm->pci->dev, 64*1024, 128*1024);
1890
1891 return 0;
1892}
1893
1894static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1895{
1896 struct snd_pcm *pcm;
1897 int err;
1898
1899 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1900 if (err < 0)
1901 return err;
1902
1903 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1904
1905 pcm->private_data = cm;
1906 pcm->info_flags = 0;
1907 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1908 cm->pcm2 = pcm;
1909
1910 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1911 &cm->pci->dev, 64*1024, 128*1024);
1912
1913 return 0;
1914}
1915
1916static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1917{
1918 struct snd_pcm *pcm;
1919 int err;
1920
1921 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1922 if (err < 0)
1923 return err;
1924
1925 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1926 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1927
1928 pcm->private_data = cm;
1929 pcm->info_flags = 0;
1930 strcpy(pcm->name, "C-Media PCI IEC958");
1931 cm->pcm_spdif = pcm;
1932
1933 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1934 &cm->pci->dev, 64*1024, 128*1024);
1935
1936 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1937 snd_pcm_alt_chmaps, cm->max_channels, 0,
1938 NULL);
1939 if (err < 0)
1940 return err;
1941
1942 return 0;
1943}
1944
1945/*
1946 * mixer interface:
1947 * - CM8338/8738 has a compatible mixer interface with SB16, but
1948 * lack of some elements like tone control, i/o gain and AGC.
1949 * - Access to native registers:
1950 * - A 3D switch
1951 * - Output mute switches
1952 */
1953
1954static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1955{
1956 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1957 outb(data, s->iobase + CM_REG_SB16_DATA);
1958}
1959
1960static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1961{
1962 unsigned char v;
1963
1964 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1965 v = inb(s->iobase + CM_REG_SB16_DATA);
1966 return v;
1967}
1968
1969/*
1970 * general mixer element
1971 */
1972struct cmipci_sb_reg {
1973 unsigned int left_reg, right_reg;
1974 unsigned int left_shift, right_shift;
1975 unsigned int mask;
1976 unsigned int invert: 1;
1977 unsigned int stereo: 1;
1978};
1979
1980#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1981 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1982
1983#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1984{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1985 .info = snd_cmipci_info_volume, \
1986 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1987 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1988}
1989
1990#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1991#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1992#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1993#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1994
1995static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1996{
1997 r->left_reg = val & 0xff;
1998 r->right_reg = (val >> 8) & 0xff;
1999 r->left_shift = (val >> 16) & 0x07;
2000 r->right_shift = (val >> 19) & 0x07;
2001 r->invert = (val >> 22) & 1;
2002 r->stereo = (val >> 23) & 1;
2003 r->mask = (val >> 24) & 0xff;
2004}
2005
2006static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2007 struct snd_ctl_elem_info *uinfo)
2008{
2009 struct cmipci_sb_reg reg;
2010
2011 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2012 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2013 uinfo->count = reg.stereo + 1;
2014 uinfo->value.integer.min = 0;
2015 uinfo->value.integer.max = reg.mask;
2016 return 0;
2017}
2018
2019static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2020 struct snd_ctl_elem_value *ucontrol)
2021{
2022 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2023 struct cmipci_sb_reg reg;
2024 int val;
2025
2026 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2027 spin_lock_irq(&cm->reg_lock);
2028 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2029 if (reg.invert)
2030 val = reg.mask - val;
2031 ucontrol->value.integer.value[0] = val;
2032 if (reg.stereo) {
2033 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2034 if (reg.invert)
2035 val = reg.mask - val;
2036 ucontrol->value.integer.value[1] = val;
2037 }
2038 spin_unlock_irq(&cm->reg_lock);
2039 return 0;
2040}
2041
2042static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2043 struct snd_ctl_elem_value *ucontrol)
2044{
2045 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2046 struct cmipci_sb_reg reg;
2047 int change;
2048 int left, right, oleft, oright;
2049
2050 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2051 left = ucontrol->value.integer.value[0] & reg.mask;
2052 if (reg.invert)
2053 left = reg.mask - left;
2054 left <<= reg.left_shift;
2055 if (reg.stereo) {
2056 right = ucontrol->value.integer.value[1] & reg.mask;
2057 if (reg.invert)
2058 right = reg.mask - right;
2059 right <<= reg.right_shift;
2060 } else
2061 right = 0;
2062 spin_lock_irq(&cm->reg_lock);
2063 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2064 left |= oleft & ~(reg.mask << reg.left_shift);
2065 change = left != oleft;
2066 if (reg.stereo) {
2067 if (reg.left_reg != reg.right_reg) {
2068 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2069 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2070 } else
2071 oright = left;
2072 right |= oright & ~(reg.mask << reg.right_shift);
2073 change |= right != oright;
2074 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2075 } else
2076 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2077 spin_unlock_irq(&cm->reg_lock);
2078 return change;
2079}
2080
2081/*
2082 * input route (left,right) -> (left,right)
2083 */
2084#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2085{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2086 .info = snd_cmipci_info_input_sw, \
2087 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2088 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2089}
2090
2091static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2092 struct snd_ctl_elem_info *uinfo)
2093{
2094 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2095 uinfo->count = 4;
2096 uinfo->value.integer.min = 0;
2097 uinfo->value.integer.max = 1;
2098 return 0;
2099}
2100
2101static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2102 struct snd_ctl_elem_value *ucontrol)
2103{
2104 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2105 struct cmipci_sb_reg reg;
2106 int val1, val2;
2107
2108 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2109 spin_lock_irq(&cm->reg_lock);
2110 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2111 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2112 spin_unlock_irq(&cm->reg_lock);
2113 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2114 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2115 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2116 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2117 return 0;
2118}
2119
2120static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2121 struct snd_ctl_elem_value *ucontrol)
2122{
2123 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2124 struct cmipci_sb_reg reg;
2125 int change;
2126 int val1, val2, oval1, oval2;
2127
2128 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2129 spin_lock_irq(&cm->reg_lock);
2130 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2131 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2132 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2133 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2134 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2135 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2136 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2137 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2138 change = val1 != oval1 || val2 != oval2;
2139 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2140 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2141 spin_unlock_irq(&cm->reg_lock);
2142 return change;
2143}
2144
2145/*
2146 * native mixer switches/volumes
2147 */
2148
2149#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2150{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2151 .info = snd_cmipci_info_native_mixer, \
2152 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2153 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2154}
2155
2156#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2157{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2158 .info = snd_cmipci_info_native_mixer, \
2159 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2160 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2161}
2162
2163#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2164{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2165 .info = snd_cmipci_info_native_mixer, \
2166 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2167 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2168}
2169
2170#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2171{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2172 .info = snd_cmipci_info_native_mixer, \
2173 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2174 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2175}
2176
2177static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2178 struct snd_ctl_elem_info *uinfo)
2179{
2180 struct cmipci_sb_reg reg;
2181
2182 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2183 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2184 uinfo->count = reg.stereo + 1;
2185 uinfo->value.integer.min = 0;
2186 uinfo->value.integer.max = reg.mask;
2187 return 0;
2188
2189}
2190
2191static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2192 struct snd_ctl_elem_value *ucontrol)
2193{
2194 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2195 struct cmipci_sb_reg reg;
2196 unsigned char oreg, val;
2197
2198 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2199 spin_lock_irq(&cm->reg_lock);
2200 oreg = inb(cm->iobase + reg.left_reg);
2201 val = (oreg >> reg.left_shift) & reg.mask;
2202 if (reg.invert)
2203 val = reg.mask - val;
2204 ucontrol->value.integer.value[0] = val;
2205 if (reg.stereo) {
2206 val = (oreg >> reg.right_shift) & reg.mask;
2207 if (reg.invert)
2208 val = reg.mask - val;
2209 ucontrol->value.integer.value[1] = val;
2210 }
2211 spin_unlock_irq(&cm->reg_lock);
2212 return 0;
2213}
2214
2215static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2216 struct snd_ctl_elem_value *ucontrol)
2217{
2218 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2219 struct cmipci_sb_reg reg;
2220 unsigned char oreg, nreg, val;
2221
2222 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2223 spin_lock_irq(&cm->reg_lock);
2224 oreg = inb(cm->iobase + reg.left_reg);
2225 val = ucontrol->value.integer.value[0] & reg.mask;
2226 if (reg.invert)
2227 val = reg.mask - val;
2228 nreg = oreg & ~(reg.mask << reg.left_shift);
2229 nreg |= (val << reg.left_shift);
2230 if (reg.stereo) {
2231 val = ucontrol->value.integer.value[1] & reg.mask;
2232 if (reg.invert)
2233 val = reg.mask - val;
2234 nreg &= ~(reg.mask << reg.right_shift);
2235 nreg |= (val << reg.right_shift);
2236 }
2237 outb(nreg, cm->iobase + reg.left_reg);
2238 spin_unlock_irq(&cm->reg_lock);
2239 return (nreg != oreg);
2240}
2241
2242/*
2243 * special case - check mixer sensitivity
2244 */
2245static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2246 struct snd_ctl_elem_value *ucontrol)
2247{
2248 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2249 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2250}
2251
2252static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2253 struct snd_ctl_elem_value *ucontrol)
2254{
2255 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2256 if (cm->mixer_insensitive) {
2257 /* ignored */
2258 return 0;
2259 }
2260 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2261}
2262
2263
2264static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2265 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2266 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2267 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2268 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2269 { /* switch with sensitivity */
2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271 .name = "PCM Playback Switch",
2272 .info = snd_cmipci_info_native_mixer,
2273 .get = snd_cmipci_get_native_mixer_sensitive,
2274 .put = snd_cmipci_put_native_mixer_sensitive,
2275 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2276 },
2277 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2278 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2279 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2280 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2281 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2282 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2283 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2284 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2285 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2286 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2287 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2288 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2289 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2290 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2291 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2292 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2293 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2294 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2295 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2296 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2297 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2298 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2299 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2300};
2301
2302/*
2303 * other switches
2304 */
2305
2306struct cmipci_switch_args {
2307 int reg; /* register index */
2308 unsigned int mask; /* mask bits */
2309 unsigned int mask_on; /* mask bits to turn on */
2310 unsigned int is_byte: 1; /* byte access? */
2311 unsigned int ac3_sensitive: 1; /* access forbidden during
2312 * non-audio operation?
2313 */
2314};
2315
2316#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2317
2318static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2319 struct snd_ctl_elem_value *ucontrol,
2320 struct cmipci_switch_args *args)
2321{
2322 unsigned int val;
2323 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2324
2325 spin_lock_irq(&cm->reg_lock);
2326 if (args->ac3_sensitive && cm->mixer_insensitive) {
2327 ucontrol->value.integer.value[0] = 0;
2328 spin_unlock_irq(&cm->reg_lock);
2329 return 0;
2330 }
2331 if (args->is_byte)
2332 val = inb(cm->iobase + args->reg);
2333 else
2334 val = snd_cmipci_read(cm, args->reg);
2335 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2336 spin_unlock_irq(&cm->reg_lock);
2337 return 0;
2338}
2339
2340static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2341 struct snd_ctl_elem_value *ucontrol)
2342{
2343 struct cmipci_switch_args *args;
2344 args = (struct cmipci_switch_args *)kcontrol->private_value;
2345 if (snd_BUG_ON(!args))
2346 return -EINVAL;
2347 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2348}
2349
2350static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2351 struct snd_ctl_elem_value *ucontrol,
2352 struct cmipci_switch_args *args)
2353{
2354 unsigned int val;
2355 int change;
2356 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2357
2358 spin_lock_irq(&cm->reg_lock);
2359 if (args->ac3_sensitive && cm->mixer_insensitive) {
2360 /* ignored */
2361 spin_unlock_irq(&cm->reg_lock);
2362 return 0;
2363 }
2364 if (args->is_byte)
2365 val = inb(cm->iobase + args->reg);
2366 else
2367 val = snd_cmipci_read(cm, args->reg);
2368 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2369 args->mask_on : (args->mask & ~args->mask_on));
2370 if (change) {
2371 val &= ~args->mask;
2372 if (ucontrol->value.integer.value[0])
2373 val |= args->mask_on;
2374 else
2375 val |= (args->mask & ~args->mask_on);
2376 if (args->is_byte)
2377 outb((unsigned char)val, cm->iobase + args->reg);
2378 else
2379 snd_cmipci_write(cm, args->reg, val);
2380 }
2381 spin_unlock_irq(&cm->reg_lock);
2382 return change;
2383}
2384
2385static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2386 struct snd_ctl_elem_value *ucontrol)
2387{
2388 struct cmipci_switch_args *args;
2389 args = (struct cmipci_switch_args *)kcontrol->private_value;
2390 if (snd_BUG_ON(!args))
2391 return -EINVAL;
2392 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2393}
2394
2395#ifndef TARGET_OS2
2396#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2397static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2398 .reg = xreg, \
2399 .mask = xmask, \
2400 .mask_on = xmask_on, \
2401 .is_byte = xis_byte, \
2402 .ac3_sensitive = xac3, \
2403}
2404#else
2405#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2406 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2407 xreg, \
2408 xmask, \
2409 xmask_on, \
2410 xis_byte, \
2411 xac3, \
2412 }
2413#endif
2414
2415#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2416 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2417
2418#if 0 /* these will be controlled in pcm device */
2419DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2420DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2421#endif
2422DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2423DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2424DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2425DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2426DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2427DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2428DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2429DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2430// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2431DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2432DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2433/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2434DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2435DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2436#if CM_CH_PLAY == 1
2437DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2438#else
2439DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2440#endif
2441DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2442// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2443// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2444// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2445DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2446
2447#define DEFINE_SWITCH(sname, stype, sarg) \
2448{ .name = sname, \
2449 .iface = stype, \
2450 .info = snd_cmipci_uswitch_info, \
2451 .get = snd_cmipci_uswitch_get, \
2452 .put = snd_cmipci_uswitch_put, \
2453 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2454}
2455
2456#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2457#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2458
2459
2460/*
2461 * callbacks for spdif output switch
2462 * needs toggle two registers..
2463 */
2464static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2465 struct snd_ctl_elem_value *ucontrol)
2466{
2467 int changed;
2468 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2469 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2470 return changed;
2471}
2472
2473static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2474 struct snd_ctl_elem_value *ucontrol)
2475{
2476 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2477 int changed;
2478 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2479 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2480 if (changed) {
2481 if (ucontrol->value.integer.value[0]) {
2482 if (chip->spdif_playback_avail)
2483 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2484 } else {
2485 if (chip->spdif_playback_avail)
2486 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2487 }
2488 }
2489 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2490 return changed;
2491}
2492
2493
2494static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2495 struct snd_ctl_elem_info *uinfo)
2496{
2497 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2498 static const char *const texts[3] = {
2499 "Line-In", "Rear Output", "Bass Output"
2500 };
2501
2502 return snd_ctl_enum_info(uinfo, 1,
2503 cm->chip_version >= 39 ? 3 : 2, texts);
2504}
2505
2506static inline unsigned int get_line_in_mode(struct cmipci *cm)
2507{
2508 unsigned int val;
2509 if (cm->chip_version >= 39) {
2510 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2511 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2512 return 2;
2513 }
2514 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2515 if (val & CM_REAR2LIN)
2516 return 1;
2517 return 0;
2518}
2519
2520static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2521 struct snd_ctl_elem_value *ucontrol)
2522{
2523 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2524
2525 spin_lock_irq(&cm->reg_lock);
2526 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2527 spin_unlock_irq(&cm->reg_lock);
2528 return 0;
2529}
2530
2531static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2532 struct snd_ctl_elem_value *ucontrol)
2533{
2534 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2535 int change;
2536
2537 spin_lock_irq(&cm->reg_lock);
2538 if (ucontrol->value.enumerated.item[0] == 2)
2539 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2540 else
2541 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2542 if (ucontrol->value.enumerated.item[0] == 1)
2543 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2544 else
2545 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2546 spin_unlock_irq(&cm->reg_lock);
2547 return change;
2548}
2549
2550static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2551 struct snd_ctl_elem_info *uinfo)
2552{
2553 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2554
2555 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2556}
2557
2558static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2559 struct snd_ctl_elem_value *ucontrol)
2560{
2561 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2562 /* same bit as spdi_phase */
2563 spin_lock_irq(&cm->reg_lock);
2564 ucontrol->value.enumerated.item[0] =
2565 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2566 spin_unlock_irq(&cm->reg_lock);
2567 return 0;
2568}
2569
2570static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2571 struct snd_ctl_elem_value *ucontrol)
2572{
2573 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2574 int change;
2575
2576 spin_lock_irq(&cm->reg_lock);
2577 if (ucontrol->value.enumerated.item[0])
2578 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2579 else
2580 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2581 spin_unlock_irq(&cm->reg_lock);
2582 return change;
2583}
2584
2585/* both for CM8338/8738 */
2586static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2587 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2588 {
2589 .name = "Line-In Mode",
2590 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2591 .info = snd_cmipci_line_in_mode_info,
2592 .get = snd_cmipci_line_in_mode_get,
2593 .put = snd_cmipci_line_in_mode_put,
2594 },
2595};
2596
2597/* for non-multichannel chips */
2598static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2599DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2600
2601/* only for CM8738 */
2602static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2603#if 0 /* controlled in pcm device */
2604 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2605 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2606 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2607#endif
2608 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2609 { .name = "IEC958 Output Switch",
2610 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2611 .info = snd_cmipci_uswitch_info,
2612 .get = snd_cmipci_spdout_enable_get,
2613 .put = snd_cmipci_spdout_enable_put,
2614 },
2615 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2616 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2617 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2618// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2619 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2620 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2621};
2622
2623/* only for model 033/037 */
2624static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2625 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2626 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2627 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2628};
2629
2630/* only for model 039 or later */
2631static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2632 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2633 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2634 {
2635 .name = "Mic-In Mode",
2636 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2637 .info = snd_cmipci_mic_in_mode_info,
2638 .get = snd_cmipci_mic_in_mode_get,
2639 .put = snd_cmipci_mic_in_mode_put,
2640 }
2641};
2642
2643/* card control switches */
2644static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2645DEFINE_CARD_SWITCH("Modem", modem);
2646
2647
2648static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2649{
2650 struct snd_card *card;
2651 const struct snd_kcontrol_new *sw;
2652 struct snd_kcontrol *kctl;
2653 unsigned int idx;
2654 int err;
2655
2656 if (snd_BUG_ON(!cm || !cm->card))
2657 return -EINVAL;
2658
2659 card = cm->card;
2660
2661 strcpy(card->mixername, "CMedia PCI");
2662
2663 spin_lock_irq(&cm->reg_lock);
2664 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2665 spin_unlock_irq(&cm->reg_lock);
2666
2667 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2668 if (cm->chip_version == 68) { // 8768 has no PCM volume
2669 if (!strcmp(snd_cmipci_mixers[idx].name,
2670 "PCM Playback Volume"))
2671 continue;
2672 }
2673 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2674 return err;
2675 }
2676
2677 /* mixer switches */
2678 sw = snd_cmipci_mixer_switches;
2679 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2680 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2681 if (err < 0)
2682 return err;
2683 }
2684 if (! cm->can_multi_ch) {
2685 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2686 if (err < 0)
2687 return err;
2688 }
2689 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2690 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2691 sw = snd_cmipci_8738_mixer_switches;
2692 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2693 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2694 if (err < 0)
2695 return err;
2696 }
2697 if (cm->can_ac3_hw) {
2698 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2699 return err;
2700 kctl->id.device = pcm_spdif_device;
2701 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2702 return err;
2703 kctl->id.device = pcm_spdif_device;
2704 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2705 return err;
2706 kctl->id.device = pcm_spdif_device;
2707 }
2708 if (cm->chip_version <= 37) {
2709 sw = snd_cmipci_old_mixer_switches;
2710 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2711 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2712 if (err < 0)
2713 return err;
2714 }
2715 }
2716 }
2717 if (cm->chip_version >= 39) {
2718 sw = snd_cmipci_extra_mixer_switches;
2719 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2720 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2721 if (err < 0)
2722 return err;
2723 }
2724 }
2725
2726 /* card switches */
2727 /*
2728 * newer chips don't have the register bits to force modem link
2729 * detection; the bit that was FLINKON now mutes CH1
2730 */
2731 if (cm->chip_version < 39) {
2732 err = snd_ctl_add(cm->card,
2733 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2734 if (err < 0)
2735 return err;
2736 }
2737
2738 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2739 struct snd_ctl_elem_id elem_id;
2740 struct snd_kcontrol *ctl;
2741 memset(&elem_id, 0, sizeof(elem_id));
2742 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2743 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2744 ctl = snd_ctl_find_id(cm->card, &elem_id);
2745 if (ctl)
2746 cm->mixer_res_ctl[idx] = ctl;
2747 }
2748
2749 return 0;
2750}
2751
2752
2753/*
2754 * proc interface
2755 */
2756
2757static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2758 struct snd_info_buffer *buffer)
2759{
2760 struct cmipci *cm = entry->private_data;
2761 int i, v;
2762
2763 snd_iprintf(buffer, "%s\n", cm->card->longname);
2764 for (i = 0; i < 0x94; i++) {
2765 if (i == 0x28)
2766 i = 0x90;
2767 v = inb(cm->iobase + i);
2768 if (i % 4 == 0)
2769 snd_iprintf(buffer, "\n%02x:", i);
2770 snd_iprintf(buffer, " %02x", v);
2771 }
2772 snd_iprintf(buffer, "\n");
2773}
2774
2775static void snd_cmipci_proc_init(struct cmipci *cm)
2776{
2777 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2778}
2779
2780static const struct pci_device_id snd_cmipci_ids[] = {
2781 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2782 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2783 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2784 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2785 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2786 {0,},
2787};
2788
2789
2790/*
2791 * check chip version and capabilities
2792 * driver name is modified according to the chip model
2793 */
2794static void query_chip(struct cmipci *cm)
2795{
2796 unsigned int detect;
2797
2798 /* check reg 0Ch, bit 24-31 */
2799 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2800 if (! detect) {
2801 /* check reg 08h, bit 24-28 */
2802 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2803 switch (detect) {
2804 case 0:
2805 cm->chip_version = 33;
2806 if (cm->do_soft_ac3)
2807 cm->can_ac3_sw = 1;
2808 else
2809 cm->can_ac3_hw = 1;
2810 break;
2811 case CM_CHIP_037:
2812 cm->chip_version = 37;
2813 cm->can_ac3_hw = 1;
2814 break;
2815 default:
2816 cm->chip_version = 39;
2817 cm->can_ac3_hw = 1;
2818 break;
2819 }
2820 cm->max_channels = 2;
2821 } else {
2822 if (detect & CM_CHIP_039) {
2823 cm->chip_version = 39;
2824 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2825 cm->max_channels = 6;
2826 else
2827 cm->max_channels = 4;
2828 } else if (detect & CM_CHIP_8768) {
2829 cm->chip_version = 68;
2830 cm->max_channels = 8;
2831 cm->can_96k = 1;
2832 } else {
2833 cm->chip_version = 55;
2834 cm->max_channels = 6;
2835 cm->can_96k = 1;
2836 }
2837 cm->can_ac3_hw = 1;
2838 cm->can_multi_ch = 1;
2839 }
2840}
2841
2842#ifdef SUPPORT_JOYSTICK
2843static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2844{
2845 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2846 struct gameport *gp;
2847 struct resource *r = NULL;
2848 int i, io_port = 0;
2849
2850 if (joystick_port[dev] == 0)
2851 return -ENODEV;
2852
2853 if (joystick_port[dev] == 1) { /* auto-detect */
2854 for (i = 0; ports[i]; i++) {
2855 io_port = ports[i];
2856 r = request_region(io_port, 1, "CMIPCI gameport");
2857 if (r)
2858 break;
2859 }
2860 } else {
2861 io_port = joystick_port[dev];
2862 r = request_region(io_port, 1, "CMIPCI gameport");
2863 }
2864
2865 if (!r) {
2866 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2867 return -EBUSY;
2868 }
2869
2870 cm->gameport = gp = gameport_allocate_port();
2871 if (!gp) {
2872 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2873 release_and_free_resource(r);
2874 return -ENOMEM;
2875 }
2876 gameport_set_name(gp, "C-Media Gameport");
2877 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2878 gameport_set_dev_parent(gp, &cm->pci->dev);
2879 gp->io = io_port;
2880 gameport_set_port_data(gp, r);
2881
2882 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2883
2884 gameport_register_port(cm->gameport);
2885
2886 return 0;
2887}
2888
2889static void snd_cmipci_free_gameport(struct cmipci *cm)
2890{
2891 if (cm->gameport) {
2892 struct resource *r = gameport_get_port_data(cm->gameport);
2893
2894 gameport_unregister_port(cm->gameport);
2895 cm->gameport = NULL;
2896
2897 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2898 release_and_free_resource(r);
2899 }
2900}
2901#else
2902static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2903static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2904#endif
2905
2906static int snd_cmipci_free(struct cmipci *cm)
2907{
2908 if (cm->irq >= 0) {
2909 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2910 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2911 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2912 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2913 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2914 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2915 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2916
2917 /* reset mixer */
2918 snd_cmipci_mixer_write(cm, 0, 0);
2919
2920 free_irq(cm->irq, cm);
2921 }
2922
2923 snd_cmipci_free_gameport(cm);
2924 pci_release_regions(cm->pci);
2925 pci_disable_device(cm->pci);
2926 kfree(cm);
2927 return 0;
2928}
2929
2930static int snd_cmipci_dev_free(struct snd_device *device)
2931{
2932 struct cmipci *cm = device->device_data;
2933 return snd_cmipci_free(cm);
2934}
2935
2936static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2937{
2938 long iosynth;
2939 unsigned int val;
2940 struct snd_opl3 *opl3;
2941 int err;
2942
2943 if (!fm_port)
2944 goto disable_fm;
2945
2946 if (cm->chip_version >= 39) {
2947 /* first try FM regs in PCI port range */
2948 iosynth = cm->iobase + CM_REG_FM_PCI;
2949 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2950 OPL3_HW_OPL3, 1, &opl3);
2951 } else {
2952 err = -EIO;
2953 }
2954 if (err < 0) {
2955 /* then try legacy ports */
2956 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2957 iosynth = fm_port;
2958 switch (iosynth) {
2959 case 0x3E8: val |= CM_FMSEL_3E8; break;
2960 case 0x3E0: val |= CM_FMSEL_3E0; break;
2961 case 0x3C8: val |= CM_FMSEL_3C8; break;
2962 case 0x388: val |= CM_FMSEL_388; break;
2963 default:
2964 goto disable_fm;
2965 }
2966 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2967 /* enable FM */
2968 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2969
2970 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2971 OPL3_HW_OPL3, 0, &opl3) < 0) {
2972 dev_err(cm->card->dev,
2973 "no OPL device at %#lx, skipping...\n",
2974 iosynth);
2975 goto disable_fm;
2976 }
2977 }
2978 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2979 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2980 return err;
2981 }
2982 return 0;
2983
2984 disable_fm:
2985 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2986 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2987 return 0;
2988}
2989
2990static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2991 int dev, struct cmipci **rcmipci)
2992{
2993 struct cmipci *cm;
2994 int err;
2995 static const struct snd_device_ops ops = {
2996 .dev_free = snd_cmipci_dev_free,
2997 };
2998 unsigned int val;
2999 long iomidi = 0;
3000 int integrated_midi = 0;
3001 char modelstr[16];
3002 int pcm_index, pcm_spdif_index;
3003 static const struct pci_device_id intel_82437vx[] = {
3004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3005 {0},
3006 };
3007
3008 *rcmipci = NULL;
3009
3010 if ((err = pci_enable_device(pci)) < 0)
3011 return err;
3012
3013 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3014 if (cm == NULL) {
3015 pci_disable_device(pci);
3016 return -ENOMEM;
3017 }
3018
3019 spin_lock_init(&cm->reg_lock);
3020 mutex_init(&cm->open_mutex);
3021 cm->device = pci->device;
3022 cm->card = card;
3023 cm->pci = pci;
3024 cm->irq = -1;
3025 cm->channel[0].ch = 0;
3026 cm->channel[1].ch = 1;
3027 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3028
3029 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3030 kfree(cm);
3031 pci_disable_device(pci);
3032 return err;
3033 }
3034 cm->iobase = pci_resource_start(pci, 0);
3035
3036 if (request_irq(pci->irq, snd_cmipci_interrupt,
3037 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3038 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3039 snd_cmipci_free(cm);
3040 return -EBUSY;
3041 }
3042 cm->irq = pci->irq;
3043 card->sync_irq = cm->irq;
3044
3045 pci_set_master(cm->pci);
3046
3047 /*
3048 * check chip version, max channels and capabilities
3049 */
3050
3051 cm->chip_version = 0;
3052 cm->max_channels = 2;
3053 cm->do_soft_ac3 = soft_ac3[dev];
3054
3055 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3056 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3057 query_chip(cm);
3058 /* added -MCx suffix for chip supporting multi-channels */
3059 if (cm->can_multi_ch)
3060 sprintf(cm->card->driver + strlen(cm->card->driver),
3061 "-MC%d", cm->max_channels);
3062 else if (cm->can_ac3_sw)
3063 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3064
3065 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3066 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3067
3068#if CM_CH_PLAY == 1
3069 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3070#else
3071 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3072#endif
3073
3074 /* initialize codec registers */
3075 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3076 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3077 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3078 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3079 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3080 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3081 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3082
3083 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3084 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3085#if CM_CH_PLAY == 1
3086 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3087#else
3088 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3089#endif
3090 if (cm->chip_version) {
3091 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3092 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3093 }
3094 /* Set Bus Master Request */
3095 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3096
3097 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3098 switch (pci->device) {
3099 case PCI_DEVICE_ID_CMEDIA_CM8738:
3100 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3101 if (!pci_dev_present(intel_82437vx))
3102 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3103 break;
3104 default:
3105 break;
3106 }
3107
3108 if (cm->chip_version < 68) {
3109 val = pci->device < 0x110 ? 8338 : 8738;
3110 } else {
3111 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3112 case 0:
3113 val = 8769;
3114 break;
3115 case 2:
3116 val = 8762;
3117 break;
3118 default:
3119 switch ((pci->subsystem_vendor << 16) |
3120 pci->subsystem_device) {
3121 case 0x13f69761:
3122 case 0x584d3741:
3123 case 0x584d3751:
3124 case 0x584d3761:
3125 case 0x584d3771:
3126 case 0x72848384:
3127 val = 8770;
3128 break;
3129 default:
3130 val = 8768;
3131 break;
3132 }
3133 }
3134 }
3135 sprintf(card->shortname, "C-Media CMI%d", val);
3136 if (cm->chip_version < 68)
3137 sprintf(modelstr, " (model %d)", cm->chip_version);
3138 else
3139 modelstr[0] = '\0';
3140 sprintf(card->longname, "%s%s at %#lx, irq %i",
3141 card->shortname, modelstr, cm->iobase, cm->irq);
3142
3143 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3144 snd_cmipci_free(cm);
3145 return err;
3146 }
3147
3148 if (cm->chip_version >= 39) {
3149 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3150 if (val != 0x00 && val != 0xff) {
3151 if (mpu_port[dev])
3152 iomidi = cm->iobase + CM_REG_MPU_PCI;
3153 integrated_midi = 1;
3154 }
3155 }
3156 if (!integrated_midi) {
3157 val = 0;
3158 iomidi = mpu_port[dev];
3159 switch (iomidi) {
3160 case 0x320: val = CM_VMPU_320; break;
3161 case 0x310: val = CM_VMPU_310; break;
3162 case 0x300: val = CM_VMPU_300; break;
3163 case 0x330: val = CM_VMPU_330; break;
3164 default:
3165 iomidi = 0; break;
3166 }
3167 if (iomidi > 0) {
3168 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3169 /* enable UART */
3170 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3171 if (inb(iomidi + 1) == 0xff) {
3172 dev_err(cm->card->dev,
3173 "cannot enable MPU-401 port at %#lx\n",
3174 iomidi);
3175 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3176 CM_UART_EN);
3177 iomidi = 0;
3178 }
3179 }
3180 }
3181
3182 if (cm->chip_version < 68) {
3183 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3184 if (err < 0)
3185 return err;
3186 }
3187
3188 /* reset mixer */
3189 snd_cmipci_mixer_write(cm, 0, 0);
3190
3191 snd_cmipci_proc_init(cm);
3192
3193 /* create pcm devices */
3194 pcm_index = pcm_spdif_index = 0;
3195 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3196 return err;
3197 pcm_index++;
3198 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3199 return err;
3200 pcm_index++;
3201 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3202 pcm_spdif_index = pcm_index;
3203 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3204 return err;
3205 }
3206
3207 /* create mixer interface & switches */
3208 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3209 return err;
3210
3211 if (iomidi > 0) {
3212 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3213 iomidi,
3214 (integrated_midi ?
3215 MPU401_INFO_INTEGRATED : 0) |
3216 MPU401_INFO_IRQ_HOOK,
3217 -1, &cm->rmidi)) < 0) {
3218 dev_err(cm->card->dev,
3219 "no UART401 device at 0x%lx\n", iomidi);
3220 }
3221 }
3222
3223#ifdef USE_VAR48KRATE
3224 for (val = 0; val < ARRAY_SIZE(rates); val++)
3225 snd_cmipci_set_pll(cm, rates[val], val);
3226
3227 /*
3228 * (Re-)Enable external switch spdo_48k
3229 */
3230 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3231#endif /* USE_VAR48KRATE */
3232
3233 if (snd_cmipci_create_gameport(cm, dev) < 0)
3234 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3235
3236 *rcmipci = cm;
3237 return 0;
3238}
3239
3240/*
3241 */
3242
3243MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3244
3245static int snd_cmipci_probe(struct pci_dev *pci,
3246 const struct pci_device_id *pci_id)
3247{
3248 static int dev;
3249 struct snd_card *card;
3250 struct cmipci *cm;
3251 int err;
3252
3253 if (dev >= SNDRV_CARDS)
3254 return -ENODEV;
3255 if (! enable[dev]) {
3256 dev++;
3257 return -ENOENT;
3258 }
3259
3260 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3261 0, &card);
3262 if (err < 0)
3263 return err;
3264
3265 switch (pci->device) {
3266 case PCI_DEVICE_ID_CMEDIA_CM8738:
3267 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3268 strcpy(card->driver, "CMI8738");
3269 break;
3270 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3271 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3272 strcpy(card->driver, "CMI8338");
3273 break;
3274 default:
3275 strcpy(card->driver, "CMIPCI");
3276 break;
3277 }
3278
3279 err = snd_cmipci_create(card, pci, dev, &cm);
3280 if (err < 0)
3281 goto free_card;
3282
3283 card->private_data = cm;
3284
3285 err = snd_card_register(card);
3286 if (err < 0)
3287 goto free_card;
3288
3289 pci_set_drvdata(pci, card);
3290 dev++;
3291 return 0;
3292
3293free_card:
3294 snd_card_free(card);
3295 return err;
3296}
3297
3298static void snd_cmipci_remove(struct pci_dev *pci)
3299{
3300 snd_card_free(pci_get_drvdata(pci));
3301}
3302
3303
3304#ifdef CONFIG_PM_SLEEP
3305/*
3306 * power management
3307 */
3308static const unsigned char saved_regs[] = {
3309 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3310 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3311 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3312 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3313 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3314};
3315
3316static const unsigned char saved_mixers[] = {
3317 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3318 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3319 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3320 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3321 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3322 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3323 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3324 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3325};
3326
3327static int snd_cmipci_suspend(struct device *dev)
3328{
3329 struct snd_card *card = dev_get_drvdata(dev);
3330 struct cmipci *cm = card->private_data;
3331 int i;
3332
3333 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3334
3335 /* save registers */
3336 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3337 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3338 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3339 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3340
3341 /* disable ints */
3342 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3343 return 0;
3344}
3345
3346static int snd_cmipci_resume(struct device *dev)
3347{
3348 struct snd_card *card = dev_get_drvdata(dev);
3349 struct cmipci *cm = card->private_data;
3350 int i;
3351
3352 /* reset / initialize to a sane state */
3353 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3354 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3355 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3356 snd_cmipci_mixer_write(cm, 0, 0);
3357
3358 /* restore registers */
3359 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3360 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3361 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3362 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3363
3364 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3365 return 0;
3366}
3367
3368static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3369#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3370#else
3371#define SND_CMIPCI_PM_OPS NULL
3372#endif /* CONFIG_PM_SLEEP */
3373
3374static struct pci_driver cmipci_driver = {
3375 .name = KBUILD_MODNAME,
3376 .id_table = snd_cmipci_ids,
3377 .probe = snd_cmipci_probe,
3378 .remove = snd_cmipci_remove,
3379 .driver = {
3380 .pm = SND_CMIPCI_PM_OPS,
3381 },
3382};
3383
3384module_pci_driver(cmipci_driver);
Note: See TracBrowser for help on using the repository browser.