source: GPL/trunk/alsa-kernel/pci/atiixp.c@ 703

Last change on this file since 703 was 703, checked in by David Azarewicz, 4 years ago

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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
4 *
5 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
6 */
7
8#include <linux/io.h>
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <sound/core.h>
17#include <sound/pcm.h>
18#include <sound/pcm_params.h>
19#include <sound/info.h>
20#include <sound/ac97_codec.h>
21#include <sound/initval.h>
22
23#ifdef TARGET_OS2
24#define KBUILD_MODNAME "atiixp"
25#endif
26
27MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
28MODULE_DESCRIPTION("ATI IXP AC97 controller");
29MODULE_LICENSE("GPL");
30
31static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
32static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
33static int ac97_clock = 48000;
34static char *ac97_quirk;
35static bool spdif_aclink = 1;
36static int ac97_codec = -1;
37
38module_param(index, int, 0444);
39MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
40module_param(id, charp, 0444);
41MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
42module_param(ac97_clock, int, 0444);
43MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
44module_param(ac97_quirk, charp, 0444);
45MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
46module_param(ac97_codec, int, 0444);
47MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
48module_param(spdif_aclink, bool, 0444);
49MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
50
51/* just for backward compatibility */
52//static bool enable;
53module_param(enable, bool, 0444);
54
55
56/*
57 */
58
59#define ATI_REG_ISR 0x00 /* interrupt source */
60#define ATI_REG_ISR_IN_XRUN (1U<<0)
61#define ATI_REG_ISR_IN_STATUS (1U<<1)
62#define ATI_REG_ISR_OUT_XRUN (1U<<2)
63#define ATI_REG_ISR_OUT_STATUS (1U<<3)
64#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
65#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
66#define ATI_REG_ISR_PHYS_INTR (1U<<8)
67#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
68#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
69#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
70#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
71#define ATI_REG_ISR_NEW_FRAME (1U<<13)
72
73#define ATI_REG_IER 0x04 /* interrupt enable */
74#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
75#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
76#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
77#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
78#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
79#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
80#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
81#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
82#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
83#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
84#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
85#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
86#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
87
88#define ATI_REG_CMD 0x08 /* command */
89#define ATI_REG_CMD_POWERDOWN (1U<<0)
90#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
91#define ATI_REG_CMD_SEND_EN (1U<<2)
92#define ATI_REG_CMD_STATUS_MEM (1U<<3)
93#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
94#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
95#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
96#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
97#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
98#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
99#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
100#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
101#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
102#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
103#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
104#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
105#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
106#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
107#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
108#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
109#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
110#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
111#define ATI_REG_CMD_PACKED_DIS (1U<<24)
112#define ATI_REG_CMD_BURST_EN (1U<<25)
113#define ATI_REG_CMD_PANIC_EN (1U<<26)
114#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
115#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
116#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
117#define ATI_REG_CMD_AC_SYNC (1U<<30)
118#define ATI_REG_CMD_AC_RESET (1U<<31)
119
120#define ATI_REG_PHYS_OUT_ADDR 0x0c
121#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
122#define ATI_REG_PHYS_OUT_RW (1U<<2)
123#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
124#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
125#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
126
127#define ATI_REG_PHYS_IN_ADDR 0x10
128#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
129#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
130#define ATI_REG_PHYS_IN_DATA_SHIFT 16
131
132#define ATI_REG_SLOTREQ 0x14
133
134#define ATI_REG_COUNTER 0x18
135#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
136#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
137
138#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
139
140#define ATI_REG_IN_DMA_LINKPTR 0x20
141#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
142#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
143#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
144#define ATI_REG_IN_DMA_DT_SIZE 0x30
145
146#define ATI_REG_OUT_DMA_SLOT 0x34
147#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
148#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
149#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
150#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
151
152#define ATI_REG_OUT_DMA_LINKPTR 0x38
153#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
154#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
155#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
156#define ATI_REG_OUT_DMA_DT_SIZE 0x48
157
158#define ATI_REG_SPDF_CMD 0x4c
159#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
160#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
161#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
162
163#define ATI_REG_SPDF_DMA_LINKPTR 0x50
164#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
165#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
166#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
167#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
168
169#define ATI_REG_MODEM_MIRROR 0x7c
170#define ATI_REG_AUDIO_MIRROR 0x80
171
172#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
173#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
174
175#define ATI_REG_FIFO_FLUSH 0x88
176#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
177#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
178
179/* LINKPTR */
180#define ATI_REG_LINKPTR_EN (1U<<0)
181
182/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
183#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
184#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
185#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
186#define ATI_REG_DMA_STATE (7U<<26)
187
188
189#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
190
191
192struct atiixp;
193
194/*
195 * DMA packate descriptor
196 */
197
198struct atiixp_dma_desc {
199 __le32 addr; /* DMA buffer address */
200 u16 status; /* status bits */
201 u16 size; /* size of the packet in dwords */
202 __le32 next; /* address of the next packet descriptor */
203};
204
205/*
206 * stream enum
207 */
208enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
209enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
210enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
211
212#define NUM_ATI_CODECS 3
213
214
215/*
216 * constants and callbacks for each DMA type
217 */
218struct atiixp_dma_ops {
219 int type; /* ATI_DMA_XXX */
220 unsigned int llp_offset; /* LINKPTR offset */
221 unsigned int dt_cur; /* DT_CUR offset */
222 /* called from open callback */
223 void (*enable_dma)(struct atiixp *chip, int on);
224 /* called from trigger (START/STOP) */
225 void (*enable_transfer)(struct atiixp *chip, int on);
226 /* called from trigger (STOP only) */
227 void (*flush_dma)(struct atiixp *chip);
228};
229
230/*
231 * DMA stream
232 */
233struct atiixp_dma {
234 const struct atiixp_dma_ops *ops;
235 struct snd_dma_buffer desc_buf;
236 struct snd_pcm_substream *substream; /* assigned PCM substream */
237 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
238 unsigned int period_bytes, periods;
239 int opened;
240 int running;
241 int suspended;
242 int pcm_open_flag;
243 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
244 unsigned int saved_curptr;
245};
246
247/*
248 * ATI IXP chip
249 */
250struct atiixp {
251 struct snd_card *card;
252 struct pci_dev *pci;
253
254 unsigned long addr;
255 void __iomem *remap_addr;
256 int irq;
257
258 struct snd_ac97_bus *ac97_bus;
259 struct snd_ac97 *ac97[NUM_ATI_CODECS];
260
261 spinlock_t reg_lock;
262
263 struct atiixp_dma dmas[NUM_ATI_DMAS];
264 struct ac97_pcm *pcms[NUM_ATI_PCMS];
265 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
266
267 int max_channels; /* max. channels for PCM out */
268
269 unsigned int codec_not_ready_bits; /* for codec detection */
270
271 int spdif_over_aclink; /* passed from the module option */
272 struct mutex open_mutex; /* playback open mutex */
273};
274
275
276/*
277 */
278static const struct pci_device_id snd_atiixp_ids[] = {
279 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
280 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
281 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
282 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
283 { 0, }
284};
285
286MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
287
288static const struct snd_pci_quirk atiixp_quirks[] = {
289 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
290 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
291 {0} /* terminator */
292};
293
294/*
295 * lowlevel functions
296 */
297
298/*
299 * update the bits of the given register.
300 * return 1 if the bits changed.
301 */
302static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
303 unsigned int mask, unsigned int value)
304{
305 void __iomem *addr = chip->remap_addr + reg;
306 unsigned int data, old_data;
307 old_data = data = readl(addr);
308 data &= ~mask;
309 data |= value;
310 if (old_data == data)
311 return 0;
312 writel(data, addr);
313 return 1;
314}
315
316/*
317 * macros for easy use
318 */
319#define atiixp_write(chip,reg,value) \
320 writel(value, chip->remap_addr + ATI_REG_##reg)
321#define atiixp_read(chip,reg) \
322 readl(chip->remap_addr + ATI_REG_##reg)
323#define atiixp_update(chip,reg,mask,val) \
324 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
325
326/*
327 * handling DMA packets
328 *
329 * we allocate a linear buffer for the DMA, and split it to each packet.
330 * in a future version, a scatter-gather buffer should be implemented.
331 */
332
333#define ATI_DESC_LIST_SIZE \
334 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
335
336/*
337 * build packets ring for the given buffer size.
338 *
339 * IXP handles the buffer descriptors, which are connected as a linked
340 * list. although we can change the list dynamically, in this version,
341 * a static RING of buffer descriptors is used.
342 *
343 * the ring is built in this function, and is set up to the hardware.
344 */
345static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
346 struct snd_pcm_substream *substream,
347 unsigned int periods,
348 unsigned int period_bytes)
349{
350 unsigned int i;
351 u32 addr, desc_addr;
352 unsigned long flags;
353
354 if (periods > ATI_MAX_DESCRIPTORS)
355 return -ENOMEM;
356
357 if (dma->desc_buf.area == NULL) {
358 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
359 &chip->pci->dev,
360 ATI_DESC_LIST_SIZE,
361 &dma->desc_buf) < 0)
362 return -ENOMEM;
363 dma->period_bytes = dma->periods = 0; /* clear */
364 }
365
366 if (dma->periods == periods && dma->period_bytes == period_bytes) {
367 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
368 (char*)chip->remap_addr + dma->ops->llp_offset);
369 return 0;
370 }
371
372 /* reset DMA before changing the descriptor table */
373 spin_lock_irqsave(&chip->reg_lock, flags);
374 writel(0, chip->remap_addr + dma->ops->llp_offset);
375 dma->ops->enable_dma(chip, 0);
376 dma->ops->enable_dma(chip, 1);
377 spin_unlock_irqrestore(&chip->reg_lock, flags);
378
379 /* fill the entries */
380 addr = (u32)substream->runtime->dma_addr;
381 desc_addr = (u32)dma->desc_buf.addr;
382 for (i = 0; i < periods; i++) {
383 struct atiixp_dma_desc *desc;
384 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
385 desc->addr = cpu_to_le32(addr);
386 desc->status = 0;
387 desc->size = period_bytes >> 2; /* in dwords */
388 desc_addr += sizeof(struct atiixp_dma_desc);
389 if (i == periods - 1)
390 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
391 else
392 desc->next = cpu_to_le32(desc_addr);
393 addr += period_bytes;
394 }
395
396 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
397 chip->remap_addr + dma->ops->llp_offset);
398
399 dma->period_bytes = period_bytes;
400 dma->periods = periods;
401
402 return 0;
403}
404
405/*
406 * remove the ring buffer and release it if assigned
407 */
408static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
409 struct snd_pcm_substream *substream)
410{
411 if (dma->desc_buf.area) {
412 writel(0, chip->remap_addr + dma->ops->llp_offset);
413 snd_dma_free_pages(&dma->desc_buf);
414 dma->desc_buf.area = NULL;
415 }
416}
417
418/*
419 * AC97 interface
420 */
421static int snd_atiixp_acquire_codec(struct atiixp *chip)
422{
423 int timeout = 1000;
424
425 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
426 if (! timeout--) {
427 dev_warn(chip->card->dev, "codec acquire timeout\n");
428 return -EBUSY;
429 }
430 udelay(1);
431 }
432 return 0;
433}
434
435static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
436{
437 unsigned int data;
438 int timeout;
439
440 if (snd_atiixp_acquire_codec(chip) < 0)
441 return 0xffff;
442 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
443 ATI_REG_PHYS_OUT_ADDR_EN |
444 ATI_REG_PHYS_OUT_RW |
445 codec;
446 atiixp_write(chip, PHYS_OUT_ADDR, data);
447 if (snd_atiixp_acquire_codec(chip) < 0)
448 return 0xffff;
449 timeout = 1000;
450 do {
451 data = atiixp_read(chip, PHYS_IN_ADDR);
452 if (data & ATI_REG_PHYS_IN_READ_FLAG)
453 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
454 udelay(1);
455 } while (--timeout);
456 /* time out may happen during reset */
457 if (reg < 0x7c)
458 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
459 return 0xffff;
460}
461
462
463static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
464 unsigned short reg, unsigned short val)
465{
466 unsigned int data;
467
468 if (snd_atiixp_acquire_codec(chip) < 0)
469 return;
470 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
471 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
472 ATI_REG_PHYS_OUT_ADDR_EN | codec;
473 atiixp_write(chip, PHYS_OUT_ADDR, data);
474}
475
476
477static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
478 unsigned short reg)
479{
480 struct atiixp *chip = ac97->private_data;
481 return snd_atiixp_codec_read(chip, ac97->num, reg);
482
483}
484
485static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
486 unsigned short val)
487{
488 struct atiixp *chip = ac97->private_data;
489 snd_atiixp_codec_write(chip, ac97->num, reg, val);
490}
491
492/*
493 * reset AC link
494 */
495static int snd_atiixp_aclink_reset(struct atiixp *chip)
496{
497 int timeout;
498
499 /* reset powerdoewn */
500 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
501 udelay(10);
502
503 /* perform a software reset */
504 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
505#pragma disable_message (302)
506 atiixp_read(chip, CMD);
507 udelay(10);
508 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
509
510 timeout = 10;
511 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
512 /* do a hard reset */
513 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
514 ATI_REG_CMD_AC_SYNC);
515 atiixp_read(chip, CMD);
516 mdelay(1);
517 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
518 if (!--timeout) {
519 dev_err(chip->card->dev, "codec reset timeout\n");
520 break;
521 }
522 }
523#pragma enable_message (302)
524
525 /* deassert RESET and assert SYNC to make sure */
526 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
527 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
528
529 return 0;
530}
531
532#ifdef CONFIG_PM_SLEEP
533static int snd_atiixp_aclink_down(struct atiixp *chip)
534{
535 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
536 // return -EBUSY;
537 atiixp_update(chip, CMD,
538 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
539 ATI_REG_CMD_POWERDOWN);
540 return 0;
541}
542#endif
543
544/*
545 * auto-detection of codecs
546 *
547 * the IXP chip can generate interrupts for the non-existing codecs.
548 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
549 * even if all three codecs are connected.
550 */
551
552#define ALL_CODEC_NOT_READY \
553 (ATI_REG_ISR_CODEC0_NOT_READY |\
554 ATI_REG_ISR_CODEC1_NOT_READY |\
555 ATI_REG_ISR_CODEC2_NOT_READY)
556#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
557
558static int ac97_probing_bugs(struct pci_dev *pci)
559{
560 const struct snd_pci_quirk *q;
561
562 q = snd_pci_quirk_lookup(pci, atiixp_quirks);
563 if (q) {
564 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n",
565 snd_pci_quirk_name(q), q->value);
566
567 return q->value;
568 }
569 /* this hardware doesn't need workarounds. Probe for codec */
570 return -1;
571}
572
573static int snd_atiixp_codec_detect(struct atiixp *chip)
574{
575 int timeout;
576
577 chip->codec_not_ready_bits = 0;
578 if (ac97_codec == -1)
579 ac97_codec = ac97_probing_bugs(chip->pci);
580 if (ac97_codec >= 0) {
581 chip->codec_not_ready_bits |=
582 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
583 return 0;
584 }
585
586 atiixp_write(chip, IER, CODEC_CHECK_BITS);
587 /* wait for the interrupts */
588 timeout = 50;
589 while (timeout-- > 0) {
590 mdelay(1);
591 if (chip->codec_not_ready_bits)
592 break;
593 }
594 atiixp_write(chip, IER, 0); /* disable irqs */
595
596 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
597 dev_err(chip->card->dev, "no codec detected!\n");
598 return -ENXIO;
599 }
600 return 0;
601}
602
603
604/*
605 * enable DMA and irqs
606 */
607static int snd_atiixp_chip_start(struct atiixp *chip)
608{
609 unsigned int reg;
610
611 /* set up spdif, enable burst mode */
612 reg = atiixp_read(chip, CMD);
613 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
614 reg |= ATI_REG_CMD_BURST_EN;
615 atiixp_write(chip, CMD, reg);
616
617 reg = atiixp_read(chip, SPDF_CMD);
618 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
619 atiixp_write(chip, SPDF_CMD, reg);
620
621 /* clear all interrupt source */
622 atiixp_write(chip, ISR, 0xffffffff);
623 /* enable irqs */
624 atiixp_write(chip, IER,
625 ATI_REG_IER_IO_STATUS_EN |
626 ATI_REG_IER_IN_XRUN_EN |
627 ATI_REG_IER_OUT_XRUN_EN |
628 ATI_REG_IER_SPDF_XRUN_EN |
629 ATI_REG_IER_SPDF_STATUS_EN);
630 return 0;
631}
632
633
634/*
635 * disable DMA and IRQs
636 */
637static int snd_atiixp_chip_stop(struct atiixp *chip)
638{
639 /* clear interrupt source */
640 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
641 /* disable irqs */
642 atiixp_write(chip, IER, 0);
643 return 0;
644}
645
646
647/*
648 * PCM section
649 */
650
651/*
652 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
653 * position. when SG-buffer is implemented, the offset must be calculated
654 * correctly...
655 */
656static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
657{
658 struct atiixp *chip = snd_pcm_substream_chip(substream);
659 struct snd_pcm_runtime *runtime = substream->runtime;
660 struct atiixp_dma *dma = runtime->private_data;
661 unsigned int curptr;
662 int timeout = 1000;
663
664 while (timeout--) {
665 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
666 if (curptr < dma->buf_addr)
667 continue;
668 curptr -= dma->buf_addr;
669 if (curptr >= dma->buf_bytes)
670 continue;
671 return bytes_to_frames(runtime, curptr);
672 }
673 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
674 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
675 return 0;
676}
677
678/*
679 * XRUN detected, and stop the PCM substream
680 */
681static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
682{
683 if (! dma->substream || ! dma->running)
684 return;
685 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
686 snd_pcm_stop_xrun(dma->substream);
687}
688
689/*
690 * the period ack. update the substream.
691 */
692static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
693{
694 if (! dma->substream || ! dma->running)
695 return;
696 snd_pcm_period_elapsed(dma->substream);
697}
698
699/* set BUS_BUSY interrupt bit if any DMA is running */
700/* call with spinlock held */
701static void snd_atiixp_check_bus_busy(struct atiixp *chip)
702{
703 unsigned int bus_busy;
704 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
705 ATI_REG_CMD_RECEIVE_EN |
706 ATI_REG_CMD_SPDF_OUT_EN))
707 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
708 else
709 bus_busy = 0;
710 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
711}
712
713/* common trigger callback
714 * calling the lowlevel callbacks in it
715 */
716static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
717{
718 struct atiixp *chip = snd_pcm_substream_chip(substream);
719 struct atiixp_dma *dma = substream->runtime->private_data;
720 int err = 0;
721
722 if (snd_BUG_ON(!dma->ops->enable_transfer ||
723 !dma->ops->flush_dma))
724 return -EINVAL;
725
726 spin_lock(&chip->reg_lock);
727 switch (cmd) {
728 case SNDRV_PCM_TRIGGER_START:
729 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
730 case SNDRV_PCM_TRIGGER_RESUME:
731 if (dma->running && dma->suspended &&
732 cmd == SNDRV_PCM_TRIGGER_RESUME)
733 writel(dma->saved_curptr, chip->remap_addr +
734 dma->ops->dt_cur);
735 dma->ops->enable_transfer(chip, 1);
736 dma->running = 1;
737 dma->suspended = 0;
738 break;
739 case SNDRV_PCM_TRIGGER_STOP:
740 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
741 case SNDRV_PCM_TRIGGER_SUSPEND:
742 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
743 if (dma->running && dma->suspended)
744 dma->saved_curptr = readl(chip->remap_addr +
745 dma->ops->dt_cur);
746 dma->ops->enable_transfer(chip, 0);
747 dma->running = 0;
748 break;
749 default:
750 err = -EINVAL;
751 break;
752 }
753 if (! err) {
754 snd_atiixp_check_bus_busy(chip);
755 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
756 dma->ops->flush_dma(chip);
757 snd_atiixp_check_bus_busy(chip);
758 }
759 }
760 spin_unlock(&chip->reg_lock);
761 return err;
762}
763
764
765/*
766 * lowlevel callbacks for each DMA type
767 *
768 * every callback is supposed to be called in chip->reg_lock spinlock
769 */
770
771/* flush FIFO of analog OUT DMA */
772static void atiixp_out_flush_dma(struct atiixp *chip)
773{
774 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
775}
776
777/* enable/disable analog OUT DMA */
778static void atiixp_out_enable_dma(struct atiixp *chip, int on)
779{
780 unsigned int data;
781 data = atiixp_read(chip, CMD);
782 if (on) {
783 if (data & ATI_REG_CMD_OUT_DMA_EN)
784 return;
785 atiixp_out_flush_dma(chip);
786 data |= ATI_REG_CMD_OUT_DMA_EN;
787 } else
788 data &= ~ATI_REG_CMD_OUT_DMA_EN;
789 atiixp_write(chip, CMD, data);
790}
791
792/* start/stop transfer over OUT DMA */
793static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
794{
795 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
796 on ? ATI_REG_CMD_SEND_EN : 0);
797}
798
799/* enable/disable analog IN DMA */
800static void atiixp_in_enable_dma(struct atiixp *chip, int on)
801{
802 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
803 on ? ATI_REG_CMD_IN_DMA_EN : 0);
804}
805
806/* start/stop analog IN DMA */
807static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
808{
809 if (on) {
810 unsigned int data = atiixp_read(chip, CMD);
811 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
812 data |= ATI_REG_CMD_RECEIVE_EN;
813#if 0 /* FIXME: this causes the endless loop */
814 /* wait until slot 3/4 are finished */
815 while ((atiixp_read(chip, COUNTER) &
816 ATI_REG_COUNTER_SLOT) != 5)
817 ;
818#endif
819 atiixp_write(chip, CMD, data);
820 }
821 } else
822 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
823}
824
825/* flush FIFO of analog IN DMA */
826static void atiixp_in_flush_dma(struct atiixp *chip)
827{
828 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
829}
830
831/* enable/disable SPDIF OUT DMA */
832static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
833{
834 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
835 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
836}
837
838/* start/stop SPDIF OUT DMA */
839static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
840{
841 unsigned int data;
842 data = atiixp_read(chip, CMD);
843 if (on)
844 data |= ATI_REG_CMD_SPDF_OUT_EN;
845 else
846 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
847 atiixp_write(chip, CMD, data);
848}
849
850/* flush FIFO of SPDIF OUT DMA */
851static void atiixp_spdif_flush_dma(struct atiixp *chip)
852{
853 int timeout;
854
855 /* DMA off, transfer on */
856 atiixp_spdif_enable_dma(chip, 0);
857 atiixp_spdif_enable_transfer(chip, 1);
858
859 timeout = 100;
860 do {
861 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
862 break;
863 udelay(1);
864 } while (timeout-- > 0);
865
866 atiixp_spdif_enable_transfer(chip, 0);
867}
868
869/* set up slots and formats for SPDIF OUT */
870static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
871{
872 struct atiixp *chip = snd_pcm_substream_chip(substream);
873
874 spin_lock_irq(&chip->reg_lock);
875 if (chip->spdif_over_aclink) {
876 unsigned int data;
877 /* enable slots 10/11 */
878 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
879 ATI_REG_CMD_SPDF_CONFIG_01);
880 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
881 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
882 ATI_REG_OUT_DMA_SLOT_BIT(11);
883 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
884 atiixp_write(chip, OUT_DMA_SLOT, data);
885 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
886 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
887 ATI_REG_CMD_INTERLEAVE_OUT : 0);
888 } else {
889 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
890 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
891 }
892 spin_unlock_irq(&chip->reg_lock);
893 return 0;
894}
895
896/* set up slots and formats for analog OUT */
897static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
898{
899 struct atiixp *chip = snd_pcm_substream_chip(substream);
900 unsigned int data;
901
902 spin_lock_irq(&chip->reg_lock);
903 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
904 switch (substream->runtime->channels) {
905 case 8:
906 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
907 ATI_REG_OUT_DMA_SLOT_BIT(11);
908 fallthrough;
909 case 6:
910 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
911 ATI_REG_OUT_DMA_SLOT_BIT(8);
912 fallthrough;
913 case 4:
914 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
915 ATI_REG_OUT_DMA_SLOT_BIT(9);
916 fallthrough;
917 default:
918 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
919 ATI_REG_OUT_DMA_SLOT_BIT(4);
920 break;
921 }
922
923 /* set output threshold */
924 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
925 atiixp_write(chip, OUT_DMA_SLOT, data);
926
927 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
928 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
929 ATI_REG_CMD_INTERLEAVE_OUT : 0);
930
931 /*
932 * enable 6 channel re-ordering bit if needed
933 */
934 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
935 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
936
937 spin_unlock_irq(&chip->reg_lock);
938 return 0;
939}
940
941/* set up slots and formats for analog IN */
942static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
943{
944 struct atiixp *chip = snd_pcm_substream_chip(substream);
945
946 spin_lock_irq(&chip->reg_lock);
947 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
948 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
949 ATI_REG_CMD_INTERLEAVE_IN : 0);
950 spin_unlock_irq(&chip->reg_lock);
951 return 0;
952}
953
954/*
955 * hw_params - allocate the buffer and set up buffer descriptors
956 */
957static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
958 struct snd_pcm_hw_params *hw_params)
959{
960 struct atiixp *chip = snd_pcm_substream_chip(substream);
961 struct atiixp_dma *dma = substream->runtime->private_data;
962 int err;
963
964 dma->buf_addr = substream->runtime->dma_addr;
965 dma->buf_bytes = params_buffer_bytes(hw_params);
966
967 err = atiixp_build_dma_packets(chip, dma, substream,
968 params_periods(hw_params),
969 params_period_bytes(hw_params));
970 if (err < 0)
971 return err;
972
973 if (dma->ac97_pcm_type >= 0) {
974 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
975 /* PCM is bound to AC97 codec(s)
976 * set up the AC97 codecs
977 */
978 if (dma->pcm_open_flag) {
979 snd_ac97_pcm_close(pcm);
980 dma->pcm_open_flag = 0;
981 }
982 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
983 params_channels(hw_params),
984 pcm->r[0].slots);
985 if (err >= 0)
986 dma->pcm_open_flag = 1;
987 }
988
989 return err;
990}
991
992static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
993{
994 struct atiixp *chip = snd_pcm_substream_chip(substream);
995 struct atiixp_dma *dma = substream->runtime->private_data;
996
997 if (dma->pcm_open_flag) {
998 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
999 snd_ac97_pcm_close(pcm);
1000 dma->pcm_open_flag = 0;
1001 }
1002 atiixp_clear_dma_packets(chip, dma, substream);
1003 return 0;
1004}
1005
1006
1007/*
1008 * pcm hardware definition, identical for all DMA types
1009 */
1010static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
1011{
1012 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1013 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1014 SNDRV_PCM_INFO_PAUSE |
1015 SNDRV_PCM_INFO_RESUME |
1016 SNDRV_PCM_INFO_MMAP_VALID),
1017 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1018 .rates = SNDRV_PCM_RATE_48000,
1019 .rate_min = 48000,
1020 .rate_max = 48000,
1021 .channels_min = 2,
1022 .channels_max = 2,
1023 .buffer_bytes_max = 256 * 1024,
1024 .period_bytes_min = 32,
1025 .period_bytes_max = 128 * 1024,
1026 .periods_min = 2,
1027 .periods_max = ATI_MAX_DESCRIPTORS,
1028};
1029
1030static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1031 struct atiixp_dma *dma, int pcm_type)
1032{
1033 struct atiixp *chip = snd_pcm_substream_chip(substream);
1034 struct snd_pcm_runtime *runtime = substream->runtime;
1035 int err;
1036
1037 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1038 return -EINVAL;
1039
1040 if (dma->opened)
1041 return -EBUSY;
1042 dma->substream = substream;
1043 runtime->hw = snd_atiixp_pcm_hw;
1044 dma->ac97_pcm_type = pcm_type;
1045 if (pcm_type >= 0) {
1046 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1047 snd_pcm_limit_hw_rates(runtime);
1048 } else {
1049 /* direct SPDIF */
1050 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1051 }
1052 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1053 if (err < 0)
1054 return err;
1055 runtime->private_data = dma;
1056
1057 /* enable DMA bits */
1058 spin_lock_irq(&chip->reg_lock);
1059 dma->ops->enable_dma(chip, 1);
1060 spin_unlock_irq(&chip->reg_lock);
1061 dma->opened = 1;
1062
1063 return 0;
1064}
1065
1066static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1067 struct atiixp_dma *dma)
1068{
1069 struct atiixp *chip = snd_pcm_substream_chip(substream);
1070 /* disable DMA bits */
1071 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1072 return -EINVAL;
1073 spin_lock_irq(&chip->reg_lock);
1074 dma->ops->enable_dma(chip, 0);
1075 spin_unlock_irq(&chip->reg_lock);
1076 dma->substream = NULL;
1077 dma->opened = 0;
1078 return 0;
1079}
1080
1081/*
1082 */
1083static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1084{
1085 struct atiixp *chip = snd_pcm_substream_chip(substream);
1086 int err;
1087
1088 mutex_lock(&chip->open_mutex);
1089 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1090 mutex_unlock(&chip->open_mutex);
1091 if (err < 0)
1092 return err;
1093 substream->runtime->hw.channels_max = chip->max_channels;
1094 if (chip->max_channels > 2)
1095 /* channels must be even */
1096 snd_pcm_hw_constraint_step(substream->runtime, 0,
1097 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1098 return 0;
1099}
1100
1101static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1102{
1103 struct atiixp *chip = snd_pcm_substream_chip(substream);
1104 int err;
1105 mutex_lock(&chip->open_mutex);
1106 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1107 mutex_unlock(&chip->open_mutex);
1108 return err;
1109}
1110
1111static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1112{
1113 struct atiixp *chip = snd_pcm_substream_chip(substream);
1114 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1115}
1116
1117static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1118{
1119 struct atiixp *chip = snd_pcm_substream_chip(substream);
1120 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1121}
1122
1123static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1124{
1125 struct atiixp *chip = snd_pcm_substream_chip(substream);
1126 int err;
1127 mutex_lock(&chip->open_mutex);
1128 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1129 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1130 else
1131 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1132 mutex_unlock(&chip->open_mutex);
1133 return err;
1134}
1135
1136static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1137{
1138 struct atiixp *chip = snd_pcm_substream_chip(substream);
1139 int err;
1140 mutex_lock(&chip->open_mutex);
1141 if (chip->spdif_over_aclink)
1142 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1143 else
1144 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1145 mutex_unlock(&chip->open_mutex);
1146 return err;
1147}
1148
1149/* AC97 playback */
1150static const struct snd_pcm_ops snd_atiixp_playback_ops = {
1151 .open = snd_atiixp_playback_open,
1152 .close = snd_atiixp_playback_close,
1153 .hw_params = snd_atiixp_pcm_hw_params,
1154 .hw_free = snd_atiixp_pcm_hw_free,
1155 .prepare = snd_atiixp_playback_prepare,
1156 .trigger = snd_atiixp_pcm_trigger,
1157 .pointer = snd_atiixp_pcm_pointer,
1158};
1159
1160/* AC97 capture */
1161static const struct snd_pcm_ops snd_atiixp_capture_ops = {
1162 .open = snd_atiixp_capture_open,
1163 .close = snd_atiixp_capture_close,
1164 .hw_params = snd_atiixp_pcm_hw_params,
1165 .hw_free = snd_atiixp_pcm_hw_free,
1166 .prepare = snd_atiixp_capture_prepare,
1167 .trigger = snd_atiixp_pcm_trigger,
1168 .pointer = snd_atiixp_pcm_pointer,
1169};
1170
1171/* SPDIF playback */
1172static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
1173 .open = snd_atiixp_spdif_open,
1174 .close = snd_atiixp_spdif_close,
1175 .hw_params = snd_atiixp_pcm_hw_params,
1176 .hw_free = snd_atiixp_pcm_hw_free,
1177 .prepare = snd_atiixp_spdif_prepare,
1178 .trigger = snd_atiixp_pcm_trigger,
1179 .pointer = snd_atiixp_pcm_pointer,
1180};
1181
1182static const struct ac97_pcm atiixp_pcm_defs[] = {
1183 /* front PCM */
1184 {
1185 .exclusive = 1,
1186 .r = { {
1187 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1188 (1 << AC97_SLOT_PCM_RIGHT) |
1189 (1 << AC97_SLOT_PCM_CENTER) |
1190 (1 << AC97_SLOT_PCM_SLEFT) |
1191 (1 << AC97_SLOT_PCM_SRIGHT) |
1192 (1 << AC97_SLOT_LFE)
1193 }
1194 }
1195 },
1196 /* PCM IN #1 */
1197 {
1198 .stream = 1,
1199 .exclusive = 1,
1200 .r = { {
1201 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1202 (1 << AC97_SLOT_PCM_RIGHT)
1203 }
1204 }
1205 },
1206 /* S/PDIF OUT (optional) */
1207 {
1208 .exclusive = 1,
1209 .spdif = 1,
1210 .r = { {
1211 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1212 (1 << AC97_SLOT_SPDIF_RIGHT2)
1213 }
1214 }
1215 },
1216};
1217
1218static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1219 .type = ATI_DMA_PLAYBACK,
1220 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1221 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1222 .enable_dma = atiixp_out_enable_dma,
1223 .enable_transfer = atiixp_out_enable_transfer,
1224 .flush_dma = atiixp_out_flush_dma,
1225};
1226
1227static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1228 .type = ATI_DMA_CAPTURE,
1229 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1230 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1231 .enable_dma = atiixp_in_enable_dma,
1232 .enable_transfer = atiixp_in_enable_transfer,
1233 .flush_dma = atiixp_in_flush_dma,
1234};
1235
1236static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1237 .type = ATI_DMA_SPDIF,
1238 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1239 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1240 .enable_dma = atiixp_spdif_enable_dma,
1241 .enable_transfer = atiixp_spdif_enable_transfer,
1242 .flush_dma = atiixp_spdif_flush_dma,
1243};
1244
1245
1246static int snd_atiixp_pcm_new(struct atiixp *chip)
1247{
1248 struct snd_pcm *pcm;
1249 struct snd_pcm_chmap *chmap;
1250 struct snd_ac97_bus *pbus = chip->ac97_bus;
1251 int err, i, num_pcms;
1252
1253 /* initialize constants */
1254 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1255 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1256 if (! chip->spdif_over_aclink)
1257 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1258
1259 /* assign AC97 pcm */
1260 if (chip->spdif_over_aclink)
1261 num_pcms = 3;
1262 else
1263 num_pcms = 2;
1264 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1265 if (err < 0)
1266 return err;
1267 for (i = 0; i < num_pcms; i++)
1268 chip->pcms[i] = &pbus->pcms[i];
1269
1270 chip->max_channels = 2;
1271 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1272 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1273 chip->max_channels = 6;
1274 else
1275 chip->max_channels = 4;
1276 }
1277
1278 /* PCM #0: analog I/O */
1279 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1280 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1281 if (err < 0)
1282 return err;
1283 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1284 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1285 pcm->private_data = chip;
1286 strcpy(pcm->name, "ATI IXP AC97");
1287 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1288
1289 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1290 &chip->pci->dev, 64*1024, 128*1024);
1291
1292 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1293 snd_pcm_alt_chmaps, chip->max_channels, 0,
1294 &chmap);
1295 if (err < 0)
1296 return err;
1297 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1298 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1299
1300 /* no SPDIF support on codec? */
1301 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1302 return 0;
1303
1304 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1305 if (chip->pcms[ATI_PCM_SPDIF])
1306 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1307
1308 /* PCM #1: spdif playback */
1309 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1310 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1311 if (err < 0)
1312 return err;
1313 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1314 pcm->private_data = chip;
1315 if (chip->spdif_over_aclink)
1316 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1317 else
1318 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1319 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1320
1321 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1322 &chip->pci->dev, 64*1024, 128*1024);
1323
1324 /* pre-select AC97 SPDIF slots 10/11 */
1325 for (i = 0; i < NUM_ATI_CODECS; i++) {
1326 if (chip->ac97[i])
1327 snd_ac97_update_bits(chip->ac97[i],
1328 AC97_EXTENDED_STATUS,
1329 0x03 << 4, 0x03 << 4);
1330 }
1331
1332 return 0;
1333}
1334
1335
1336
1337/*
1338 * interrupt handler
1339 */
1340static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1341{
1342 struct atiixp *chip = dev_id;
1343 unsigned int status;
1344
1345 status = atiixp_read(chip, ISR);
1346
1347 if (! status)
1348 return IRQ_NONE;
1349
1350 /* process audio DMA */
1351 if (status & ATI_REG_ISR_OUT_XRUN)
1352 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1353 else if (status & ATI_REG_ISR_OUT_STATUS)
1354 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1355 if (status & ATI_REG_ISR_IN_XRUN)
1356 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1357 else if (status & ATI_REG_ISR_IN_STATUS)
1358 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1359 if (! chip->spdif_over_aclink) {
1360 if (status & ATI_REG_ISR_SPDF_XRUN)
1361 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1362 else if (status & ATI_REG_ISR_SPDF_STATUS)
1363 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1364 }
1365
1366 /* for codec detection */
1367 if (status & CODEC_CHECK_BITS) {
1368 unsigned int detected;
1369 detected = status & CODEC_CHECK_BITS;
1370 spin_lock(&chip->reg_lock);
1371 chip->codec_not_ready_bits |= detected;
1372 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1373 spin_unlock(&chip->reg_lock);
1374 }
1375
1376 /* ack */
1377 atiixp_write(chip, ISR, status);
1378
1379 return IRQ_HANDLED;
1380}
1381
1382
1383/*
1384 * ac97 mixer section
1385 */
1386
1387static const struct ac97_quirk ac97_quirks[] = {
1388 {
1389 .subvendor = 0x103c,
1390 .subdevice = 0x006b,
1391 .name = "HP Pavilion ZV5030US",
1392 .type = AC97_TUNE_MUTE_LED
1393 },
1394 {
1395 .subvendor = 0x103c,
1396 .subdevice = 0x308b,
1397 .name = "HP nx6125",
1398 .type = AC97_TUNE_MUTE_LED
1399 },
1400 {
1401 .subvendor = 0x103c,
1402 .subdevice = 0x3091,
1403 .name = "unknown HP",
1404 .type = AC97_TUNE_MUTE_LED
1405 },
1406 {0} /* terminator */
1407};
1408
1409static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1410 const char *quirk_override)
1411{
1412 struct snd_ac97_bus *pbus;
1413 struct snd_ac97_template ac97;
1414 int i, err;
1415 int codec_count;
1416 static const struct snd_ac97_bus_ops ops = {
1417 .write = snd_atiixp_ac97_write,
1418 .read = snd_atiixp_ac97_read,
1419 };
1420 static const unsigned int codec_skip[NUM_ATI_CODECS] = {
1421 ATI_REG_ISR_CODEC0_NOT_READY,
1422 ATI_REG_ISR_CODEC1_NOT_READY,
1423 ATI_REG_ISR_CODEC2_NOT_READY,
1424 };
1425
1426 if (snd_atiixp_codec_detect(chip) < 0)
1427 return -ENXIO;
1428
1429 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
1430 if (err < 0)
1431 return err;
1432 pbus->clock = clock;
1433 chip->ac97_bus = pbus;
1434
1435 codec_count = 0;
1436 for (i = 0; i < NUM_ATI_CODECS; i++) {
1437 if (chip->codec_not_ready_bits & codec_skip[i])
1438 continue;
1439 memset(&ac97, 0, sizeof(ac97));
1440 ac97.private_data = chip;
1441 ac97.pci = chip->pci;
1442 ac97.num = i;
1443 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1444 if (! chip->spdif_over_aclink)
1445 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1446 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
1447 if (err < 0) {
1448 chip->ac97[i] = NULL; /* to be sure */
1449 dev_dbg(chip->card->dev,
1450 "codec %d not available for audio\n", i);
1451 continue;
1452 }
1453 codec_count++;
1454 }
1455
1456 if (! codec_count) {
1457 dev_err(chip->card->dev, "no codec available\n");
1458 return -ENODEV;
1459 }
1460
1461 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1462
1463 return 0;
1464}
1465
1466
1467#ifdef CONFIG_PM_SLEEP
1468/*
1469 * power management
1470 */
1471static int snd_atiixp_suspend(struct device *dev)
1472{
1473 struct snd_card *card = dev_get_drvdata(dev);
1474 struct atiixp *chip = card->private_data;
1475 int i;
1476
1477 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1478 for (i = 0; i < NUM_ATI_CODECS; i++)
1479 snd_ac97_suspend(chip->ac97[i]);
1480 snd_atiixp_aclink_down(chip);
1481 snd_atiixp_chip_stop(chip);
1482 return 0;
1483}
1484
1485static int snd_atiixp_resume(struct device *dev)
1486{
1487 struct snd_card *card = dev_get_drvdata(dev);
1488 struct atiixp *chip = card->private_data;
1489 int i;
1490
1491 snd_atiixp_aclink_reset(chip);
1492 snd_atiixp_chip_start(chip);
1493
1494 for (i = 0; i < NUM_ATI_CODECS; i++)
1495 snd_ac97_resume(chip->ac97[i]);
1496
1497 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1498 if (chip->pcmdevs[i]) {
1499 struct atiixp_dma *dma = &chip->dmas[i];
1500 if (dma->substream && dma->suspended) {
1501 dma->ops->enable_dma(chip, 1);
1502 dma->substream->ops->prepare(dma->substream);
1503 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1504 chip->remap_addr + dma->ops->llp_offset);
1505 }
1506 }
1507
1508 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1509 return 0;
1510}
1511
1512static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1513#define SND_ATIIXP_PM_OPS &snd_atiixp_pm
1514#else
1515#define SND_ATIIXP_PM_OPS NULL
1516#endif /* CONFIG_PM_SLEEP */
1517
1518
1519/*
1520 * proc interface for register dump
1521 */
1522
1523static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1524 struct snd_info_buffer *buffer)
1525{
1526 struct atiixp *chip = entry->private_data;
1527 int i;
1528
1529 for (i = 0; i < 256; i += 4)
1530 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1531}
1532
1533static void snd_atiixp_proc_init(struct atiixp *chip)
1534{
1535 snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
1536}
1537
1538
1539/*
1540 * destructor
1541 */
1542
1543static int snd_atiixp_free(struct atiixp *chip)
1544{
1545 if (chip->irq < 0)
1546 goto __hw_end;
1547 snd_atiixp_chip_stop(chip);
1548
1549 __hw_end:
1550 if (chip->irq >= 0)
1551 free_irq(chip->irq, chip);
1552 iounmap(chip->remap_addr);
1553 pci_release_regions(chip->pci);
1554 pci_disable_device(chip->pci);
1555 kfree(chip);
1556 return 0;
1557}
1558
1559static int snd_atiixp_dev_free(struct snd_device *device)
1560{
1561 struct atiixp *chip = device->device_data;
1562 return snd_atiixp_free(chip);
1563}
1564
1565/*
1566 * constructor for chip instance
1567 */
1568static int snd_atiixp_create(struct snd_card *card,
1569 struct pci_dev *pci,
1570 struct atiixp **r_chip)
1571{
1572 static const struct snd_device_ops ops = {
1573 .dev_free = snd_atiixp_dev_free,
1574 };
1575 struct atiixp *chip;
1576 int err;
1577
1578 err = pci_enable_device(pci);
1579 if (err < 0)
1580 return err;
1581
1582 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1583 if (chip == NULL) {
1584 pci_disable_device(pci);
1585 return -ENOMEM;
1586 }
1587
1588 spin_lock_init(&chip->reg_lock);
1589 mutex_init(&chip->open_mutex);
1590 chip->card = card;
1591 chip->pci = pci;
1592 chip->irq = -1;
1593 err = pci_request_regions(pci, "ATI IXP AC97");
1594 if (err < 0) {
1595 pci_disable_device(pci);
1596 kfree(chip);
1597 return err;
1598 }
1599 chip->addr = pci_resource_start(pci, 0);
1600 chip->remap_addr = pci_ioremap_bar(pci, 0);
1601 if (chip->remap_addr == NULL) {
1602 dev_err(card->dev, "AC'97 space ioremap problem\n");
1603 snd_atiixp_free(chip);
1604 return -EIO;
1605 }
1606
1607 if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED,
1608 KBUILD_MODNAME, chip)) {
1609 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1610 snd_atiixp_free(chip);
1611 return -EBUSY;
1612 }
1613 chip->irq = pci->irq;
1614 card->sync_irq = chip->irq;
1615 pci_set_master(pci);
1616
1617 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1618 if (err < 0) {
1619 snd_atiixp_free(chip);
1620 return err;
1621 }
1622
1623 *r_chip = chip;
1624 return 0;
1625}
1626
1627
1628static int snd_atiixp_probe(struct pci_dev *pci,
1629 const struct pci_device_id *pci_id)
1630{
1631 struct snd_card *card;
1632 struct atiixp *chip;
1633 int err;
1634
1635 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
1636 if (err < 0)
1637 return err;
1638
1639 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1640 strcpy(card->shortname, "ATI IXP");
1641 err = snd_atiixp_create(card, pci, &chip);
1642 if (err < 0)
1643 goto __error;
1644 card->private_data = chip;
1645
1646 err = snd_atiixp_aclink_reset(chip);
1647 if (err < 0)
1648 goto __error;
1649
1650 chip->spdif_over_aclink = spdif_aclink;
1651
1652 err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk);
1653 if (err < 0)
1654 goto __error;
1655
1656 err = snd_atiixp_pcm_new(chip);
1657 if (err < 0)
1658 goto __error;
1659
1660 snd_atiixp_proc_init(chip);
1661
1662 snd_atiixp_chip_start(chip);
1663
1664 snprintf(card->longname, sizeof(card->longname),
1665 "%s rev %x with %s at %#lx, irq %i", card->shortname,
1666#ifndef TARGET_OS2
1667 pci->revision,
1668#else
1669 snd_pci_revision(pci),
1670#endif
1671 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1672 chip->addr, chip->irq);
1673
1674 err = snd_card_register(card);
1675 if (err < 0)
1676 goto __error;
1677
1678 pci_set_drvdata(pci, card);
1679 return 0;
1680
1681 __error:
1682 snd_card_free(card);
1683 return err;
1684}
1685
1686static void snd_atiixp_remove(struct pci_dev *pci)
1687{
1688 snd_card_free(pci_get_drvdata(pci));
1689}
1690
1691static struct pci_driver atiixp_driver = {
1692 .name = KBUILD_MODNAME,
1693 .id_table = snd_atiixp_ids,
1694 .probe = snd_atiixp_probe,
1695 .remove = snd_atiixp_remove,
1696 .driver = {
1697 .pm = SND_ATIIXP_PM_OPS,
1698 },
1699};
1700
1701module_pci_driver(atiixp_driver);
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