Ignore:
Timestamp:
Sep 25, 2003, 9:27:01 PM (22 years ago)
Author:
zap
Message:

.

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1 edited

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  • trunk/src/binutils/gas/doc/as.1

    • Property cvs2svn:cvs-rev changed from 1.1.1.2 to 1.2
    r728 r729  
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    62 .\"
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    98 .    ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
    99 .    ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
    100 .\}
    101 .    \" troff and (daisy-wheel) nroff accents
    102 .ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
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    126 .\}
    127 .rm #[ #] #H #V #F C
    128 .\" ========================================================================
    129 .\"
    130 .IX Title "AS 1"
    131 .TH AS 1 "2003-06-12" "binutils-2.14" "GNU Development Tools"
    132 .SH "NAME"
    133 AS \- the portable GNU assembler.
    134 .SH "SYNOPSIS"
    135 .IX Header "SYNOPSIS"
    136 as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR]
    137  [\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR]
    138  [\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR]
    139  [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR]
    140  [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR]
    141  [\fB\-\-keep\-locals\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-statistics\fR] [\fB\-v\fR]
    142  [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR]
    143  [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB\-\-target\-help\fR] [\fItarget-options\fR]
    144  [\fB\-\-\fR|\fIfiles\fR ...]
    145 .PP
    146 \&\fITarget Alpha options:\fR
    147    [\fB\-m\fR\fIcpu\fR]
    148    [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
    149    [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
    150    [\fB\-F\fR] [\fB\-32addr\fR]
    151 .PP
    152 \&\fITarget \s-1ARC\s0 options:\fR
    153    [\fB\-marc[5|6|7|8]\fR]
    154    [\fB\-EB\fR|\fB\-EL\fR]
    155 .PP
    156 \&\fITarget \s-1ARM\s0 options:\fR
    157    [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
    158    [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
    159    [\fB\-mfpu\fR=\fIfloating-point-fromat\fR]
    160    [\fB\-mthumb\fR]
    161    [\fB\-EB\fR|\fB\-EL\fR]
    162    [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
    163     \fB\-mapcs\-reentrant\fR]
    164    [\fB\-mthumb\-interwork\fR] [\fB\-moabi\fR] [\fB\-k\fR]
    165 .PP
    166 \&\fITarget \s-1CRIS\s0 options:\fR
    167    [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
    168    [\fB\-\-pic\fR] [\fB\-N\fR]
    169    [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
    170 .PP
    171 \&\fITarget D10V options:\fR
    172    [\fB\-O\fR]
    173 .PP
    174 \&\fITarget D30V options:\fR
    175    [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
    176 .PP
    177 \&\fITarget i386 options:\fR
    178    [\fB\-\-32\fR|\fB\-\-64\fR]
    179 .PP
    180 \&\fITarget i960 options:\fR
    181    [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
    182     \fB\-AKC\fR|\fB\-AMC\fR]
    183    [\fB\-b\fR] [\fB\-no\-relax\fR]
    184 .PP
    185 \&\fITarget \s-1IP2K\s0 options:\fR
    186    [\fB\-mip2022\fR|\fB\-mip2022ext\fR]
    187 .PP
    188 \&\fITarget M32R options:\fR
    189    [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
    190    \fB\-\-W[n]p\fR]
    191 .PP
    192 \&\fITarget M680X0 options:\fR
    193    [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
    194 .PP
    195 \&\fITarget M68HC11 options:\fR
    196    [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR]
    197    [\fB\-mshort\fR|\fB\-mlong\fR]
    198    [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
    199    [\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR]
    200    [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
    201    [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
    202 .PP
    203 \&\fITarget \s-1MCORE\s0 options:\fR
    204    [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
    205    [\fB\-mcpu=[210|340]\fR]
    206 .PP
    207 \&\fITarget \s-1MIPS\s0 options:\fR
    208    [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-n\fR] [\fB\-O\fR[\fIoptimization level\fR]]
    209    [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
    210    [\fB\-non_shared\fR] [\fB\-xgot\fR] [\fB\-\-membedded\-pic\fR]
    211    [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
    212    [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
    213    [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
    214    [\fB\-mips64\fR]
    215    [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
    216    [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
    217    [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
    218    [\fB\-mips16\fR] [\fB\-no\-mips16\fR]
    219    [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
    220    [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
    221    [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
    222 .PP
    223 \&\fITarget \s-1MMIX\s0 options:\fR
    224    [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
    225    [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
    226    [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
    227    [\fB\-\-linker\-allocated\-gregs\fR]
    228 .PP
    229 \&\fITarget \s-1PDP11\s0 options:\fR
    230    [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
    231    [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
    232    [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR] 
    233 .PP
    234 \&\fITarget picoJava options:\fR
    235    [\fB\-mb\fR|\fB\-me\fR]
    236 .PP
    237 \&\fITarget PowerPC options:\fR
    238    [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
    239     \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
    240     \fB\-mbooke32\fR|\fB\-mbooke64\fR]
    241    [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
    242    [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
    243    [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
    244    [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
    245    [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
    246 .PP
    247 \&\fITarget \s-1SPARC\s0 options:\fR
    248    [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
    249     \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
    250    [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
    251    [\fB\-32\fR|\fB\-64\fR]
    252 .PP
    253 \&\fITarget \s-1TIC54X\s0 options:\fR
    254  [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR]
    255  [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
    256 .PP
    257 \&\fITarget Xtensa options:\fR
    258  [\fB\-\-[no\-]density\fR] [\fB\-\-[no\-]relax\fR] [\fB\-\-[no\-]generics\fR]
    259  [\fB\-\-[no\-]text\-section\-literals\fR]
    260  [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
    261 .SH "DESCRIPTION"
    262 .IX Header "DESCRIPTION"
    263 \&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
    264 If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
    265 should find a fairly similar environment when you use it on another
    266 architecture.  Each version has much in common with the others,
    267 including object file formats, most assembler directives (often called
    268 \&\fIpseudo-ops\fR) and assembler syntax.
    269 .PP
    270 \&\fBas\fR is primarily intended to assemble the output of the
    271 \&\s-1GNU\s0 C compiler  for use by the linker
    272 \&.  Nevertheless, we've tried to make \fBas\fR
    273 assemble correctly everything that other assemblers for the same
    274 machine would assemble.
    275 Any exceptions are documented explicitly.
    276 This doesn't mean \fBas\fR always uses the same syntax as another
    277 assembler for the same architecture; for example, we know of several
    278 incompatible versions of 680x0 assembly language syntax.
    279 .PP
    280 Each time you run \fBas\fR it assembles exactly one source
    281 program.  The source program is made up of one or more files.
    282 (The standard input is also a file.)
    283 .PP
    284 You give \fBas\fR a command line that has zero or more input file
    285 names.  The input files are read (from left file name to right).  A
    286 command line argument (in any position) that has no special meaning
    287 is taken to be an input file name.
    288 .PP
    289 If you give \fBas\fR no file names it attempts to read one input file
    290 from the \fBas\fR standard input, which is normally your terminal.  You
    291 may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
    292 to assemble.
    293 .PP
    294 Use \fB\-\-\fR if you need to explicitly name the standard input file
    295 in your command line.
    296 .PP
    297 If the source is empty, \fBas\fR produces a small, empty object
    298 file.
    299 .PP
    300 \&\fBas\fR may write warnings and error messages to the standard error
    301 file (usually your terminal).  This should not happen when  a compiler
    302 runs \fBas\fR automatically.  Warnings report an assumption made so
    303 that \fBas\fR could keep assembling a flawed program; errors report a
    304 grave problem that stops the assembly.
    305 .PP
    306 If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler,
    307 you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
    308 The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
    309 by commas.  For example:
    310 .PP
    311 .Vb 1
    312 \&        gcc -c -g -O -Wa,-alh,-L file.c
    313 .Ve
    314 .PP
    315 This passes two options to the assembler: \fB\-alh\fR (emit a listing to
    316 standard output with high-level and assembly source) and \fB\-L\fR (retain
    317 local symbols in the symbol table).
    318 .PP
    319 Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
    320 command-line options are automatically passed to the assembler by the compiler.
    321 (You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
    322 precisely what options it passes to each compilation pass, including the
    323 assembler.)
    324 .SH "OPTIONS"
    325 .IX Header "OPTIONS"
    326 .IP "\fB\-a[cdhlmns]\fR" 4
    327 .IX Item "-a[cdhlmns]"
    328 Turn on listings, in any of a variety of ways:
    329 .RS 4
    330 .IP "\fB\-ac\fR" 4
    331 .IX Item "-ac"
    332 omit false conditionals
    333 .IP "\fB\-ad\fR" 4
    334 .IX Item "-ad"
    335 omit debugging directives
    336 .IP "\fB\-ah\fR" 4
    337 .IX Item "-ah"
    338 include high-level source
    339 .IP "\fB\-al\fR" 4
    340 .IX Item "-al"
    341 include assembly
    342 .IP "\fB\-am\fR" 4
    343 .IX Item "-am"
    344 include macro expansions
    345 .IP "\fB\-an\fR" 4
    346 .IX Item "-an"
    347 omit forms processing
    348 .IP "\fB\-as\fR" 4
    349 .IX Item "-as"
    350 include symbols
    351 .IP "\fB=file\fR" 4
    352 .IX Item "=file"
    353 set the name of the listing file
    354 .RE
    355 .RS 4
    356 .Sp
    357 You may combine these options; for example, use \fB\-aln\fR for assembly
    358 listing without forms processing.  The \fB=file\fR option, if used, must be
    359 the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
    360 .RE
    361 .IP "\fB\-D\fR" 4
    362 .IX Item "-D"
    363 Ignored.  This option is accepted for script compatibility with calls to
    364 other assemblers.
    365 .IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
    366 .IX Item "--defsym sym=value"
    367 Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
    368 \&\fIvalue\fR must be an integer constant.  As in C, a leading \fB0x\fR
    369 indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
    370 .IP "\fB\-f\fR" 4
    371 .IX Item "-f"
    372 ``fast''\-\-\-skip whitespace and comment preprocessing (assume source is
    373 compiler output).
    374 .IP "\fB\-\-gstabs\fR" 4
    375 .IX Item "--gstabs"
    376 Generate stabs debugging information for each assembler line.  This
    377 may help debugging assembler code, if the debugger can handle it.
    378 .IP "\fB\-\-gdwarf2\fR" 4
    379 .IX Item "--gdwarf2"
    380 Generate \s-1DWARF2\s0 debugging information for each assembler line.  This
    381 may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this
    382 option is only supported by some targets, not all of them.
    383 .IP "\fB\-\-help\fR" 4
    384 .IX Item "--help"
    385 Print a summary of the command line options and exit.
    386 .IP "\fB\-\-target\-help\fR" 4
    387 .IX Item "--target-help"
    388 Print a summary of all target specific options and exit.
    389 .IP "\fB\-I\fR \fIdir\fR" 4
    390 .IX Item "-I dir"
    391 Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
    392 .IP "\fB\-J\fR" 4
    393 .IX Item "-J"
    394 Don't warn about signed overflow.
    395 .IP "\fB\-K\fR" 4
    396 .IX Item "-K"
    397 This option is accepted but has no effect on the \s-1TARGET\s0 family.
    398 .IP "\fB\-L\fR" 4
    399 .IX Item "-L"
    400 .PD 0
    401 .IP "\fB\-\-keep\-locals\fR" 4
    402 .IX Item "--keep-locals"
    403 .PD
    404 Keep (in the symbol table) local symbols.  On traditional a.out systems
    405 these start with \fBL\fR, but different systems have different local
    406 label prefixes.
    407 .IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
    408 .IX Item "--listing-lhs-width=number"
    409 Set the maximum width, in words, of the output data column for an assembler
    410 listing to \fInumber\fR.
    411 .IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
    412 .IX Item "--listing-lhs-width2=number"
    413 Set the maximum width, in words, of the output data column for continuation
    414 lines in an assembler listing to \fInumber\fR.
    415 .IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
    416 .IX Item "--listing-rhs-width=number"
    417 Set the maximum width of an input source line, as displayed in a listing, to
    418 \&\fInumber\fR bytes.
    419 .IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
    420 .IX Item "--listing-cont-lines=number"
    421 Set the maximum number of lines printed in a listing for a single line of input
    422 to \fInumber\fR + 1.
    423 .IP "\fB\-o\fR \fIobjfile\fR" 4
    424 .IX Item "-o objfile"
    425 Name the object-file output from \fBas\fR \fIobjfile\fR.
    426 .IP "\fB\-R\fR" 4
    427 .IX Item "-R"
    428 Fold the data section into the text section.
    429 .IP "\fB\-\-statistics\fR" 4
    430 .IX Item "--statistics"
    431 Print the maximum space (in bytes) and total time (in seconds) used by
    432 assembly.
    433 .IP "\fB\-\-strip\-local\-absolute\fR" 4
    434 .IX Item "--strip-local-absolute"
    435 Remove local absolute symbols from the outgoing symbol table.
    436 .IP "\fB\-v\fR" 4
    437 .IX Item "-v"
    438 .PD 0
    439 .IP "\fB\-version\fR" 4
    440 .IX Item "-version"
    441 .PD
    442 Print the \fBas\fR version.
    443 .IP "\fB\-\-version\fR" 4
    444 .IX Item "--version"
    445 Print the \fBas\fR version and exit.
    446 .IP "\fB\-W\fR" 4
    447 .IX Item "-W"
    448 .PD 0
    449 .IP "\fB\-\-no\-warn\fR" 4
    450 .IX Item "--no-warn"
    451 .PD
    452 Suppress warning messages.
    453 .IP "\fB\-\-fatal\-warnings\fR" 4
    454 .IX Item "--fatal-warnings"
    455 Treat warnings as errors.
    456 .IP "\fB\-\-warn\fR" 4
    457 .IX Item "--warn"
    458 Don't suppress warning messages or treat them as errors.
    459 .IP "\fB\-w\fR" 4
    460 .IX Item "-w"
    461 Ignored.
    462 .IP "\fB\-x\fR" 4
    463 .IX Item "-x"
    464 Ignored.
    465 .IP "\fB\-Z\fR" 4
    466 .IX Item "-Z"
    467 Generate an object file even after errors.
    468 .IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
    469 .IX Item "-- | files ..."
    470 Standard input, or source files to assemble.
    471 .PP
    472 The following options are available when as is configured for
    473 an \s-1ARC\s0 processor.
    474 .IP "\fB\-marc[5|6|7|8]\fR" 4
    475 .IX Item "-marc[5|6|7|8]"
    476 This option selects the core processor variant.
    477 .IP "\fB\-EB | \-EL\fR" 4
    478 .IX Item "-EB | -EL"
    479 Select either big-endian (\-EB) or little-endian (\-EL) output.
    480 .PP
    481 The following options are available when as is configured for the \s-1ARM\s0
    482 processor family.
    483 .IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
    484 .IX Item "-mcpu=processor[+extension...]"
    485 Specify which \s-1ARM\s0 processor variant is the target.
    486 .IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
    487 .IX Item "-march=architecture[+extension...]"
    488 Specify which \s-1ARM\s0 architecture variant is used by the target.
    489 .IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
    490 .IX Item "-mfpu=floating-point-format"
    491 Select which Floating Point architecture is the target.
    492 .IP "\fB\-mthumb\fR" 4
    493 .IX Item "-mthumb"
    494 Enable Thumb only instruction decoding.
    495 .IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\fR" 4
    496 .IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
    497 Select which procedure calling convention is in use.
    498 .IP "\fB\-EB | \-EL\fR" 4
    499 .IX Item "-EB | -EL"
    500 Select either big-endian (\-EB) or little-endian (\-EL) output.
    501 .IP "\fB\-mthumb\-interwork\fR" 4
    502 .IX Item "-mthumb-interwork"
    503 Specify that the code has been generated with interworking between Thumb and
    504 \&\s-1ARM\s0 code in mind.
    505 .IP "\fB\-k\fR" 4
    506 .IX Item "-k"
    507 Specify that \s-1PIC\s0 code has been generated.
    508 .PP
    509 See the info pages for documentation of the CRIS-specific options.
    510 .PP
    511 The following options are available when as is configured for
    512 a D10V processor.
    513 .IP "\fB\-O\fR" 4
    514 .IX Item "-O"
    515 Optimize output by parallelizing instructions.
    516 .PP
    517 The following options are available when as is configured for a D30V
    518 processor.
    519 .IP "\fB\-O\fR" 4
    520 .IX Item "-O"
    521 Optimize output by parallelizing instructions.
    522 .IP "\fB\-n\fR" 4
    523 .IX Item "-n"
    524 Warn when nops are generated.
    525 .IP "\fB\-N\fR" 4
    526 .IX Item "-N"
    527 Warn when a nop after a 32\-bit multiply instruction is generated.
    528 .PP
    529 The following options are available when as is configured for the
    530 Intel 80960 processor.
    531 .IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
    532 .IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
    533 Specify which variant of the 960 architecture is the target.
    534 .IP "\fB\-b\fR" 4
    535 .IX Item "-b"
    536 Add code to collect statistics about branches taken.
    537 .IP "\fB\-no\-relax\fR" 4
    538 .IX Item "-no-relax"
    539 Do not alter compare-and-branch instructions for long displacements;
    540 error if necessary.
    541 .PP
    542 The following options are available when as is configured for the
    543 Ubicom \s-1IP2K\s0 series.
    544 .IP "\fB\-mip2022ext\fR" 4
    545 .IX Item "-mip2022ext"
    546 Specifies that the extended \s-1IP2022\s0 instructions are allowed.
    547 .IP "\fB\-mip2022\fR" 4
    548 .IX Item "-mip2022"
    549 Restores the default behaviour, which restricts the permitted instructions to
    550 just the basic \s-1IP2022\s0 ones.
    551 .PP
    552 The following options are available when as is configured for the
    553 Renesas M32R (formerly Mitsubishi M32R) series.
    554 .IP "\fB\-\-m32rx\fR" 4
    555 .IX Item "--m32rx"
    556 Specify which processor in the M32R family is the target.  The default
    557 is normally the M32R, but this option changes it to the M32RX.
    558 .IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
    559 .IX Item "--warn-explicit-parallel-conflicts or --Wp"
    560 Produce warning messages when questionable parallel constructs are
    561 encountered.
    562 .IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
    563 .IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
    564 Do not produce warning messages when questionable parallel constructs are
    565 encountered.
    566 .PP
    567 The following options are available when as is configured for the
    568 Motorola 68000 series.
    569 .IP "\fB\-l\fR" 4
    570 .IX Item "-l"
    571 Shorten references to undefined symbols, to one word instead of two.
    572 .IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
    573 .IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
    574 .PD 0
    575 .IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
    576 .IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
    577 .IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
    578 .IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
    579 .PD
    580 Specify what processor in the 68000 family is the target.  The default
    581 is normally the 68020, but this can be changed at configuration time.
    582 .IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
    583 .IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
    584 The target machine does (or does not) have a floating-point coprocessor.
    585 The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
    586 the basic 68000 is not compatible with the 68881, a combination of the
    587 two can be specified, since it's possible to do emulation of the
    588 coprocessor instructions with the main processor.
    589 .IP "\fB\-m68851 | \-mno\-68851\fR" 4
    590 .IX Item "-m68851 | -mno-68851"
    591 The target machine does (or does not) have a memory-management
    592 unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.
    593 .PP
    594 For details about the \s-1PDP\-11\s0 machine dependent features options,
    595 see \f(CW@ref\fR{PDP\-11\-Options}.
    596 .IP "\fB\-mpic | \-mno\-pic\fR" 4
    597 .IX Item "-mpic | -mno-pic"
    598 Generate position-independent (or position\-dependent) code.  The
    599 default is \fB\-mpic\fR.
    600 .IP "\fB\-mall\fR" 4
    601 .IX Item "-mall"
    602 .PD 0
    603 .IP "\fB\-mall\-extensions\fR" 4
    604 .IX Item "-mall-extensions"
    605 .PD
    606 Enable all instruction set extensions.  This is the default.
    607 .IP "\fB\-mno\-extensions\fR" 4
    608 .IX Item "-mno-extensions"
    609 Disable all instruction set extensions.
    610 .IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
    611 .IX Item "-mextension | -mno-extension"
    612 Enable (or disable) a particular instruction set extension.
    613 .IP "\fB\-m\fR\fIcpu\fR" 4
    614 .IX Item "-mcpu"
    615 Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
    616 disable all other extensions.
    617 .IP "\fB\-m\fR\fImachine\fR" 4
    618 .IX Item "-mmachine"
    619 Enable the instruction set extensions supported by a particular machine
    620 model, and disable all other extensions.
    621 .PP
    622 The following options are available when as is configured for
    623 a picoJava processor.
    624 .IP "\fB\-mb\fR" 4
    625 .IX Item "-mb"
    626 Generate ``big endian'' format output.
    627 .IP "\fB\-ml\fR" 4
    628 .IX Item "-ml"
    629 Generate ``little endian'' format output.
    630 .PP
    631 The following options are available when as is configured for the
    632 Motorola 68HC11 or 68HC12 series.
    633 .IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4
    634 .IX Item "-m68hc11 | -m68hc12 | -m68hcs12"
    635 Specify what processor is the target.  The default is
    636 defined by the configuration option when building the assembler.
    637 .IP "\fB\-mshort\fR" 4
    638 .IX Item "-mshort"
    639 Specify to use the 16\-bit integer \s-1ABI\s0.
    640 .IP "\fB\-mlong\fR" 4
    641 .IX Item "-mlong"
    642 Specify to use the 32\-bit integer \s-1ABI\s0. 
    643 .IP "\fB\-mshort\-double\fR" 4
    644 .IX Item "-mshort-double"
    645 Specify to use the 32\-bit double \s-1ABI\s0. 
    646 .IP "\fB\-mlong\-double\fR" 4
    647 .IX Item "-mlong-double"
    648 Specify to use the 64\-bit double \s-1ABI\s0. 
    649 .IP "\fB\-\-force\-long\-branchs\fR" 4
    650 .IX Item "--force-long-branchs"
    651 Relative branches are turned into absolute ones. This concerns
    652 conditional branches, unconditional branches and branches to a
    653 sub routine.
    654 .IP "\fB\-S | \-\-short\-branchs\fR" 4
    655 .IX Item "-S | --short-branchs"
    656 Do not turn relative branchs into absolute ones
    657 when the offset is out of range.
    658 .IP "\fB\-\-strict\-direct\-mode\fR" 4
    659 .IX Item "--strict-direct-mode"
    660 Do not turn the direct addressing mode into extended addressing mode
    661 when the instruction does not support direct addressing mode.
    662 .IP "\fB\-\-print\-insn\-syntax\fR" 4
    663 .IX Item "--print-insn-syntax"
    664 Print the syntax of instruction in case of error.
    665 .IP "\fB\-\-print\-opcodes\fR" 4
    666 .IX Item "--print-opcodes"
    667 print the list of instructions with syntax and then exit.
    668 .IP "\fB\-\-generate\-example\fR" 4
    669 .IX Item "--generate-example"
    670 print an example of instruction for each possible instruction and then exit.
    671 This option is only useful for testing \fBas\fR.
    672 .PP
    673 The following options are available when \fBas\fR is configured
    674 for the \s-1SPARC\s0 architecture:
    675 .IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
    676 .IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
    677 .PD 0
    678 .IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
    679 .IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
    680 .PD
    681 Explicitly select a variant of the \s-1SPARC\s0 architecture.
    682 .Sp
    683 \&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
    684 \&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
    685 .Sp
    686 \&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
    687 UltraSPARC extensions.
    688 .IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
    689 .IX Item "-xarch=v8plus | -xarch=v8plusa"
    690 For compatibility with the Solaris v9 assembler.  These options are
    691 equivalent to \-Av8plus and \-Av8plusa, respectively.
    692 .IP "\fB\-bump\fR" 4
    693 .IX Item "-bump"
    694 Warn when the assembler switches to another architecture.
    695 .PP
    696 The following options are available when as is configured for the 'c54x
    697 architecture.
    698 .IP "\fB\-mfar\-mode\fR" 4
    699 .IX Item "-mfar-mode"
    700 Enable extended addressing mode.  All addresses and relocations will assume
    701 extended addressing (usually 23 bits).
    702 .IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4
    703 .IX Item "-mcpu=CPU_VERSION"
    704 Sets the \s-1CPU\s0 version being compiled for.
    705 .IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4
    706 .IX Item "-merrors-to-file FILENAME"
    707 Redirect error output to a file, for broken systems which don't support such
    708 behaviour in the shell.
    709 .PP
    710 The following options are available when as is configured for
    711 a \s-1MIPS\s0 processor.
    712 .IP "\fB\-G\fR \fInum\fR" 4
    713 .IX Item "-G num"
    714 This option sets the largest size of an object that can be referenced
    715 implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that
    716 use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
    717 .IP "\fB\-EB\fR" 4
    718 .IX Item "-EB"
    719 Generate ``big endian'' format output.
    720 .IP "\fB\-EL\fR" 4
    721 .IX Item "-EL"
    722 Generate ``little endian'' format output.
    723 .IP "\fB\-mips1\fR" 4
    724 .IX Item "-mips1"
    725 .PD 0
    726 .IP "\fB\-mips2\fR" 4
    727 .IX Item "-mips2"
    728 .IP "\fB\-mips3\fR" 4
    729 .IX Item "-mips3"
    730 .IP "\fB\-mips4\fR" 4
    731 .IX Item "-mips4"
    732 .IP "\fB\-mips5\fR" 4
    733 .IX Item "-mips5"
    734 .IP "\fB\-mips32\fR" 4
    735 .IX Item "-mips32"
    736 .IP "\fB\-mips32r2\fR" 4
    737 .IX Item "-mips32r2"
    738 .IP "\fB\-mips64\fR" 4
    739 .IX Item "-mips64"
    740 .PD
    741 Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
    742 \&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
    743 alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
    744 \&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
    745 \&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, and \fB\-mips64\fR
    746 correspond to generic
    747 \&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, and
    748 \&\fB\s-1MIPS64\s0\fR \s-1ISA\s0 processors,
    749 respectively.
    750 .IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4
    751 .IX Item "-march=CPU"
    752 Generate code for a particular \s-1MIPS\s0 cpu.
    753 .IP "\fB\-mtune=\fR\fIcpu\fR" 4
    754 .IX Item "-mtune=cpu"
    755 Schedule and tune for a particular \s-1MIPS\s0 cpu.
    756 .IP "\fB\-mfix7000\fR" 4
    757 .IX Item "-mfix7000"
    758 .PD 0
    759 .IP "\fB\-mno\-fix7000\fR" 4
    760 .IX Item "-mno-fix7000"
    761 .PD
    762 Cause nops to be inserted if the read of the destination register
    763 of an mfhi or mflo instruction occurs in the following two instructions.
    764 .IP "\fB\-mdebug\fR" 4
    765 .IX Item "-mdebug"
    766 .PD 0
    767 .IP "\fB\-no\-mdebug\fR" 4
    768 .IX Item "-no-mdebug"
    769 .PD
    770 Cause stabs-style debugging output to go into an ECOFF-style .mdebug
    771 section instead of the standard \s-1ELF\s0 .stabs sections.
    772 .IP "\fB\-mgp32\fR" 4
    773 .IX Item "-mgp32"
    774 .PD 0
    775 .IP "\fB\-mfp32\fR" 4
    776 .IX Item "-mfp32"
    777 .PD
    778 The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these
    779 flags force a certain group of registers to be treated as 32 bits wide at
    780 all times.  \fB\-mgp32\fR controls the size of general-purpose registers
    781 and \fB\-mfp32\fR controls the size of floating-point registers.
    782 .IP "\fB\-mips16\fR" 4
    783 .IX Item "-mips16"
    784 .PD 0
    785 .IP "\fB\-no\-mips16\fR" 4
    786 .IX Item "-no-mips16"
    787 .PD
    788 Generate code for the \s-1MIPS\s0 16 processor.  This is equivalent to putting
    789 \&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file.  \fB\-no\-mips16\fR
    790 turns off this option.
    791 .IP "\fB\-mips3d\fR" 4
    792 .IX Item "-mips3d"
    793 .PD 0
    794 .IP "\fB\-no\-mips3d\fR" 4
    795 .IX Item "-no-mips3d"
    796 .PD
    797 Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
    798 This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
    799 \&\fB\-no\-mips3d\fR turns off this option.
    800 .IP "\fB\-mdmx\fR" 4
    801 .IX Item "-mdmx"
    802 .PD 0
    803 .IP "\fB\-no\-mdmx\fR" 4
    804 .IX Item "-no-mdmx"
    805 .PD
    806 Generate code for the \s-1MDMX\s0 Application Specific Extension.
    807 This tells the assembler to accept \s-1MDMX\s0 instructions.
    808 \&\fB\-no\-mdmx\fR turns off this option.
    809 .IP "\fB\-\-construct\-floats\fR" 4
    810 .IX Item "--construct-floats"
    811 .PD 0
    812 .IP "\fB\-\-no\-construct\-floats\fR" 4
    813 .IX Item "--no-construct-floats"
    814 .PD
    815 The \fB\-\-no\-construct\-floats\fR option disables the construction of
    816 double width floating point constants by loading the two halves of the
    817 value into the two single width floating point registers that make up
    818 the double width register.  By default \fB\-\-construct\-floats\fR is
    819 selected, allowing construction of these floating point constants.
    820 .IP "\fB\-\-emulation=\fR\fIname\fR" 4
    821 .IX Item "--emulation=name"
    822 This option causes \fBas\fR to emulate \fBas\fR configured
    823 for some other target, in all respects, including output format (choosing
    824 between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
    825 debugging information or store symbol table information, and default
    826 endianness.  The available configuration names are: \fBmipsecoff\fR,
    827 \&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
    828 \&\fBmipsbelf\fR.  The first two do not alter the default endianness from that
    829 of the primary target for which the assembler was configured; the others change
    830 the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
    831 in the name.  Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
    832 selection in any case.
    833 .Sp
    834 This option is currently supported only when the primary target
    835 \&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
    836 Furthermore, the primary target or others specified with
    837 \&\fB\-\-enable\-targets=...\fR at configuration time must include support for
    838 the other format, if both are to be available.  For example, the Irix 5
    839 configuration includes support for both.
    840 .Sp
    841 Eventually, this option will support more configurations, with more
    842 fine-grained control over the assembler's behavior, and will be supported for
    843 more processors.
    844 .IP "\fB\-nocpp\fR" 4
    845 .IX Item "-nocpp"
    846 \&\fBas\fR ignores this option.  It is accepted for compatibility with
    847 the native tools.
    848 .IP "\fB\-\-trap\fR" 4
    849 .IX Item "--trap"
    850 .PD 0
    851 .IP "\fB\-\-no\-trap\fR" 4
    852 .IX Item "--no-trap"
    853 .IP "\fB\-\-break\fR" 4
    854 .IX Item "--break"
    855 .IP "\fB\-\-no\-break\fR" 4
    856 .IX Item "--no-break"
    857 .PD
    858 Control how to deal with multiplication overflow and division by zero.
    859 \&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
    860 (and only work for Instruction Set Architecture level 2 and higher);
    861 \&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
    862 break exception.
    863 .IP "\fB\-n\fR" 4
    864 .IX Item "-n"
    865 When this option is used, \fBas\fR will issue a warning every
    866 time it generates a nop instruction from a macro.
    867 .PP
    868 The following options are available when as is configured for
    869 an MCore processor.
    870 .IP "\fB\-jsri2bsr\fR" 4
    871 .IX Item "-jsri2bsr"
    872 .PD 0
    873 .IP "\fB\-nojsri2bsr\fR" 4
    874 .IX Item "-nojsri2bsr"
    875 .PD
    876 Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation.  By default this is enabled.
    877 The command line option \fB\-nojsri2bsr\fR can be used to disable it.
    878 .IP "\fB\-sifilter\fR" 4
    879 .IX Item "-sifilter"
    880 .PD 0
    881 .IP "\fB\-nosifilter\fR" 4
    882 .IX Item "-nosifilter"
    883 .PD
    884 Enable or disable the silicon filter behaviour.  By default this is disabled.
    885 The default can be overridden by the \fB\-sifilter\fR command line option.
    886 .IP "\fB\-relax\fR" 4
    887 .IX Item "-relax"
    888 Alter jump instructions for long displacements.
    889 .IP "\fB\-mcpu=[210|340]\fR" 4
    890 .IX Item "-mcpu=[210|340]"
    891 Select the cpu type on the target hardware.  This controls which instructions
    892 can be assembled.
    893 .IP "\fB\-EB\fR" 4
    894 .IX Item "-EB"
    895 Assemble for a big endian target.
    896 .IP "\fB\-EL\fR" 4
    897 .IX Item "-EL"
    898 Assemble for a little endian target.
    899 .PP
    900 See the info pages for documentation of the MMIX-specific options.
    901 .PP
    902 The following options are available when as is configured for
    903 an Xtensa processor.
    904 .IP "\fB\-\-density | \-\-no\-density\fR" 4
    905 .IX Item "--density | --no-density"
    906 Enable or disable use of instructions from the Xtensa code density
    907 option.  This is enabled by default when the Xtensa processor supports
    908 the code density option.
    909 .IP "\fB\-\-relax | \-\-no\-relax\fR" 4
    910 .IX Item "--relax | --no-relax"
    911 Enable or disable instruction relaxation.  This is enabled by default.
    912 Note: In the current implementation, these options also control whether
    913 assembler optimizations are performed, making these options equivalent
    914 to \fB\-\-generics\fR and \fB\-\-no\-generics\fR.
    915 .IP "\fB\-\-generics | \-\-no\-generics\fR" 4
    916 .IX Item "--generics | --no-generics"
    917 Enable or disable all assembler transformations of Xtensa instructions.
    918 The default is \fB\-\-generics\fR;
    919 \&\fB\-\-no\-generics\fR should be used only in the rare cases when the
    920 instructions must be exactly as specified in the assembly source.
    921 .IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
    922 .IX Item "--text-section-literals | --no-text-section-literals"
    923 With \fB\-\-text\-section\-literals\fR, literal pools are interspersed
    924 in the text section.  The default is
    925 \&\fB\-\-no\-text\-section\-literals\fR, which places literals in a
    926 separate section in the output file.
    927 .IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
    928 .IX Item "--target-align | --no-target-align"
    929 Enable or disable automatic alignment to reduce branch penalties at the
    930 expense of some code density.  The default is \fB\-\-target\-align\fR.
    931 .IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
    932 .IX Item "--longcalls | --no-longcalls"
    933 Enable or disable transformation of call instructions to allow calls
    934 across a greater range of addresses.  The default is
    935 \&\fB\-\-no\-longcalls\fR.
    936 .SH "SEE ALSO"
    937 .IX Header "SEE ALSO"
    938 \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
    939 .SH "COPYRIGHT"
    940 .IX Header "COPYRIGHT"
    941 Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
    942 .PP
    943 Permission is granted to copy, distribute and/or modify this document
    944 under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
    945 or any later version published by the Free Software Foundation;
    946 with no Invariant Sections, with no Front-Cover Texts, and with no
    947 Back-Cover Texts.  A copy of the license is included in the
    948 section entitled ``\s-1GNU\s0 Free Documentation License''.
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