Changeset 609 for branches/GNU/src/binutils/opcodes/arm-dis.c
- Timestamp:
- Aug 16, 2003, 6:59:22 PM (22 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/GNU/src/binutils/opcodes/arm-dis.c
-
Property cvs2svn:cvs-rev
changed from
1.1
to1.1.1.2
r608 r609 1 1 /* Instruction printing code for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 3 3 Free Software Foundation, Inc. 4 4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 5 5 Modification by James G. Smith (jsmith@cygnus.co.uk) 6 6 7 This file is part of libopcodes. 8 9 This program is free software; you can redistribute it and/or modify it under10 the terms of the GNU General Public License as published by the Free11 Software Foundation; either version 2 of the License, or (at your option)12 any later version. 13 14 This program is distributed in the hope that it will be useful, but WITHOUT15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for17 more details. 18 19 You should have received a copy of the GNU General Public License20 along with this program; if not, write to the Free Software21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */7 This file is part of libopcodes. 8 9 This program is free software; you can redistribute it and/or modify it under 10 the terms of the GNU General Public License as published by the Free 11 Software Foundation; either version 2 of the License, or (at your option) 12 any later version. 13 14 This program is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 22 22 23 23 #include "sysdep.h" … … 29 29 #include "opintl.h" 30 30 31 /* FIXME: This shouldn't be done here */31 /* FIXME: This shouldn't be done here. */ 32 32 #include "elf-bfd.h" 33 33 #include "elf/internal.h" … … 71 71 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 72 72 { "special-atpcs", "Select special register names used in the ATPCS", 73 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} 73 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 74 { "iwmmxt_regnames", "Select register names used on the Intel Wireless MMX technology coprocessor", 75 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}}, 76 { "iwmmxt_Cregnames", "Select control register names used on the Intel Wireless MMX technology coprocessor", 77 {"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}} 78 }; 79 80 static char * iwmmxt_wwnames[] = 81 {"b", "h", "w", "d"}; 82 83 static char * iwmmxt_wwssnames[] = 84 {"b", "bus", "b", "bss", 85 "h", "hus", "h", "hss", 86 "w", "wus", "w", "wss", 87 "d", "dus", "d", "dss" 74 88 }; 75 89 … … 80 94 #define arm_regnames regnames[regname_selected].reg_names 81 95 82 static b oolean force_thumb = false;96 static bfd_boolean force_thumb = FALSE; 83 97 84 98 static char * arm_fp_const[] = 85 99 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 86 100 87 static char * arm_shift[] = 101 static char * arm_shift[] = 88 102 {"lsl", "lsr", "asr", "ror"}; 89 103 90 104 91 105 /* Forward declarations. */ 92 static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); 93 static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); 94 static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); 95 static void parse_disassembler_options PARAMS ((char *)); 96 static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); 97 int get_arm_regname_num_options (void); 98 int set_arm_regname_option (int option); 99 int get_arm_regnames (int option, const char **setname, 100 const char **setdescription, 101 const char ***register_names); 102 103 104 /* Functions. */ 106 static void arm_decode_shift 107 PARAMS ((long, fprintf_ftype, void *)); 108 static int print_insn_arm 109 PARAMS ((bfd_vma, struct disassemble_info *, long)); 110 static int print_insn_thumb 111 PARAMS ((bfd_vma, struct disassemble_info *, long)); 112 static void parse_disassembler_options 113 PARAMS ((char *)); 114 static int print_insn 115 PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean)); 116 static int set_iwmmxt_regnames 117 PARAMS ((void)); 118 119 int get_arm_regname_num_options 120 PARAMS ((void)); 121 int set_arm_regname_option 122 PARAMS ((int)); 123 int get_arm_regnames 124 PARAMS ((int, const char **, const char **, const char ***)); 125 126 127 /* Functions. */ 105 128 int 106 get_arm_regname_num_options ( void)129 get_arm_regname_num_options () 107 130 { 108 131 return NUM_ARM_REGNAMES; … … 110 133 111 134 int 112 set_arm_regname_option (int option) 135 set_arm_regname_option (option) 136 int option; 113 137 { 114 138 int old = regname_selected; … … 118 142 119 143 int 120 get_arm_regnames (int option, const char **setname, 121 const char **setdescription, 122 const char ***register_names) 144 get_arm_regnames (option, setname, setdescription, register_names) 145 int option; 146 const char **setname; 147 const char **setdescription; 148 const char ***register_names; 123 149 { 124 150 *setname = regnames[option].name; … … 135 161 { 136 162 func (stream, "%s", arm_regnames[given & 0xf]); 137 163 138 164 if ((given & 0xff0) != 0) 139 165 { … … 142 168 int amount = (given & 0xf80) >> 7; 143 169 int shift = (given & 0x60) >> 5; 144 170 145 171 if (amount == 0) 146 172 { … … 150 176 return; 151 177 } 152 178 153 179 amount = 32; 154 180 } 155 181 156 182 func (stream, ", %s #%d", arm_shift[shift], amount); 157 183 } … … 162 188 } 163 189 190 static int 191 set_iwmmxt_regnames () 192 { 193 const char * setname; 194 const char * setdesc; 195 const char ** regnames; 196 int iwmmxt_regnames = 0; 197 int num_regnames = get_arm_regname_num_options (); 198 199 get_arm_regnames (iwmmxt_regnames, &setname, 200 &setdesc, ®names); 201 while ((strcmp ("iwmmxt_regnames", setname)) 202 && (iwmmxt_regnames < num_regnames)) 203 get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, ®names); 204 205 return iwmmxt_regnames; 206 } 207 164 208 /* Print one instruction from PC on INFO->STREAM. 165 209 Return the size of the instruction (always 4 on ARM). */ 210 166 211 static int 167 212 print_insn_arm (pc, info, given) 168 bfd_vma pc; 169 struct disassemble_info * info; 170 long given; 171 { 172 struct arm_opcode * insn; 173 void * stream = info->stream; 174 fprintf_ftype func = info->fprintf_func; 213 bfd_vma pc; 214 struct disassemble_info *info; 215 long given; 216 { 217 const struct arm_opcode *insn; 218 void *stream = info->stream; 219 fprintf_ftype func = info->fprintf_func; 220 static int iwmmxt_regnames = 0; 175 221 176 222 for (insn = arm_opcodes; insn->assembler; insn++) 177 223 { 224 if (insn->value == FIRST_IWMMXT_INSN 225 && info->mach != bfd_mach_arm_XScale 226 && info->mach != bfd_mach_arm_iWMMXt) 227 insn = insn + IWMMXT_INSN_COUNT; 228 178 229 if ((given & insn->mask) == insn->value) 179 230 { 180 231 char * c; 181 232 182 233 for (c = insn->assembler; *c; c++) 183 234 { … … 195 246 { 196 247 int offset = given & 0xfff; 197 248 198 249 func (stream, "[pc"); 199 250 200 251 if (given & 0x01000000) 201 252 { 202 253 if ((given & 0x00800000) == 0) 203 254 offset = - offset; 204 205 /* pre-indexed*/206 func (stream, ", #% x]", offset);255 256 /* Pre-indexed. */ 257 func (stream, ", #%d]", offset); 207 258 208 259 offset += pc + 8; … … 218 269 { 219 270 /* Post indexed. */ 220 func (stream, "], #%x", offset); 221 222 offset = pc + 8; /* ie ignore the offset. */ 271 func (stream, "], #%d", offset); 272 273 /* ie ignore the offset. */ 274 offset = pc + 8; 223 275 } 224 276 225 277 func (stream, "\t; "); 226 278 info->print_address_func (offset, info); … … 228 280 else 229 281 { 230 func (stream, "[%s", 282 func (stream, "[%s", 231 283 arm_regnames[(given >> 16) & 0xf]); 232 284 if ((given & 0x01000000) != 0) … … 248 300 } 249 301 250 func (stream, "]%s", 302 func (stream, "]%s", 251 303 ((given & 0x00200000) != 0) ? "!" : ""); 252 304 } … … 260 312 (((given & 0x00800000) == 0) 261 313 ? "-" : ""), offset); 262 else 314 else 263 315 func (stream, "]"); 264 316 } … … 266 318 { 267 319 func (stream, "], %s", 268 (((given & 0x00800000) == 0) 320 (((given & 0x00800000) == 0) 269 321 ? "-" : "")); 270 322 arm_decode_shift (given, func, stream); … … 279 331 /* PC relative with immediate offset. */ 280 332 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 281 333 282 334 if ((given & 0x00800000) == 0) 283 335 offset = -offset; 284 285 func (stream, "[pc, #% x]\t; ", offset);286 336 337 func (stream, "[pc, #%d]\t; ", offset); 338 287 339 (*info->print_address_func) 288 340 (offset + pc + 8, info); … … 290 342 else 291 343 { 292 func (stream, "[%s", 344 func (stream, "[%s", 293 345 arm_regnames[(given >> 16) & 0xf]); 294 346 if ((given & 0x01000000) != 0) … … 313 365 } 314 366 315 func (stream, "]%s", 367 func (stream, "]%s", 316 368 ((given & 0x00200000) != 0) ? "!" : ""); 317 369 } … … 327 379 (((given & 0x00800000) == 0) 328 380 ? "-" : ""), offset); 329 else 381 else 330 382 func (stream, "]"); 331 383 } … … 341 393 } 342 394 break; 343 395 344 396 case 'b': 345 397 (*info->print_address_func) … … 391 443 if ((given & 0x01200000) == 0x00200000) 392 444 func (stream, "t"); 393 break;394 395 case 'h':396 if ((given & 0x00000020) == 0x00000020)397 func (stream, "h");398 else399 func (stream, "b");400 445 break; 401 446 … … 430 475 bfd_vma address; 431 476 bfd_vma offset = 0; 432 477 433 478 if (given & 0x00800000) 434 479 /* Is signed, hi bits should be ones. */ … … 439 484 offset <<= 2; 440 485 address = offset + pc + 8; 441 486 442 487 if (given & 0x01000000) 443 488 /* H bit allows addressing to 2-byte boundaries. */ … … 446 491 info->print_address_func (address, info); 447 492 } 493 break; 494 495 case 'I': 496 /* Print a Cirrus/DSP shift immediate. */ 497 /* Immediates are 7bit signed ints with bits 0..3 in 498 bits 0..3 of opcode and bits 4..6 in bits 5..7 499 of opcode. */ 500 { 501 int imm; 502 503 imm = (given & 0xf) | ((given & 0xe0) >> 1); 504 505 /* Is ``imm'' a negative number? */ 506 if (imm & 0x40) 507 imm |= (-1 << 7); 508 509 func (stream, "%d", imm); 510 } 511 448 512 break; 449 513 … … 476 540 } 477 541 break; 478 542 479 543 case 'P': 480 544 switch (given & 0x00080080) … … 528 592 break; 529 593 530 case '0': case '1': case '2': case '3': case '4': 594 case '0': case '1': case '2': case '3': case '4': 531 595 case '5': case '6': case '7': case '8': case '9': 532 596 { … … 540 604 case '-': 541 605 c++; 542 606 543 607 while (*c >= '0' && *c <= '9') 544 608 bitend = (bitend * 10) + *c++ - '0'; 545 609 546 610 if (!bitend) 547 611 abort (); 548 612 549 613 switch (*c) 550 614 { … … 552 616 { 553 617 long reg; 554 618 555 619 reg = given >> bitstart; 556 620 reg &= (2 << (bitend - bitstart)) - 1; 557 621 558 622 func (stream, "%s", arm_regnames[reg]); 559 623 } … … 562 626 { 563 627 long reg; 564 628 565 629 reg = given >> bitstart; 566 630 reg &= (2 << (bitend - bitstart)) - 1; 567 631 568 632 func (stream, "%d", reg); 569 633 } … … 572 636 { 573 637 long reg; 574 638 575 639 reg = given >> bitstart; 576 640 reg &= (2 << (bitend - bitstart)) - 1; 577 641 578 642 func (stream, "0x%08x", reg); 579 643 580 644 /* Some SWI instructions have special 581 645 meanings. */ … … 589 653 { 590 654 long reg; 591 655 592 656 reg = given >> bitstart; 593 657 reg &= (2 << (bitend - bitstart)) - 1; 594 658 595 659 func (stream, "%01x", reg & 0xf); 596 660 } … … 599 663 { 600 664 long reg; 601 665 602 666 reg = given >> bitstart; 603 667 reg &= (2 << (bitend - bitstart)) - 1; 604 668 605 669 if (reg > 7) 606 670 func (stream, "#%s", … … 610 674 } 611 675 break; 676 677 case 'w': 678 { 679 long reg; 680 681 if (bitstart != bitend) 682 { 683 reg = given >> bitstart; 684 reg &= (2 << (bitend - bitstart)) - 1; 685 if (bitend - bitstart == 1) 686 func (stream, "%s", iwmmxt_wwnames[reg]); 687 else 688 func (stream, "%s", iwmmxt_wwssnames[reg]); 689 } 690 else 691 { 692 reg = (((given >> 8) & 0x1) | 693 ((given >> 22) & 0x1)); 694 func (stream, "%s", iwmmxt_wwnames[reg]); 695 } 696 } 697 break; 698 699 case 'g': 700 { 701 long reg; 702 int current_regnames; 703 704 if (! iwmmxt_regnames) 705 iwmmxt_regnames = set_iwmmxt_regnames (); 706 current_regnames = set_arm_regname_option 707 (iwmmxt_regnames); 708 709 reg = given >> bitstart; 710 reg &= (2 << (bitend - bitstart)) - 1; 711 func (stream, "%s", arm_regnames[reg]); 712 set_arm_regname_option (current_regnames); 713 } 714 break; 715 716 case 'G': 717 { 718 long reg; 719 int current_regnames; 720 721 if (! iwmmxt_regnames) 722 iwmmxt_regnames = set_iwmmxt_regnames (); 723 current_regnames = set_arm_regname_option 724 (iwmmxt_regnames + 1); 725 726 reg = given >> bitstart; 727 reg &= (2 << (bitend - bitstart)) - 1; 728 func (stream, "%s", arm_regnames[reg]); 729 set_arm_regname_option (current_regnames); 730 } 731 break; 732 612 733 default: 613 734 abort (); 614 735 } 615 736 break; 616 737 738 case 'y': 739 case 'z': 740 { 741 int single = *c == 'y'; 742 int regno; 743 744 switch (bitstart) 745 { 746 case 4: /* Sm pair */ 747 func (stream, "{"); 748 /* Fall through. */ 749 case 0: /* Sm, Dm */ 750 regno = given & 0x0000000f; 751 if (single) 752 { 753 regno <<= 1; 754 regno += (given >> 5) & 1; 755 } 756 break; 757 758 case 1: /* Sd, Dd */ 759 regno = (given >> 12) & 0x0000000f; 760 if (single) 761 { 762 regno <<= 1; 763 regno += (given >> 22) & 1; 764 } 765 break; 766 767 case 2: /* Sn, Dn */ 768 regno = (given >> 16) & 0x0000000f; 769 if (single) 770 { 771 regno <<= 1; 772 regno += (given >> 7) & 1; 773 } 774 break; 775 776 case 3: /* List */ 777 func (stream, "{"); 778 regno = (given >> 12) & 0x0000000f; 779 if (single) 780 { 781 regno <<= 1; 782 regno += (given >> 22) & 1; 783 } 784 break; 785 786 787 default: 788 abort (); 789 } 790 791 func (stream, "%c%d", single ? 's' : 'd', regno); 792 793 if (bitstart == 3) 794 { 795 int count = given & 0xff; 796 797 if (single == 0) 798 count >>= 1; 799 800 if (--count) 801 { 802 func (stream, "-%c%d", 803 single ? 's' : 'd', 804 regno + count); 805 } 806 807 func (stream, "}"); 808 } 809 else if (bitstart == 4) 810 func (stream, ", %c%d}", single ? 's' : 'd', 811 regno + 1); 812 813 break; 814 } 815 617 816 case '`': 618 817 c++; … … 637 836 break; 638 837 838 case 'L': 839 switch (given & 0x00400100) 840 { 841 case 0x00000000: func (stream, "b"); break; 842 case 0x00400000: func (stream, "h"); break; 843 case 0x00000100: func (stream, "w"); break; 844 case 0x00400100: func (stream, "d"); break; 845 default: 846 break; 847 } 848 break; 849 850 case 'Z': 851 { 852 int value; 853 /* given (20, 23) | given (0, 3) */ 854 value = ((given >> 16) & 0xf0) | (given & 0xf); 855 func (stream, "%d", value); 856 } 857 break; 858 859 case 'l': 860 /* This is like the 'A' operator, except that if 861 the width field "M" is zero, then the offset is 862 *not* multiplied by four. */ 863 { 864 int offset = given & 0xff; 865 int multiplier = (given & 0x00000100) ? 4 : 1; 866 867 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 868 869 if (offset) 870 { 871 if ((given & 0x01000000) != 0) 872 func (stream, ", %s#%d]%s", 873 ((given & 0x00800000) == 0 ? "-" : ""), 874 offset * multiplier, 875 ((given & 0x00200000) != 0 ? "!" : "")); 876 else 877 func (stream, "], %s#%d", 878 ((given & 0x00800000) == 0 ? "-" : ""), 879 offset * multiplier); 880 } 881 else 882 func (stream, "]"); 883 } 884 break; 885 639 886 default: 640 887 abort (); … … 653 900 /* Print one instruction from PC on INFO->STREAM. 654 901 Return the size of the instruction. */ 902 655 903 static int 656 904 print_insn_thumb (pc, info, given) 657 bfd_vma 658 struct disassemble_info * 659 long 660 { 661 struct thumb_opcode *insn;662 void * 663 fprintf_ftype 905 bfd_vma pc; 906 struct disassemble_info *info; 907 long given; 908 { 909 const struct thumb_opcode *insn; 910 void *stream = info->stream; 911 fprintf_ftype func = info->fprintf_func; 664 912 665 913 for (insn = thumb_opcodes; insn->assembler; insn++) … … 672 920 if (!*c) /* Check for empty (not NULL) assembler string. */ 673 921 { 922 long offset; 923 674 924 info->bytes_per_chunk = 4; 675 925 info->bytes_per_line = 4; 676 926 927 offset = BDISP23 (given); 928 offset = offset * 2 + pc + 4; 929 677 930 if ((given & 0x10000000) == 0) 678 func (stream, "blx\t"); 931 { 932 func (stream, "blx\t"); 933 offset &= 0xfffffffc; 934 } 679 935 else 680 681 682 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);936 func (stream, "bl\t"); 937 938 info->print_address_func (offset, info); 683 939 return 4; 684 940 } … … 687 943 info->bytes_per_chunk = 2; 688 944 info->bytes_per_line = 4; 689 945 690 946 given &= 0xffff; 691 947 692 948 for (; *c; c++) 693 949 { … … 696 952 int domaskpc = 0; 697 953 int domasklr = 0; 698 954 699 955 switch (*++c) 700 956 { … … 706 962 { 707 963 long reg; 708 964 709 965 reg = (given >> 3) & 0x7; 710 966 if (given & (1 << 6)) 711 967 reg += 8; 712 968 713 969 func (stream, "%s", arm_regnames[reg]); 714 970 } … … 718 974 { 719 975 long reg; 720 976 721 977 reg = given & 0x7; 722 978 if (given & (1 << 7)) 723 979 reg += 8; 724 980 725 981 func (stream, "%s", arm_regnames[reg]); 726 982 } … … 744 1000 int started = 0; 745 1001 int reg; 746 1002 747 1003 func (stream, "{"); 748 1004 749 1005 /* It would be nice if we could spot 750 1006 ranges, and generate the rS-rE format: */ … … 778 1034 779 1035 780 case '0': case '1': case '2': case '3': case '4': 1036 case '0': case '1': case '2': case '3': case '4': 781 1037 case '5': case '6': case '7': case '8': case '9': 782 1038 { 783 1039 int bitstart = *c++ - '0'; 784 1040 int bitend = 0; 785 1041 786 1042 while (*c >= '0' && *c <= '9') 787 1043 bitstart = (bitstart * 10) + *c++ - '0'; … … 792 1048 { 793 1049 long reg; 794 1050 795 1051 c++; 796 1052 while (*c >= '0' && *c <= '9') … … 884 1140 885 1141 /* Parse an individual disassembler option. */ 1142 886 1143 void 887 1144 parse_arm_disassembler_option (option) … … 890 1147 if (option == NULL) 891 1148 return; 892 1149 893 1150 if (strneq (option, "reg-names-", 10)) 894 1151 { 895 1152 int i; 896 1153 897 1154 option += 10; 898 1155 … … 903 1160 break; 904 1161 } 905 1162 906 1163 if (i < 0) 907 1164 fprintf (stderr, _("Unrecognised register name set: %s\n"), option); … … 913 1170 else 914 1171 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 915 1172 916 1173 return; 917 1174 } 918 1175 919 1176 /* Parse the string of disassembler options, spliting it at whitespaces. */ 1177 920 1178 static void 921 1179 parse_disassembler_options (options) … … 923 1181 { 924 1182 char * space; 925 1183 926 1184 if (options == NULL) 927 1185 return; … … 946 1204 /* NOTE: There are no checks in these routines that 947 1205 the relevant number of data bytes exist. */ 1206 948 1207 static int 949 1208 print_insn (pc, info, little) 950 1209 bfd_vma pc; 951 1210 struct disassemble_info * info; 952 b oolean little;1211 bfd_boolean little; 953 1212 { 954 1213 unsigned char b[4]; … … 960 1219 { 961 1220 parse_disassembler_options (info->disassembler_options); 962 1221 963 1222 /* To avoid repeated parsing of these options, we remove them here. */ 964 1223 info->disassembler_options = NULL; 965 1224 } 966 1225 967 1226 is_thumb = force_thumb; 968 1227 969 1228 if (!is_thumb && info->symbols != NULL) 970 1229 { … … 972 1231 { 973 1232 coff_symbol_type * cs; 974 1233 975 1234 cs = coffsymbol (*info->symbols); 976 1235 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT … … 984 1243 elf_symbol_type * es; 985 1244 unsigned int type; 986 1245 987 1246 es = *(elf_symbol_type **)(info->symbols); 988 1247 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 989 1248 990 1249 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); 991 1250 } 992 1251 } 993 1252 994 1253 info->bytes_per_chunk = 4; 995 1254 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; … … 1001 1260 { 1002 1261 info->bytes_per_chunk = 2; 1003 1262 1004 1263 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 1005 1264 b[3] = b[2] = 0; 1006 1265 } 1007 1266 1008 1267 if (status != 0) 1009 1268 { … … 1011 1270 return -1; 1012 1271 } 1013 1272 1014 1273 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 1015 1274 } … … 1023 1282 return -1; 1024 1283 } 1025 1284 1026 1285 if (is_thumb) 1027 1286 { … … 1029 1288 { 1030 1289 given = (b[2] << 8) | b[3]; 1031 1290 1032 1291 status = info->read_memory_func 1033 1292 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); … … 1037 1296 return -1; 1038 1297 } 1039 1298 1040 1299 given |= (b[0] << 24) | (b[1] << 16); 1041 1300 } … … 1046 1305 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); 1047 1306 } 1048 1307 1049 1308 if (info->flags & INSN_HAS_RELOC) 1050 1309 /* If the instruction has a reloc associated with it, then … … 1054 1313 addresses, since the addend is not currently pc-relative. */ 1055 1314 pc = 0; 1056 1315 1057 1316 if (is_thumb) 1058 1317 status = print_insn_thumb (pc, info, given); … … 1068 1327 struct disassemble_info * info; 1069 1328 { 1070 return print_insn (pc, info, false);1329 return print_insn (pc, info, FALSE); 1071 1330 } 1072 1331 … … 1076 1335 struct disassemble_info * info; 1077 1336 { 1078 return print_insn (pc, info, true);1337 return print_insn (pc, info, TRUE); 1079 1338 } 1080 1339 … … 1087 1346 The following ARM specific disassembler options are supported for use with\n\ 1088 1347 the -M switch:\n")); 1089 1348 1090 1349 for (i = NUM_ARM_REGNAMES; i--;) 1091 1350 fprintf (stream, " reg-names-%s %*c%s\n", 1092 1351 regnames[i].name, 1093 14 - strlen (regnames[i].name), ' ',1352 (int)(14 - strlen (regnames[i].name)), ' ', 1094 1353 regnames[i].description); 1095 1354 -
Property cvs2svn:cvs-rev
changed from
Note:
See TracChangeset
for help on using the changeset viewer.