Changeset 174 for trunk/src/os2ahci/ahci.c
- Timestamp:
- Nov 10, 2013, 4:56:20 PM (12 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/src/os2ahci/ahci.c
r171 r174 315 315 /* more ports in port_map than in HOST_CAP & 0x1f */ 316 316 ports = ai->hw_ports; 317 dprintf("implemented port map (0x%lx) contains more " 318 "ports than nr_ports (%d), using nr_ports\n", 319 ai->port_map, ports); 317 dprintf("implemented port map (0x%lx) contains more ports than nr_ports (%d), using nr_ports\n", ai->port_map, ports); 320 318 ai->port_map = (1UL << ports) - 1UL; 321 319 } … … 347 345 readl(ai->mmio + HOST_CTL); 348 346 349 if ((ai->bios_config[HOST_CTL / sizeof(u32)] & HOST_AHCI_EN) == 0 && 350 ai->pci_vendor == PCI_VENDOR_ID_INTEL) { 347 if ((ai->bios_config[HOST_CTL / sizeof(u32)] & HOST_AHCI_EN) == 0 && ai->pci_vendor == PCI_VENDOR_ID_INTEL) { 351 348 352 349 /* This BIOS apparently accesses the controller via SATA registers and … … 410 407 } 411 408 409 #ifdef NOT_USED 412 410 int ahci_reset_controller(AD_INFO *ai) 413 411 { … … 416 414 417 415 dprintf("controller reset starting on adapter %d\n", ad_no(ai)); 418 /* we must be in AHCI mode, before using anything 419 * AHCI-specific, such as HOST_RESET. 420 */ 416 417 /* we must be in AHCI mode, before using anything AHCI-specific, such as HOST_RESET. */ 421 418 ahci_enable_ahci(ai); 422 419 … … 445 442 ahci_enable_ahci(ai); 446 443 447 /* Some registers might be cleared on reset. Restore 448 * initial values. 449 */ 444 /* Some registers might be cleared on reset. Restore initial values. */ 450 445 ahci_restore_initial_config(ai); 451 446 … … 465 460 return 0; 466 461 } 462 #endif 467 463 468 464 /****************************************************************************** … … 769 765 writel(port_mmio + PORT_SCR_ERR, tmp); 770 766 771 /* power up and spin up the drive if necessary */ 772 if (((tmp = readl(port_mmio + PORT_CMD)) & (PORT_CMD_SPIN_UP|PORT_CMD_POWER_ON)) != (PORT_CMD_SPIN_UP|PORT_CMD_POWER_ON)) { 773 writel(port_mmio + PORT_CMD, tmp | PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON); 774 } 767 /* Some hardware reports incorrect status so just set these bits unconditionally */ 768 tmp = readl(port_mmio + PORT_CMD); 769 tmp &= ~PORT_CMD_ALPE; /* turn off agressive power management */ 770 tmp |= (PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON); /* power up and spin up the drive */ 771 writel(port_mmio + PORT_CMD, tmp); 775 772 776 773 /* set link speed and power management options */ … … 1309 1306 rc = timer_check_and_block(&Timer); 1310 1307 if (rc) { 1311 dprintf(" Timeout" , tmp);1308 dprintf(" Timeout"); 1312 1309 break; 1313 1310 } 1314 1311 } 1315 1312 1316 if ((tmp = readl(port_mmio + PORT_SCR_ERR)) != 0) { 1313 tmp = readl(port_mmio + PORT_SCR_ERR); 1314 if (tmp & PORT_ERR_FAIL_BITS) { 1317 1315 dprintf(" SERR = 0x%08lx", tmp); 1318 1316 rc = 1;
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