| 1 | /******************************************************************************
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| 2 | * os2ahci.h - main header file for os2ahci driver
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| 3 | *
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| 4 | * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
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| 5 | * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
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| 6 | *
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| 7 | * This program is free software; you can redistribute it and/or modify
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| 8 | * it under the terms of the GNU General Public License as published by
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| 9 | * the Free Software Foundation; either version 2 of the License, or
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| 10 | * (at your option) any later version.
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| 11 | *
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| 12 | * This program is distributed in the hope that it will be useful,
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| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 15 | * GNU General Public License for more details.
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| 16 | *
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| 17 | * You should have received a copy of the GNU General Public License
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| 18 | * along with this program; if not, write to the Free Software
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| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 20 | */
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| 21 |
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| 22 | /* ----------------------------- include files ----------------------------- */
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| 23 |
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| 24 | /* IMPORTANT NOTE: The DDK headers require tight structure packing and this
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| 25 | * is controlled via compiler parameters. Thus, all stuctures in os2ahci.sys
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| 26 | * are expected to be byte-aligned without the need of explicit pragma pack()
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| 27 | * directives. Where possible, the structures are layed out such that words
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| 28 | * and dwords are aligned at least on 2-byte boundaries.
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| 29 | */
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| 30 |
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| 31 | #define INCL_NOPMAPI
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| 32 | #define INCL_DOSINFOSEG
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| 33 | #define INCL_NO_SCB
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| 34 | #define INCL_DOSERRORS
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| 35 | #include <os2.h>
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| 36 | #include <dos.h>
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| 37 | #include <bseerr.h>
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| 38 | #include <dskinit.h>
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| 39 | #include <scb.h>
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| 40 |
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| 41 | #include <devhdr.h>
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| 42 | #include <iorb.h>
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| 43 | #include <strat2.h>
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| 44 | #include <reqpkt.h>
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| 45 |
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| 46 | #ifdef __WATCOMC__
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| 47 | /* include WATCOM specific DEVHELP stubs */
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| 48 | #include <devhelp.h>
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| 49 | #else
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| 50 | #include <dhcalls.h>
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| 51 | #endif
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| 52 |
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| 53 | #include <addcalls.h>
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| 54 | #include <rmcalls.h>
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| 55 | #include <devclass.h>
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| 56 | #include <devcmd.h>
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| 57 | #include <rmbase.h>
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| 58 |
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| 59 | #include "ahci.h"
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| 60 | #include "version.h"
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| 61 |
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| 62 | /* -------------------------- macros and constants ------------------------- */
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| 63 |
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| 64 | #define MAX_AD 8 /* maximum number of adapters */
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| 65 |
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| 66 | /* Timer pool size. In theory, we need one timer per outstanding command plus
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| 67 | * a few miscellaneous timers but it's unlikely we'll ever have outstanding
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| 68 | * commands on all devices on all ports on all apapters -- this would be
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| 69 | * 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
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| 70 | * devices and that's a bit of an exaggeration. It should be more than enough
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| 71 | * to have 128 timers.
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| 72 | */
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| 73 | #define TIMER_COUNT 128
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| 74 | #define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
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| 75 | TIMER_COUNT * sizeof(ADD_TIMER_DATA))
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| 76 |
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| 77 | /* default command timeout (can be overwritten in the IORB) */
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| 78 | #define DEFAULT_TIMEOUT 30000
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| 79 |
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| 80 | /* debug output macros */
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| 81 | #define dprintf if (debug > 0) printf
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| 82 | #define dphex if (debug > 0) phex
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| 83 | #define ddprintf if (debug > 1) printf
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| 84 | #define ddphex if (debug > 1) phex
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| 85 | #define dddprintf if (debug > 2) printf
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| 86 | #define dddphex if (debug > 2) phex
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| 87 |
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| 88 | /* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
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| 89 | #define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
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| 90 |
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| 91 | /* Convert far function address into NPFN (the DDK needs this all over the
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| 92 | * place and just casting to NPFN will produce a "segment lost in conversion"
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| 93 | * warning. Since casting to a u32 is a bit nasty for function pointers and
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| 94 | * might have to be revised for different compilers, we'll use a central
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| 95 | * macro for this crap.
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| 96 | */
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| 97 | #define mk_NPFN(func) (NPFN) (u32) (func)
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| 98 |
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| 99 | /* stdarg.h macros with explicit far pointers
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| 100 | *
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| 101 | * NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
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| 102 | * the last fixed argument (i.e. the one passed to va_start) must
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| 103 | * have at least 16 bits. Otherwise, the address calculation in
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| 104 | * va_start() will fail.
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| 105 | */
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| 106 | typedef char _far *va_list;
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| 107 | #define va_start(va, last) va = (va_list) (&last + 1)
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| 108 | #define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
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| 109 | #define va_end(va) va = 0
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| 110 |
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| 111 | /* ctype macros */
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| 112 | #define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
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| 113 | #define tolower(ch) (isupper(ch) ? (ch) - ('a' - 'A') : (ch))
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| 114 |
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| 115 | /* stddef macros */
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| 116 | #define offsetof(s, e) ((u16) &((s *) 0)->e)
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| 117 |
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| 118 | /* SMP spinlock compatibility macros for older DDKs using CLI/STI */
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| 119 | #ifndef OS2AHCI_SMP
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| 120 | #define DevHelp_CreateSpinLock(sph) *(sph) = 0
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| 121 | #define DevHelp_FreeSpinLock(sph) 0
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| 122 |
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| 123 | #define DevHelp_AquireSpinLock(sph) if ((sph) != 0) \
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| 124 | panic("recursive spinlock"); \
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| 125 | (sph) = disable()
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| 126 |
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| 127 | #define DevHelp_ReleaseSpinLock(sph) if (sph) { \
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| 128 | (sph) = 0; \
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| 129 | enable(); \
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| 130 | }
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| 131 | #endif
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| 132 |
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| 133 | /* shortcut macros */
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| 134 | #define spin_lock(sl) DevHelp_AquireSpinLock(sl)
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| 135 | #define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
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| 136 |
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| 137 | /* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
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| 138 | * MMIO addresses are assumed to be valid 16:16 pointers which implies
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| 139 | * that one GDT selector is allocated per adapter.
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| 140 | */
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| 141 | #define port_base(ai, p) ((u8 _far *) (ai)->mmio + 0x100 + (p) * 0x80)
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| 142 |
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| 143 | /* Get address of port-specific DMA scratch buffer. The total size of all DMA
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| 144 | * buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
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| 145 | * GDT selectors to access all port DMA scratch buffers and some logic to map
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| 146 | * a port number to the corresponding DMA scratch buffer address.
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| 147 | */
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| 148 | #define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
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| 149 | #define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
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| 150 | / PORT_DMA_BUFS_PER_SEG)
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| 151 | #define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
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| 152 | (u32) AHCI_PORT_PRIV_DMA_SZ)
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| 153 |
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| 154 | #define port_dma_base(ai, p) \
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| 155 | ((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
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| 156 | ((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
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| 157 |
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| 158 | #define port_dma_base_phys(ai, p) \
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| 159 | ((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
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| 160 |
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| 161 | /* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
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| 162 | * (and the other way round). The mapping looks like this:
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| 163 | *
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| 164 | * mapping comment
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| 165 | * -----------------------------------------------------------------------
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| 166 | * 4 bits for the adapter current max is 8 adapters
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| 167 | * 4 bits for the port AHCI spec defines up to 32 ports
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| 168 | * 4 bits for the device SATA spec defines up to 15 devices behind PMP
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| 169 | */
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| 170 | #define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) | \
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| 171 | (((u16) (p) & 0x0fU) << 4) | \
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| 172 | (((u16) (d) & 0x0fU)))
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| 173 | #define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
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| 174 | #define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
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| 175 | #define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
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| 176 |
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| 177 | /*******************************************************************************
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| 178 | * Convenience macros for IORB processing functions
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| 179 | */
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| 180 | /* is this IORB on driver or port level? */
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| 181 | #define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
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| 182 |
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| 183 | /* is this IORB to be inserted at the beginnig of the IORB queue? */
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| 184 | #define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
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| 185 | (iorb)->CommandModifier == IOCM_ABORT))
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| 186 |
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| 187 | /* access IORB ADD workspace */
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| 188 | #define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
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| 189 |
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| 190 | /* free resources in ADD workspace (timer, buffer, ...) */
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| 191 | #define aws_free(aws) if ((aws)->timer != 0) { \
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| 192 | ADD_CancelTimer((aws)->timer); \
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| 193 | (aws)->timer = 0; \
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| 194 | } \
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| 195 | if ((aws)->buf != NULL) { \
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| 196 | free((aws)->buf); \
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| 197 | (aws)->buf = NULL; \
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| 198 | }
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| 199 |
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| 200 | /******************************************************************************
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| 201 | * PCI generic IDs and macros
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| 202 | */
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| 203 | #define PCI_ANY_ID 0xffffU
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| 204 | #define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
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| 205 | PCI_ANY_ID, PCI_ANY_ID, 0, 0
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| 206 |
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| 207 | /******************************************************************************
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| 208 | * PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
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| 209 | * pci_ids.h)
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| 210 | */
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| 211 | #define PCI_VENDOR_ID_AL 0x10b9
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| 212 | #define PCI_VENDOR_ID_AMD 0x1022
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| 213 | #define PCI_VENDOR_ID_AT 0x1259
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| 214 | #define PCI_VENDOR_ID_ATI 0x1002
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| 215 | #define PCI_VENDOR_ID_ATT 0x11c1
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| 216 | #define PCI_VENDOR_ID_CMD 0x1095
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| 217 | #define PCI_VENDOR_ID_CT 0x102c
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| 218 | #define PCI_VENDOR_ID_INTEL 0x8086
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| 219 | #define PCI_VENDOR_ID_INITIO 0x1101
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| 220 | #define PCI_VENDOR_ID_JMICRON 0x197B
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| 221 | #define PCI_VENDOR_ID_MARVELL 0x11ab
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| 222 | #define PCI_VENDOR_ID_NVIDIA 0x10de
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| 223 | #define PCI_VENDOR_ID_PROMISE 0x105a
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| 224 | #define PCI_VENDOR_ID_SI 0x1039
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| 225 | #define PCI_VENDOR_ID_VIA 0x1106
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| 226 |
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| 227 | /******************************************************************************
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| 228 | * PCI class IDs we're interested in (copied from Linux pci_ids.h)
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| 229 | */
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| 230 | #define PCI_BASE_CLASS_STORAGE 0x01
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| 231 | #define PCI_CLASS_STORAGE_SCSI 0x0100
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| 232 | #define PCI_CLASS_STORAGE_IDE 0x0101
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| 233 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102
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| 234 | #define PCI_CLASS_STORAGE_IPI 0x0103
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| 235 | #define PCI_CLASS_STORAGE_RAID 0x0104
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| 236 | #define PCI_CLASS_STORAGE_SATA 0x0106
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| 237 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
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| 238 | #define PCI_CLASS_STORAGE_SAS 0x0107
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| 239 | #define PCI_CLASS_STORAGE_OTHER 0x0180
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| 240 |
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| 241 | /* ------------------------ typedefs and structures ------------------------ */
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| 242 |
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| 243 | typedef unsigned int size_t;
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| 244 |
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| 245 | /* PCI device information structure; this is used both for scanning and for
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| 246 | * identification purposes in 'AD_INFO'; based on the Linux pci_device_id
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| 247 | * structure but hard-wired to use board_* constants for 'driver_data'
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| 248 | */
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| 249 | typedef struct {
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| 250 | u16 vendor; /* PCI device vendor/manufacturer */
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| 251 | u16 device; /* PCI device ID inside vendor scope */
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| 252 | u16 subvendor; /* subsystem vendor (unused so far) */
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| 253 | u16 subdevice; /* subsystem device (unused so far) */
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| 254 | u32 class; /* PCI device class */
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| 255 | u32 class_mask; /* bits to match when scanning for 'class' */
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| 256 | u32 board; /* AHCI controller board type (board_* constants) */
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| 257 | } PCI_ID;
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| 258 |
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| 259 | /* IORB queue; since IORB queues are updated at interrupt time, the
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| 260 | * corresponding pointers (not the data they point to) need to be volatile.
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| 261 | */
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| 262 | typedef struct {
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| 263 | IORBH _far *volatile root; /* root of request list */
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| 264 | IORBH _far *volatile tail; /* tail of request list */
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| 265 | } IORB_QUEUE;
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| 266 |
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| 267 | /* port information structure */
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| 268 | typedef struct {
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| 269 | IORB_QUEUE iorb_queue; /* IORB queue for this port */
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| 270 | unsigned dev_max : 4; /* maximum device number on this port (0-15) */
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| 271 | unsigned cmd_slot : 5; /* current command slot index (using round-
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| 272 | * robin indexes to prevent starvation) */
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| 273 |
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| 274 | volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
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| 275 | volatile u32 reg_cmds; /* bitmap for regular commands issued */
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| 276 |
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| 277 | struct {
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| 278 | unsigned allocated : 1; /* if != 0, device is allocated */
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| 279 | unsigned present : 1; /* if != 0, device is present */
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| 280 | unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
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| 281 | unsigned atapi : 1; /* if != 0, this is an ATAPI device */
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| 282 | unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
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| 283 | unsigned removable : 1; /* if != 0, device has removable media */
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| 284 | unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
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| 285 | unsigned ncq_max : 5; /* maximum tag number for queued commands */
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| 286 | UNITINFO _far *unit_info; /* pointer to modified unit info */
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| 287 | } devs[15];
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| 288 | } P_INFO;
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| 289 |
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| 290 | /* adapter information structure */
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| 291 | typedef struct {
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| 292 | PCI_ID *pci; /* pointer to corresponding PCI ID */
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| 293 |
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| 294 | unsigned port_max : 5; /* maximum port number (0-31) */
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| 295 | unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
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| 296 | unsigned port_scan_done : 1; /* if != 0, port scan already done */
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| 297 | unsigned busy : 1; /* if != 0, adapter is busy */
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| 298 |
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| 299 | u32 port_map; /* bitmap of active ports */
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| 300 |
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| 301 | /* initial adapter configuration from BIOS */
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| 302 | u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
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| 303 |
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| 304 | u32 cap; /* working copy of CAP register */
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| 305 | u32 cap2; /* working copy of CAP2 register */
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| 306 | u32 flags; /* adapter flags */
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| 307 |
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| 308 | HRESOURCE rm_adh; /* resource handle for adapter */
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| 309 | HRESOURCE rm_mmio; /* resource handle for MMIO */
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| 310 | HRESOURCE rm_irq; /* resource handle for IRQ */
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| 311 |
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| 312 | u8 bus; /* PCI bus number */
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| 313 | u8 dev_func; /* PCI device and function number */
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| 314 | u16 irq; /* interrupt number */
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| 315 |
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| 316 | u32 mmio_phys; /* physical address of MMIO region */
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| 317 | u8 _far *mmio; /* pointer to this adapter's MMIO region */
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| 318 |
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| 319 | u32 dma_buf_phys; /* physical address of DMA scratch buffer */
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| 320 | u8 _far *dma_buf[PORT_DMA_BUF_SEGS]; /* DMA scatch buffer */
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| 321 |
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| 322 | P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
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| 323 | } AD_INFO;
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| 324 |
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| 325 | /* ADD workspace in IORB (must not exceed 16 bytes) */
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| 326 | typedef struct {
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| 327 | void (*ppfunc)(IORBH _far *iorb); /* post-processing function */
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| 328 | void *buf; /* response buffer (e.g. for identify cmds) */
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| 329 | ULONG timer; /* timer for timeout procesing */
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| 330 | USHORT blocks; /* number of blocks to be transferred */
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| 331 | unsigned processing : 1; /* IORB is being processd */
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| 332 | unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
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| 333 | unsigned queued_hw : 1; /* IORB has been queued to hardware */
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| 334 | unsigned no_ncq : 1; /* must not use native command queuing */
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| 335 | unsigned is_ncq : 1; /* should use native command queueing */
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| 336 | unsigned complete : 1; /* IORB has completed processing */
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| 337 | unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
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| 338 | } ADD_WORKSPACE;
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| 339 |
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| 340 | /* -------------------------- function prototypes -------------------------- */
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| 341 |
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| 342 | /* init.asm */
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| 343 | extern u32 _cdecl readl (void _far *addr);
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| 344 | extern u32 _cdecl writel (void _far *addr, u32 val);
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| 345 | extern void _far * _cdecl memcpy (void _far *v_dst, void _far *v_src, int len);
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| 346 | extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
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| 347 | extern void _cdecl _far restart_hook (void);
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| 348 | extern void _cdecl _far reset_hook (void);
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| 349 | extern void _cdecl _far engine_hook (void);
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| 350 |
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| 351 | /* os2ahci.c */
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| 352 | extern USHORT init_drv (RPINITIN _far *req);
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| 353 | extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
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| 354 | extern void trigger_engine (void);
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| 355 | extern int trigger_engine_1 (void);
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| 356 | extern void send_iorb (IORBH _far *iorb);
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| 357 | extern void iocc_configuration (IORBH _far *iorb);
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| 358 | extern void iocc_device_control (IORBH _far *iorb);
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| 359 | extern void iocc_unit_control (IORBH _far *iorb);
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| 360 | extern void iocm_device_table (IORBH _far *iorb);
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| 361 | extern void iocc_geometry (IORBH _far *iorb);
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| 362 | extern void iocc_execute_io (IORBH _far *iorb);
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| 363 | extern void iocc_unit_status (IORBH _far *iorb);
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| 364 | extern void iocc_adapter_passthru (IORBH _far *iorb);
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| 365 | extern void iorb_queue_add (IORB_QUEUE _far *queue, IORBH _far *iorb);
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| 366 | extern int iorb_queue_del (IORB_QUEUE _far *queue, IORBH _far *iorb);
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| 367 | extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
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| 368 | extern void iorb_done (IORBH _far *iorb);
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| 369 | extern void iorb_requeue (IORBH _far *iorb);
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| 370 |
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| 371 | /* ahci.c */
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| 372 | extern int ahci_save_bios_config (AD_INFO *ai);
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| 373 | extern int ahci_restore_bios_config (AD_INFO *ai);
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| 374 | extern int ahci_restore_initial_config (AD_INFO *ai);
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| 375 | extern AHCI_PORT_CFG *ahci_save_port_config (AD_INFO *ai, int p);
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| 376 | extern void ahci_restore_port_config (AD_INFO *ai, int p,
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| 377 | AHCI_PORT_CFG *pc);
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| 378 | extern int ahci_enable_ahci (AD_INFO *ai);
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| 379 | extern int ahci_scan_ports (AD_INFO *ai);
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| 380 | extern int ahci_complete_init (AD_INFO *ai);
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| 381 | extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
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| 382 | extern int ahci_start_port (AD_INFO *ai, int p, int ei);
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| 383 | extern void ahci_start_fis_rx (AD_INFO *ai, int p);
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| 384 | extern void ahci_start_engine (AD_INFO *ai, int p);
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| 385 | extern int ahci_stop_port (AD_INFO *ai, int p);
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| 386 | extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
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| 387 | extern int ahci_stop_engine (AD_INFO *ai, int p);
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| 388 | extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
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| 389 | int (*func)(IORBH _far *, int));
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| 390 | extern void ahci_exec_polled_iorb (IORBH _far *iorb,
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| 391 | int (*func)(IORBH _far *, int),
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| 392 | ULONG timeout);
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| 393 | extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
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| 394 | int timeout, int cmd, ...);
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| 395 |
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| 396 | extern int ahci_intr (u16 irq);
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| 397 | extern void ahci_port_intr (AD_INFO *ai, int p);
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| 398 | extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
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| 399 |
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| 400 | extern void ahci_get_geometry (IORBH _far *iorb);
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| 401 | extern void ahci_unit_ready (IORBH _far *iorb);
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| 402 | extern void ahci_read (IORBH _far *iorb);
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| 403 | extern void ahci_verify (IORBH _far *iorb);
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| 404 | extern void ahci_write (IORBH _far *iorb);
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| 405 | extern void ahci_execute_cdb (IORBH _far *iorb);
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| 406 | extern void ahci_execute_ata (IORBH _far *iorb);
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| 407 |
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| 408 | /* libc.c */
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| 409 | extern void init_com1 (void);
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| 410 | extern int vsprintf (char _far *buf, const char *fmt, va_list va);
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| 411 | extern int sprintf (char _far *buf, const char *fmt, ...);
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| 412 | extern void vfprintf (const char *fmt, va_list va);
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| 413 | extern void _cdecl printf (const char *fmt, ...);
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| 414 | extern void cprintf (const char *fmt, ...);
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| 415 | extern void phex (const void _far *p, int len,
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| 416 | const char *fmt, ...);
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| 417 | extern size_t strlen (const char _far *s);
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| 418 | extern char _far *strcpy (char _far *dst, const char _far *src);
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| 419 | extern int memcmp (void _far *p1, void _far *p2, size_t len);
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| 420 | extern long strtol (const char _far *buf,
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| 421 | const char _far * _far *ep, int base);
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| 422 | extern void *malloc (size_t len);
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| 423 | extern void free (void *ptr);
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| 424 | extern void mdelay_cal (void);
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| 425 | extern void mdelay (u32 millies);
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| 426 | extern void msleep (u32 millies);
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| 427 | extern void panic (char *msg);
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| 428 | extern int disable (void);
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| 429 | extern void enable (void);
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| 430 |
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| 431 | /* pci.c */
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| 432 | extern int add_pci_id (u16 vendor, u16 device);
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| 433 | extern void scan_pci_bus (void);
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| 434 | extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
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| 435 | extern void pci_hack_virtualbox(void);
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| 436 |
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| 437 | /* ctxhook.c */
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| 438 | extern void _cdecl restart_ctxhook (ULONG parm);
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| 439 | extern void _cdecl reset_ctxhook (ULONG parm);
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| 440 | extern void _cdecl engine_ctxhook (ULONG parm);
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| 441 |
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| 442 | /* ---------------------------- global variables --------------------------- */
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| 443 |
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| 444 | extern char _cdecl end_of_data; /* label at the end of all data segments */
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| 445 | extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
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| 446 |
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| 447 | extern int debug; /* if != 0, print debug messages to COM1 */
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| 448 | extern int thorough_scan; /* if != 0, perform thorough PCI scan */
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| 449 | extern int init_reset; /* if != 0, reset ports during init */
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| 450 |
|
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| 451 | extern HDRIVER rm_drvh; /* resource manager driver handle */
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| 452 | extern USHORT add_handle; /* adapter device driver handle */
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| 453 | extern UCHAR timer_pool[]; /* timer pool */
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| 454 |
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| 455 | extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
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| 456 | extern ULONG drv_lock; /* driver-level spinlock */
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| 457 | extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
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| 458 | extern AD_INFO ad_infos[]; /* adapter information list */
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| 459 | extern int ad_info_cnt; /* number of entries in ad_infos[] */
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| 460 | extern int init_complete; /* if != 0, initialization has completed */
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|---|
| 461 |
|
|---|
| 462 | extern u16 com_base; /* debug COM port base address */
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|---|
| 463 |
|
|---|
| 464 | /* port restart context hook and input data */
|
|---|
| 465 | extern ULONG restart_ctxhook_h;
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|---|
| 466 | extern volatile u32 ports_to_restart[MAX_AD];
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|---|
| 467 |
|
|---|
| 468 | /* port reset context hook and input data */
|
|---|
| 469 | extern ULONG reset_ctxhook_h;
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|---|
| 470 | extern volatile u32 ports_to_reset[MAX_AD];
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|---|
| 471 | extern IORB_QUEUE abort_queue;
|
|---|
| 472 |
|
|---|
| 473 | /* trigger engine context hook and input data */
|
|---|
| 474 | extern ULONG engine_ctxhook_h;
|
|---|
| 475 |
|
|---|
| 476 | /* apapter/port-specific options saved when parsing the command line */
|
|---|
| 477 | extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
|
|---|
| 478 | extern u8 disable_ncq[MAX_AD][AHCI_MAX_PORTS];
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| 479 |
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