source: trunk/src/os2ahci/os2ahci.h@ 27

Last change on this file since 27 was 27, checked in by markus, 15 years ago

added bldlevel signature creation; set ignore patterns
File size: 22.0 KB
Line 
1/******************************************************************************
2 * os2ahci.h - main header file for os2ahci driver
3 *
4 * Copyright (c) 2010 Christian Mueller. Parts copied from/inspired by the
5 * Linux AHCI driver; those parts are (c) Linux AHCI/ATA maintainers
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/* ----------------------------- include files ----------------------------- */
23
24/* IMPORTANT NOTE: The DDK headers require tight structure packing and this
25 * is controlled via compiler parameters. Thus, all stuctures in os2ahci.sys
26 * are expected to be byte-aligned without the need of explicit pragma pack()
27 * directives. Where possible, the structures are layed out such that words
28 * and dwords are aligned at least on 2-byte boundaries.
29 */
30
31#define INCL_NOPMAPI
32#define INCL_DOSINFOSEG
33#define INCL_NO_SCB
34#define INCL_DOSERRORS
35#include <os2.h>
36#include <dos.h>
37#include <bseerr.h>
38#include <dskinit.h>
39#include <scb.h>
40
41#include <devhdr.h>
42#include <iorb.h>
43#include <strat2.h>
44#include <reqpkt.h>
45
46#ifdef __WATCOMC__
47/* include WATCOM specific DEVHELP stubs */
48#include <devhelp.h>
49#else
50#include <dhcalls.h>
51#endif
52
53#include <addcalls.h>
54#include <rmcalls.h>
55#include <devclass.h>
56#include <devcmd.h>
57#include <rmbase.h>
58
59#include "ahci.h"
60#include "version.h"
61
62/* -------------------------- macros and constants ------------------------- */
63
64#define MAX_AD 8 /* maximum number of adapters */
65
66/* Timer pool size. In theory, we need one timer per outstanding command plus
67 * a few miscellaneous timers but it's unlikely we'll ever have outstanding
68 * commands on all devices on all ports on all apapters -- this would be
69 * 8 * 32 * 32 = 8192 outstanding commands on a maximum of 8 * 32 * 15 = 3840
70 * devices and that's a bit of an exaggeration. It should be more than enough
71 * to have 128 timers.
72 */
73#define TIMER_COUNT 128
74#define TIMER_POOL_SIZE (sizeof(ADD_TIMER_POOL) + \
75 TIMER_COUNT * sizeof(ADD_TIMER_DATA))
76
77/* default command timeout (can be overwritten in the IORB) */
78#define DEFAULT_TIMEOUT 30000
79
80/* debug output macros */
81#define dprintf if (debug > 0) printf
82#define dphex if (debug > 0) phex
83#define ddprintf if (debug > 1) printf
84#define ddphex if (debug > 1) phex
85#define dddprintf if (debug > 2) printf
86#define dddphex if (debug > 2) phex
87
88/* adapter number from AD_INFO pointer; mainly for dprintf() purposes */
89#define ad_no(ai) (((u16) ai - (u16) ad_infos) / sizeof(*ai))
90
91/* Convert far function address into NPFN (the DDK needs this all over the
92 * place and just casting to NPFN will produce a "segment lost in conversion"
93 * warning. Since casting to a u32 is a bit nasty for function pointers and
94 * might have to be revised for different compilers, we'll use a central
95 * macro for this crap.
96 */
97#define mk_NPFN(func) (NPFN) (u32) (func)
98
99/* stdarg.h macros with explicit far pointers
100 *
101 * NOTE: The compiler pushes fixed arguments with 16 bits minimum, thus
102 * the last fixed argument (i.e. the one passed to va_start) must
103 * have at least 16 bits. Otherwise, the address calculation in
104 * va_start() will fail.
105 */
106typedef char _far *va_list;
107#define va_start(va, last) va = (va_list) (&last + 1)
108#define va_arg(va, type) ((type _far *) (va += sizeof(type)))[-1]
109#define va_end(va) va = 0
110
111/* ctype macros */
112#define isupper(ch) ((ch) >= 'A' && (ch) <= 'Z')
113#define tolower(ch) (isupper(ch) ? (ch) - ('a' - 'A') : (ch))
114
115/* stddef macros */
116#define offsetof(s, e) ((u16) &((s *) 0)->e)
117
118/* SMP spinlock compatibility macros for older DDKs using CLI/STI */
119#ifndef OS2AHCI_SMP
120#define DevHelp_CreateSpinLock(sph) *(sph) = 0
121#define DevHelp_FreeSpinLock(sph) 0
122
123#define DevHelp_AquireSpinLock(sph) if ((sph) != 0) \
124 panic("recursive spinlock"); \
125 (sph) = disable()
126
127#define DevHelp_ReleaseSpinLock(sph) if (sph) { \
128 (sph) = 0; \
129 enable(); \
130 }
131#endif
132
133/* shortcut macros */
134#define spin_lock(sl) DevHelp_AquireSpinLock(sl)
135#define spin_unlock(sl) DevHelp_ReleaseSpinLock(sl)
136
137/* Get AHCI port MMIO base from AD_INFO and port number. For the time being,
138 * MMIO addresses are assumed to be valid 16:16 pointers which implies
139 * that one GDT selector is allocated per adapter.
140 */
141#define port_base(ai, p) ((u8 _far *) (ai)->mmio + 0x100 + (p) * 0x80)
142
143/* Get address of port-specific DMA scratch buffer. The total size of all DMA
144 * buffers required for 32 ports exceeds 65536 bytes, thus we need multiple
145 * GDT selectors to access all port DMA scratch buffers and some logic to map
146 * a port number to the corresponding DMA scratch buffer address.
147 */
148#define PORT_DMA_BUFS_PER_SEG ((size_t) (65536UL / AHCI_PORT_PRIV_DMA_SZ))
149#define PORT_DMA_BUF_SEGS ((AHCI_MAX_PORTS + PORT_DMA_BUFS_PER_SEG - 1) \
150 / PORT_DMA_BUFS_PER_SEG)
151#define PORT_DMA_SEG_SIZE ((u32) PORT_DMA_BUFS_PER_SEG * \
152 (u32) AHCI_PORT_PRIV_DMA_SZ)
153
154#define port_dma_base(ai, p) \
155 ((AHCI_PORT_DMA _far *) ((ai)->dma_buf[(p) / PORT_DMA_BUFS_PER_SEG] + \
156 ((p) % PORT_DMA_BUFS_PER_SEG) * AHCI_PORT_PRIV_DMA_SZ))
157
158#define port_dma_base_phys(ai, p) \
159 ((ai)->dma_buf_phys + (u32) (p) * AHCI_PORT_PRIV_DMA_SZ)
160
161/* Convert an SATA adapter/port/device address into a 16-bit IORB unit handle
162 * (and the other way round). The mapping looks like this:
163 *
164 * mapping comment
165 * -----------------------------------------------------------------------
166 * 4 bits for the adapter current max is 8 adapters
167 * 4 bits for the port AHCI spec defines up to 32 ports
168 * 4 bits for the device SATA spec defines up to 15 devices behind PMP
169 */
170#define iorb_unit(a, p, d) ((((u16) (a) & 0x0fU) << 8) | \
171 (((u16) (p) & 0x0fU) << 4) | \
172 (((u16) (d) & 0x0fU)))
173#define iorb_unit_adapter(iorb) (((u16) (iorb)->UnitHandle >> 8) & 0x07U)
174#define iorb_unit_port(iorb) (((u16) (iorb)->UnitHandle >> 4) & 0x0fU)
175#define iorb_unit_device(iorb) ((u16) (iorb)->UnitHandle & 0x0fU)
176
177/*******************************************************************************
178 * Convenience macros for IORB processing functions
179 */
180/* is this IORB on driver or port level? */
181#define iorb_driver_level(iorb) ((iorb)->CommandCode == IOCC_CONFIGURATION)
182
183/* is this IORB to be inserted at the beginnig of the IORB queue? */
184#define iorb_priority(iorb) ((iorb)->CommandCode == IOCC_DEVICE_CONTROL && \
185 (iorb)->CommandModifier == IOCM_ABORT))
186
187/* access IORB ADD workspace */
188#define add_workspace(iorb) ((ADD_WORKSPACE _far *) &(iorb)->ADDWorkSpace)
189
190/* free resources in ADD workspace (timer, buffer, ...) */
191#define aws_free(aws) if ((aws)->timer != 0) { \
192 ADD_CancelTimer((aws)->timer); \
193 (aws)->timer = 0; \
194 } \
195 if ((aws)->buf != NULL) { \
196 free((aws)->buf); \
197 (aws)->buf = NULL; \
198 }
199
200/******************************************************************************
201 * PCI generic IDs and macros
202 */
203#define PCI_ANY_ID 0xffffU
204#define PCI_VDEVICE(vendor, device) PCI_VENDOR_ID_##vendor, (device), \
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0
206
207/******************************************************************************
208 * PCI vendor IDs for AHCI adapters known to this driver (copied from Linux
209 * pci_ids.h)
210 */
211#define PCI_VENDOR_ID_AL 0x10b9
212#define PCI_VENDOR_ID_AMD 0x1022
213#define PCI_VENDOR_ID_AT 0x1259
214#define PCI_VENDOR_ID_ATI 0x1002
215#define PCI_VENDOR_ID_ATT 0x11c1
216#define PCI_VENDOR_ID_CMD 0x1095
217#define PCI_VENDOR_ID_CT 0x102c
218#define PCI_VENDOR_ID_INTEL 0x8086
219#define PCI_VENDOR_ID_JMICRON 0x197B
220#define PCI_VENDOR_ID_MARVELL 0x11ab
221#define PCI_VENDOR_ID_NVIDIA 0x10de
222#define PCI_VENDOR_ID_PROMISE 0x105a
223#define PCI_VENDOR_ID_SI 0x1039
224#define PCI_VENDOR_ID_VIA 0x1106
225
226/******************************************************************************
227 * PCI class IDs we're interested in (copied from Linux pci_ids.h)
228 */
229#define PCI_BASE_CLASS_STORAGE 0x01
230#define PCI_CLASS_STORAGE_SCSI 0x0100
231#define PCI_CLASS_STORAGE_IDE 0x0101
232#define PCI_CLASS_STORAGE_FLOPPY 0x0102
233#define PCI_CLASS_STORAGE_IPI 0x0103
234#define PCI_CLASS_STORAGE_RAID 0x0104
235#define PCI_CLASS_STORAGE_SATA 0x0106
236#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
237#define PCI_CLASS_STORAGE_SAS 0x0107
238#define PCI_CLASS_STORAGE_OTHER 0x0180
239
240/* ------------------------ typedefs and structures ------------------------ */
241
242typedef unsigned int size_t;
243
244/* PCI device information structure; this is used both for scanning and for
245 * identification purposes in 'AD_INFO'; based on the Linux pci_device_id
246 * structure but hard-wired to use board_* constants for 'driver_data'
247 */
248typedef struct {
249 u16 vendor; /* PCI device vendor/manufacturer */
250 u16 device; /* PCI device ID inside vendor scope */
251 u16 subvendor; /* subsystem vendor (unused so far) */
252 u16 subdevice; /* subsystem device (unused so far) */
253 u32 class; /* PCI device class */
254 u32 class_mask; /* bits to match when scanning for 'class' */
255 u32 board; /* AHCI controller board type (board_* constants) */
256} PCI_ID;
257
258/* IORB queue; since IORB queues are updated at interrupt time, the
259 * corresponding pointers (not the data they point to) need to be volatile.
260 */
261typedef struct {
262 IORBH _far *volatile root; /* root of request list */
263 IORBH _far *volatile tail; /* tail of request list */
264} IORB_QUEUE;
265
266/* port information structure */
267typedef struct {
268 IORB_QUEUE iorb_queue; /* IORB queue for this port */
269 unsigned dev_max : 4; /* maximum device number on this port (0-15) */
270 unsigned cmd_slot : 5; /* current command slot index (using round-
271 * robin indexes to prevent starvation) */
272
273 volatile u32 ncq_cmds; /* bitmap for NCQ commands issued */
274 volatile u32 reg_cmds; /* bitmap for regular commands issued */
275
276 struct {
277 unsigned allocated : 1; /* if != 0, device is allocated */
278 unsigned present : 1; /* if != 0, device is present */
279 unsigned lba48 : 1; /* if != 0, device supports 48-bit LBA */
280 unsigned atapi : 1; /* if != 0, this is an ATAPI device */
281 unsigned atapi_16 : 1; /* if != 0, device suports 16-byte cmds */
282 unsigned removable : 1; /* if != 0, device has removable media */
283 unsigned dev_type : 5; /* device type (UIB_TYPE_* in iorb.h) */
284 unsigned ncq_max : 5; /* maximum tag number for queued commands */
285 UNITINFO _far *unit_info; /* pointer to modified unit info */
286 } devs[15];
287} P_INFO;
288
289/* adapter information structure */
290typedef struct {
291 PCI_ID *pci; /* pointer to corresponding PCI ID */
292
293 unsigned port_max : 5; /* maximum port number (0-31) */
294 unsigned cmd_max : 5; /* maximum cmd slot number (0-31) */
295 unsigned port_scan_done : 1; /* if != 0, port scan already done */
296 unsigned busy : 1; /* if != 0, adapter is busy */
297
298 u32 port_map; /* bitmap of active ports */
299
300 /* initial adapter configuration from BIOS */
301 u32 bios_config[HOST_CAP2 / sizeof(u32) + 1];
302
303 u32 cap; /* working copy of CAP register */
304 u32 cap2; /* working copy of CAP2 register */
305 u32 flags; /* adapter flags */
306
307 HRESOURCE rm_adh; /* resource handle for adapter */
308 HRESOURCE rm_mmio; /* resource handle for MMIO */
309 HRESOURCE rm_irq; /* resource handle for IRQ */
310
311 u8 bus; /* PCI bus number */
312 u8 dev_func; /* PCI device and function number */
313 u16 irq; /* interrupt number */
314
315 u32 mmio_phys; /* physical address of MMIO region */
316 u8 _far *mmio; /* pointer to this adapter's MMIO region */
317
318 u32 dma_buf_phys; /* physical address of DMA scratch buffer */
319 u8 _far *dma_buf[PORT_DMA_BUF_SEGS]; /* DMA scatch buffer */
320
321 P_INFO ports[AHCI_MAX_PORTS]; /* SATA ports on this adapter */
322} AD_INFO;
323
324/* ADD workspace in IORB (must not exceed 16 bytes) */
325typedef struct {
326 void (*ppfunc)(IORBH _far *iorb); /* post-processing function */
327 void *buf; /* response buffer (e.g. for identify cmds) */
328 ULONG timer; /* timer for timeout procesing */
329 USHORT blocks; /* number of blocks to be transferred */
330 unsigned processing : 1; /* IORB is being processd */
331 unsigned idempotent : 1; /* IORB is idempotent (can be retried) */
332 unsigned queued_hw : 1; /* IORB has been queued to hardware */
333 unsigned no_ncq : 1; /* must not use native command queuing */
334 unsigned is_ncq : 1; /* should use native command queueing */
335 unsigned complete : 1; /* IORB has completed processing */
336 unsigned cmd_slot : 5; /* AHCI command slot for this IORB */
337} ADD_WORKSPACE;
338
339/* -------------------------- function prototypes -------------------------- */
340
341/* init.asm */
342extern u32 _cdecl readl (void _far *addr);
343extern u32 _cdecl writel (void _far *addr, u32 val);
344extern void _far * _cdecl memcpy (void _far *v_dst, void _far *v_src, int len);
345extern void _far * _cdecl memset (void _far *p, int ch, size_t len);
346extern void _cdecl _far restart_hook (void);
347extern void _cdecl _far reset_hook (void);
348extern void _cdecl _far engine_hook (void);
349
350/* os2ahci.c */
351extern USHORT init_drv (RPINITIN _far *req);
352extern void _cdecl _far _loadds add_entry (IORBH _far *iorb);
353extern void trigger_engine (void);
354extern int trigger_engine_1 (void);
355extern void send_iorb (IORBH _far *iorb);
356extern void iocc_configuration (IORBH _far *iorb);
357extern void iocc_device_control (IORBH _far *iorb);
358extern void iocc_unit_control (IORBH _far *iorb);
359extern void iocm_device_table (IORBH _far *iorb);
360extern void iocc_geometry (IORBH _far *iorb);
361extern void iocc_execute_io (IORBH _far *iorb);
362extern void iocc_unit_status (IORBH _far *iorb);
363extern void iocc_adapter_passthru (IORBH _far *iorb);
364extern void iorb_queue_add (IORB_QUEUE _far *queue, IORBH _far *iorb);
365extern int iorb_queue_del (IORB_QUEUE _far *queue, IORBH _far *iorb);
366extern void iorb_seterr (IORBH _far *iorb, USHORT error_code);
367extern void iorb_done (IORBH _far *iorb);
368extern void iorb_requeue (IORBH _far *iorb);
369
370/* ahci.c */
371extern int ahci_save_bios_config (AD_INFO *ai);
372extern int ahci_restore_bios_config (AD_INFO *ai);
373extern int ahci_restore_initial_config (AD_INFO *ai);
374extern AHCI_PORT_CFG *ahci_save_port_config (AD_INFO *ai, int p);
375extern void ahci_restore_port_config (AD_INFO *ai, int p,
376 AHCI_PORT_CFG *pc);
377extern int ahci_enable_ahci (AD_INFO *ai);
378extern int ahci_scan_ports (AD_INFO *ai);
379extern int ahci_complete_init (AD_INFO *ai);
380extern int ahci_reset_port (AD_INFO *ai, int p, int ei);
381extern int ahci_start_port (AD_INFO *ai, int p, int ei);
382extern void ahci_start_fis_rx (AD_INFO *ai, int p);
383extern void ahci_start_engine (AD_INFO *ai, int p);
384extern int ahci_stop_port (AD_INFO *ai, int p);
385extern int ahci_stop_fis_rx (AD_INFO *ai, int p);
386extern int ahci_stop_engine (AD_INFO *ai, int p);
387extern void ahci_exec_iorb (IORBH _far *iorb, int ncq_capable,
388 int (*func)(IORBH _far *, int));
389extern void ahci_exec_polled_iorb (IORBH _far *iorb,
390 int (*func)(IORBH _far *, int),
391 ULONG timeout);
392extern int ahci_exec_polled_cmd (AD_INFO *ai, int p, int d,
393 int timeout, int cmd, ...);
394
395extern int ahci_intr (u16 irq);
396extern void ahci_port_intr (AD_INFO *ai, int p);
397extern void ahci_error_intr (AD_INFO *ai, int p, u32 irq_stat);
398
399extern void ahci_get_geometry (IORBH _far *iorb);
400extern void ahci_unit_ready (IORBH _far *iorb);
401extern void ahci_read (IORBH _far *iorb);
402extern void ahci_verify (IORBH _far *iorb);
403extern void ahci_write (IORBH _far *iorb);
404extern void ahci_execute_cdb (IORBH _far *iorb);
405extern void ahci_execute_ata (IORBH _far *iorb);
406
407/* libc.c */
408extern void init_com1 (void);
409extern int vsprintf (char _far *buf, const char *fmt, va_list va);
410extern int sprintf (char _far *buf, const char *fmt, ...);
411extern void vfprintf (const char *fmt, va_list va);
412extern void _cdecl printf (const char *fmt, ...);
413extern void cprintf (const char *fmt, ...);
414extern void phex (const void _far *p, int len,
415 const char *fmt, ...);
416extern size_t strlen (const char _far *s);
417extern char _far *strcpy (char _far *dst, const char _far *src);
418extern int memcmp (void _far *p1, void _far *p2, size_t len);
419extern long strtol (const char _far *buf,
420 const char _far * _far *ep, int base);
421extern void *malloc (size_t len);
422extern void free (void *ptr);
423extern void mdelay_cal (void);
424extern void mdelay (u32 millies);
425extern void msleep (u32 millies);
426extern void panic (char *msg);
427extern int disable (void);
428extern void enable (void);
429
430/* pci.c */
431extern int add_pci_id (u16 vendor, u16 device);
432extern void scan_pci_bus (void);
433extern int pci_enable_int (UCHAR bus, UCHAR dev_func);
434extern void pci_hack_virtualbox(void);
435
436/* ctxhook.c */
437extern void _cdecl restart_ctxhook (ULONG parm);
438extern void _cdecl reset_ctxhook (ULONG parm);
439extern void _cdecl engine_ctxhook (ULONG parm);
440
441/* ---------------------------- global variables --------------------------- */
442
443extern char _cdecl end_of_data; /* label at the end of all data segments */
444extern void _cdecl _near end_of_code(); /* label at the end of all code segments */
445
446extern int debug; /* if != 0, print debug messages to COM1 */
447extern int thorough_scan; /* if != 0, perform thorough PCI scan */
448extern int init_reset; /* if != 0, reset ports during init */
449
450extern HDRIVER rm_drvh; /* resource manager driver handle */
451extern USHORT add_handle; /* adapter device driver handle */
452extern UCHAR timer_pool[]; /* timer pool */
453
454extern PCI_ID pci_ids[]; /* SATA adapter PCI IDs */
455extern ULONG drv_lock; /* driver-level spinlock */
456extern IORB_QUEUE driver_queue; /* driver-level IORB queue */
457extern AD_INFO ad_infos[]; /* adapter information list */
458extern int ad_info_cnt; /* number of entries in ad_infos[] */
459extern int init_complete; /* if != 0, initialization has completed */
460
461extern u16 com_base; /* debug COM port base address */
462
463/* port restart context hook and input data */
464extern ULONG restart_ctxhook_h;
465extern volatile u32 ports_to_restart[MAX_AD];
466
467/* port reset context hook and input data */
468extern ULONG reset_ctxhook_h;
469extern volatile u32 ports_to_reset[MAX_AD];
470extern IORB_QUEUE abort_queue;
471
472/* trigger engine context hook and input data */
473extern ULONG engine_ctxhook_h;
474
475/* apapter/port-specific options saved when parsing the command line */
476extern u8 link_speed[MAX_AD][AHCI_MAX_PORTS];
477extern u8 disable_ncq[MAX_AD][AHCI_MAX_PORTS];
478
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