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DYNAJUST: an efficient automatic routing technique optimizing delay conditions

Authors:

Y. Fujihara,

Y. Sekiyama,

Y. Ishibashi,

M. YanakaAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 791 - 794

https://doi.org/10.1145/74382.74531

Published: 01 June 1989 Publication History

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Abstract

A new routing technique DYNAJUST, Dynamic Wire Length Adjustment, is described. It accurately realizes specified wire lengths to fulfill delay conditions. The implementation, based on the combination of shortest path algorithms, is proposed to achieve a high completion ratio in a short processing time. The technique is useful in practical situations where high accuracy is required of many nets.

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R. Linsker, "An I t er at ive-lmprovement Penal ty- Function-Driven Wire Routing System", IBM J. Res. Develop., Vol. 28, No. 5, pp. 613-624, 1984.

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Jing THong XXu JBao HCheng CGu J(2006)UTACOIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82335423:3(358-365)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.823354
Hong XXue THuang JCheng CKuh E(2006)TIGERIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66382216:11(1323-1331)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.663822
Prasitjutrakul SKubitz W(2006)A performance-driven global router for custom VLSI chip designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.14977511:8(1044-1051)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.149775
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Index Terms

DYNAJUST: an efficient automatic routing technique optimizing delay conditions
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design

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DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1989

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Jing THong XXu JBao HCheng CGu J(2006)UTACOIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82335423:3(358-365)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.823354
Hong XXue THuang JCheng CKuh E(2006)TIGERIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66382216:11(1323-1331)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.663822
Prasitjutrakul SKubitz W(2006)A performance-driven global router for custom VLSI chip designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.14977511:8(1044-1051)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.149775
Jing THong XBao HCai YXu JCheng CGu JYasuura H(2003)UTACOProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119956(834-839)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119956
Tong Jing Xianlong Hong Haiyun Bao Yici Cai Jingyu Xu Chungkuan Cheng Jun Gu (2003)UTACO: a unified timing and congestion optimizing algorithm for standard cell global routingProceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.10.1109/ASPDAC.2003.1195133(834-839)Online publication date: 2003
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Hong XJing TXu JBao HGu J(2003)CNBJournal of Computer Science and Technology10.1007/BF0294546118:6(732-738)Online publication date: 1-Nov-2003
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Tong Jing Xian-Long Hong Hai-Yun Bao Yi-Ci Cai Jing-Yu Xu Jun Gu (2002)A novel and efficient timing-driven global router for standard cell layout design based on critical network concept2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)10.1109/ISCAS.2002.1009803(I-165-I-168)Online publication date: 2002
https://doi.org/10.1109/ISCAS.2002.1009803
Huang JHong XCheng CKuh EDunlop A(1993)An efficient timing-driven global routing algorithmProceedings of the 30th international Design Automation Conference10.1145/157485.165063(596-600)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.165063
Terai HGoto FWakai KKozawa TEdagawa MHososaka SHashimoto MNewton A(1991)Basic concepts of timing-oriented design automation for high-performance mainframe computersProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127663(193-198)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127663
Sekiyama YFujihara YHayashi TSeki MKusuhara JIijima KTakakura MFukatani K(1991)Timing-oriented routers for PCB layout design of high-performance computers1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers10.1109/ICCAD.1991.185268(332-335)Online publication date: 1991
https://doi.org/10.1109/ICCAD.1991.185268
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An efficient multilayer MCM router based on four-via routing

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs

An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs

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An efficient multilayer MCM router based on four-via routing

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs

An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs

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