Article

HA²TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI

Authors:

Abhijit ChatterjeeAuthors Info & Claims

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

Pages 207 - 212

https://doi.org/10.1145/566408.566459

Published: 12 August 2002 Publication History

Abstract

This paper describes an efficient hierarchical design and optimization approach for ultra-low power CMOS logic circuits. We introduce the Hierarchical Activity-Aware Time Slack Distribution (HA²TSD) algorithm, which distributes the surplus time slack into the most power-hungry modules hierarchically. HA²TSD ensures that the total slack budget is maximal and the total power is near-minimal. Based on these time slacks, we have optimized technology parameters (supply voltage, threshold voltage, and device width) through a gate-level power optimizer and have tested the algorithm on a set of benchmark example circuits and building blocks of a synthesizable ARM core. The experimental results show that our strategy delivers over an order of magnitude savings in total (static and dynamic) power and reduces the optimization run-time significantly.

References

[1]

A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-power CMOS digital design," IEEE Journal of Solid-State Circuits, vol. 27, pp. 473--484, April 1992.

[2]

J.M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1996, pp 21-64,130--160.

Digital Library

[3]

R. Nair, C.L. Berman, P.S. hauge, and E.J. Yoffe, "Generation of performance constraints for layout," IEEE Transactions on Computer-Aided Design, pp.860--874, Aug. 1989.

Digital Library

[4]

T. Gao, P.M. Vaidya, and C.L. Liu,"A new performance driven placement algorithm," Proc. of ICCAD, pp. 44--47, 1991.

[5]

H. Youssef and E. Shragowitz, " Timing constraints for correct performance," Proc. of ICCAD, pp. 24--27, 1990.

[6]

P. Pant, V. De, and A. Chatterjee, "Simultaneous power Supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits," IEEE Trans. On VLSI Systems, vol. 6, no. 4, pp. 538--545, December 1998.

Digital Library

[7]

T. Sakurai and A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal Solid-State Circuits, vol. 25, pp. 584--594, Apr. 1990.

[8]

A. Bhavnagarwala, V. De, B. Austin, and J. Meindl, "Circuit techniques for CMOS low power GSI," in Proc. Int. Symp. Low Power Electron. Design: Dig. Tech. Papers, Aug. 1996, pp. 193--196.

Digital Library

[9]

A.Raghunathan, N.K. Jha, and S. Dey, High-Level Power Analysis and Optimization, Kluwer Academic Publishers, 1998, pp 1--25.

Digital Library

[10]

K. Roy and S.C. Prasad, Low-Power CMOS VLSI Circuit Design, John wiley & Sons, Inc., 2000, pp. 201--252.

[11]

T. Kobayashi and T. Sakurai, "Self adjusting threshold voltage scheme (SATS) for low voltage high speed operation," IEEE CICC, 1994, pp.271--277.

[12]

S. Mutoh, "1-V Power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, pp. 847-, April 1992.

[13]

A. Fariborz, "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," IEDM Tech., 1994, pp.809--818.

[14]

L. Wei, Z. Chen, and K.Roy, "Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs," IEEE SOI conference, 1997, pp. 82--83.

[15]

S.S. Sapatnekar, V.B. Rao, P.M. Vaidya, and S Kang, "An exact solution to the transistor sizing problem ofr CMOS circuits using convex optimization," IEEE Trans. On CAD of Integrated Circuits and Systems, vol. 12, no. 11, pp. 1621--1634, September 1993.

Digital Library

Cited By

Choi KChatterjee AVerbauwhede IRoh H(2003)UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSIProceedings of the 2003 international symposium on Low power electronics and design10.1145/871506.871527(72-77)Online publication date: 25-Aug-2003
https://dl.acm.org/doi/10.1145/871506.871527
Kyu-won Choi Chatterjee A(2003)UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSIProceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.10.1109/LPE.2003.1231838(72-77)Online publication date: 2003
https://doi.org/10.1109/LPE.2003.1231838

Index Terms

HA²TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

Recommendations

UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI
ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

In this paper, we propose an efficient approach to minimize total power (switching, short-circuit, and leakage power) without performance loss for ultra-low power CMOS circuits in nanometer technologies. We present a framework for combining supply/...
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives ...
Analysis of energy reduction on dynamic voltage scaling-enabled systems

Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency, based on the computation load, to provide the desired performance with the minimal amount of energy consumption. It has been demonstrated as one of the most ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

August 2002

342 pages

ISBN:1581134754

DOI:10.1145/566408

General Chairs:
Vivek De
Intel Corporation
,
Mary Jane Irwin
Penn State University
,
Program Chairs:
Ingrid Verbauwhede
University of California, Los Angeles
,
Christian Piguet
CSEM

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 August 2002

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISLPED02

Sponsor:

ISLPED02: International Symposium on Power Design and Electronics

August 12 - 14, 2002

California, Monterey, USA

Acceptance Rates

ISLPED '02 Paper Acceptance Rate 40 of 162 submissions, 25%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
13
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Choi KChatterjee AVerbauwhede IRoh H(2003)UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSIProceedings of the 2003 international symposium on Low power electronics and design10.1145/871506.871527(72-77)Online publication date: 25-Aug-2003
https://dl.acm.org/doi/10.1145/871506.871527
Kyu-won Choi Chatterjee A(2003)UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSIProceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.10.1109/LPE.2003.1231838(72-77)Online publication date: 2003
https://doi.org/10.1109/LPE.2003.1231838

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents