research-article

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits

Authors:

Samah Mohamed Saeed,

Nithin Mahendran,

Alwin Zulehner,

Ramesh KarriAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 15, Issue 3

Article No.: 23, Pages 1 - 17

https://doi.org/10.1145/3289392

Published: 29 April 2019 Publication History

Abstract

Reversible circuits employ a computational paradigm that is beneficial for several applications, including the design of encoding and decoding devices, low-power design, and emerging applications in quantum computation. However, similarly to conventional logic, reversible circuits are expected to be subject to Intellectual Property/Integrated Circuit piracy. To counteract such attacks, an understanding of how to identify the target function from a reversible circuit is a crucial first step. In contrast to conventional logic, the target function is (implicitly or explicitly) embedded into the reversible circuit. Numerous synthesis approaches have been proposed for this embedding task. To recover the target function embedded in a reversible circuit, one needs to know what synthesis approach has been used to embed the circuit.

We propose a machine-learning-based scheme to determine the used reversible synthesis approach based on the telltale signs it leaves in the synthesized reversible circuit. We study the impact of optimizing the synthesis approaches on the telltale signs that they leave. Our analysis shows that the synthesis approaches can be determined in the vast majority of cases even if optimized versions of the synthesis approaches are used.

References

[1]

M. P. Frank and M. Ottavi. 2019. Special issue: Design of reversible computing systems. In IEEE Transactions on Emerging Topics in Computing.

[2]

L. Amaru, P. E. Gaillardon, R. Wille, and G. De Micheli. 2016. Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. In Proceedings of the Design, Automation Test in Europe Conference Exhibition. 175--180.

Digital Library

[3]

W. C. Athas and L. J. Svensson. 1994. Reversible logic issues in adiabatic CMOS. In Proceedings of the Workshop on Physics and Computation. 111--118.

[4]

C. H. Bennett. 1973. Logical reversibility of computation. IBM J. Res. Dev 17, 6 (Nov. 1973), 525--532.

Digital Library

[5]

A. Berut, A. Arakelyan, A. Petrosyan, S. Ciliberto, R. Dillenschneider, and E. Lutz. 2012. Experimental verification of Landauer’s principle linking information and thermodynamics. Nature 483 (2012), 187--189.

[6]

R. E. Bryant. 1986. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput. 35, 8 (Aug. 1986), 677--691.

Digital Library

[7]

L. W. Chow, J. P. Baukus, B. J. Wang, and R. P. Cocchi. 2012. Camouflaging a standard cell based integrated circuit. Google Patents.

[8]

N. Cristianini and J. Shawe-Taylor. 2000. An Introduction to Support Vector Machines: And Other Kernel-based Learning Methods. Cambridge University Press.

Digital Library

[9]

R. Cuykendall and D. R. Andersen. 1987. Reversible optical computing circuits. Opt. Lett. 12, 7 (1987), 542--544.

[10]

S. J. Devitt and I. Lanese (Eds.). 2016. In Proceedings of the 8th International Conference on Reversible Computation (RC’16). Lecture Notes in Computer Science, Vol. 9720. Springer.

[11]

K. Fazel, M. A. Thornton, and J. E. Rice. 2007. ESOP-based Toffoli gate cascade generation. In Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. 206--209.

[12]

M. P. Frank. 2017. The future of computing depends on making it reversible. IEEE Spectrum (2017).

[13]

D. A. Freedman. 2009. Statistical Models: Theory and Practice. Cambridge University Press.

[14]

T. K. Ho. 1995. Proceedings of international conference on document analysis and recognition. In Proceedings of the International Conference on Document Analysis and Recognition (ICDAR’95), Vol. 1. 278--282.

[15]

T. Hogg, M. S. Moses, and D. G. Allis. 2017. Mechanical computing systems using only links and rotary joints. Molec. Syst. Des. Eng. 2, 3 (2017), 235--252.

[16]

R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor. 2010. Trustworthy hardware: Identifying and classifying hardware trojans. Computer 43, 10 (Oct. 2010), 39--46.

Digital Library

[17]

R. Landauer. 1961. Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 3 (1961), 183--191.

Digital Library

[18]

D. Maslov and G. W. Dueck. 2004. Reversible cascades with minimal garbage. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 23, 11 (Nov. 2004), 1497--1509.

Digital Library

[19]

M. El Massad, J. Zhang, S. Garg, and M. V. Tripunitara. 2017. Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism. In arXiv:1703.10187.

[20]

D. M. Miller, D. Maslov, and G. W. Dueck. 2003. A transformation based algorithm for reversible logic synthesis. In Proceedings of the ACM/ESDA/IEEE Design Automation Conference. 318--323.

Digital Library

[21]

M. Nielsen and I. Chuang. 2000. Quantum Computation and Quantum Information. Cambridge University Press.

Digital Library

[22]

P. Niemann, R. Wille, D. M. Miller, M. A. Thornton, and R. Drechsler. 2016. QMDDs: Efficient quantum function representation and manipulation. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 35, 1 (2016), 86--99.

Digital Library

[23]

M. Pecht and S. Tiku. 2006. Bogus: Electronic manufacturing and consumers confront a rising tide of counterfeit electronics. IEEE Spectrum 43, 5 (2006), 37--46.

Digital Library

[24]

I. Phillips and H. Rahaman (Eds.). 2017. In Proceedings of the 9th International Conference on Reversible Computation (RC’17). Lecture Notes in Computer Science, Vol. 10301. Springer.

[25]

J. R. Quinlan. 1986. Induction of decision trees. Mach. Learn. 1, 1 (Mar. 1986), 81--106.

Digital Library

[26]

Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, and Ramesh Karri. 2013. Security analysis of integrated circuit camouflaging. In Proceedings of the ACM SIGSAC Conference on Computer 8 Communications Security. 709--720.

Digital Library

[27]

J. Rajendran, O. Sinanoglu, and R. Karri. 2013. Is split manufacturing secure? In Proceedings of the Design, Automation Test in Europe Conference Exhibition. 1259--1264.

Digital Library

[28]

J. Rajendran, O. Sinanoglu, and R. Karri. 2013. VLSI testing based security metric for IC camouflaging. In Proceedings of the IEEE International Test Conference. 1--4.

[29]

J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri. 2015. Fault analysis-based logic encryption. IEEE Trans. Comput. 64, 2 (2015), 410--424.

Digital Library

[30]

A. Rauchenecker, T. Ostermann, and R. Wille. 2017. Exploiting reversible logic design for implementing adiabatic circuit. In Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems.

[31]

J. A. Roy, F. Koushanfar, and I. L. Markov. 2010. Ending piracy of integrated circuits. Computer 43, 10 (2010), 30--38.

Digital Library

[32]

S. M. Saeed, X. Cui, R. Wille, A. Zulehner, K. Wu, R. Drechsler, and R. Karri. 2017. Towards reverse engineering reversible logic. CoRR abs/1704.08397 (2017).

[33]

S. M. Saeed, X. Cui, R. Wille, A. Zulehner, K. Wu, R. Drechsler, and R. Karri. 2018. IC/IP piracy assessment of reversible logic. In Proceedings of the International Conference on Computer-Aided Design.

Digital Library

[34]

S. M. Saeed, N. Mahendran, A. Zulehner, R. Wille, and R. Karri. 2017. Identifying reversible circuit synthesis approaches to enable IP piracy attacks. In Proceedings of the IEEE International Conference on Computer Design. 537--540.

[35]

Y. Sanaee and G. W. Dueck. 2009. Generating Toffoli networks from ESOP expressions. In Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. IEEE, 715--719.

[36]

P. W. Shor. 1997. Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer. SIAM J. Comput. 26, 5 (Oct. 1997), 1484--1509.

Digital Library

[37]

M. Soeken, G. W. Dueck, M. M. Rahman, and D. M. Miller. 2016. An extension of transformation-based reversible and quantum circuit synthesis. In Proceedings of the IEEE International Symposium on Circuits and Systems. 2290--2293.

[38]

M. Soeken, R. Wille, C. Hilken, N. Przigoda, and R. Drechsler. 2012. Synthesis of reversible circuits with minimal lines for large functions. In Proceedings of the Asia and South Pacific Design Automation Conference. 85--92.

[39]

R. Wille and R. Drechsler. 2009. BDD-based synthesis of reversible logic for large functions. In Proceedings of the ACM/ESDA/IEEE Design Automation Conference. 270--275.

Digital Library

[40]

R. Wille and R. Drechsler. 2010. Effect of BDD optimization on synthesis of reversible and quantum logic. Electr. Not. Theor. Comput. Sci. 253, 1 (Mar. 2010), 57--70.

Digital Library

[41]

R. Wille, R. Drechsler, C. Osewold, and A. García Ortiz. 2012. Automatic design of low-power encoders using reversible circuit synthesis. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’12). 1036--1041.

Digital Library

[42]

R. Wille, D. Grosse, L. Teuber, G. W. Dueck, and R. Drechsler. 2008. RevLib: An online resource for reversible functions and reversible circuits. In Proceedings of the International Symposium on Multiple Valued Logic. 220--225.

Digital Library

[43]

R. Wille, O. Keszocze, S. Hillmich, M. Walter, and A. García Ortiz. 2016. Synthesis of approximate coders for on-chip interconnects using reversible logic. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’16). 1140--1143.

Digital Library

[44]

B. Wire. 2014. Research and markets: Outsourced semiconductor assembly and test market (OSAT) trends. Retrieved from http://www.businesswire.com/news/home/20140324005628/en/Research-Markets-Outsourced-Semiconductor-Assembly-Test-Market.

[45]

W. Wustmann and K. Osborn. 2017. Reversible fluxon logic: Topological particles allow gates beyond the standard adiabatic limit. In arXiv:1711.04339.

[46]

M. Yasin, J. J. Rajendran, O. Sinanoglu, and R. Karri. 2016. On improving the security of logic locking. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 35, 9 (2016), 1411--1424.

Digital Library

[47]

M. Yasin, S. M. Saeed, J. Rajendran, and O. Sinanoglu. 2016. Activation of logic encrypted chips: Pre-test or post-test? In Proceedings of the Design, Automation and Test in Europe Conference Exhibition. 139--144.

Digital Library

[48]

A. Zulehner, M. Frank, and R. Wille. 2019. Design automation for adiabatic circuits. In Proceedings of the Asia and South Pacific Design Automation Conference.

Digital Library

[49]

A. Zulehner and R. Wille. 2017. Improving synthesis of reversible circuits: Exploiting redundancies in paths and nodes of QMDDs. In Proceedings of the International Conference on Reversible Computation. Springer, 232--247.

[50]

A. Zulehner and R. Wille. 2017. Make it reversible: Efficient embedding of non-reversible functions. In Proceedings of the Design, Automation and Test in Europe Conference Exhibition.

Digital Library

[51]

A. Zulehner and R. Wille. 2017. Taking one-to-one mappings for granted: Advanced logic design of encoder circuits. In Proceedings of the Design, Automation and Test in Europe Conference Exhibition.

Digital Library

Cited By

Chaurasia RSengupta A(2023)Retinal Biometric for Securing JPEG-Codec Hardware IP Core for CE SystemsIEEE Transactions on Consumer Electronics10.1109/TCE.2023.326466969:3(441-457)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TCE.2023.3264669
Saravanan VSaeed S(2022)Pauli Error Propagation-Based Gate Rescheduling for Quantum Circuit Error MitigationIEEE Transactions on Quantum Engineering10.1109/TQE.2022.31611973(1-11)Online publication date: 2022
https://doi.org/10.1109/TQE.2022.3161197
Saeed SWille RKarri R(2019)Locking the Design of Building Blocks for Quantum CircuitsACM Transactions on Embedded Computing Systems10.1145/335818418:5s(1-15)Online publication date: 7-Oct-2019
https://dl.acm.org/doi/10.1145/3358184
Show More Cited By

Index Terms

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits
1. Hardware
  1. Emerging technologies
    1. Reversible logic

Recommendations

Synthesis of reversible PLA using products sharing

Reversible logic is a computing design, where the ideal implementation would produce zero entropy gain. This unique feature causes prominent use of reversible computing. At the same time, more integration capability and regular structure for ...
Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares

In this paper, a synthesis method for combinational multiple-valued reversible logic (MVRL) circuits is proposed. This algorithm can use the don't care values in the synthesis process to obtain the optimal circuit with respect to quantum cost. The ...
Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new ...

Comments

Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 15, Issue 3

July 2019

160 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3327966

Editor:
Yuan Xie
University of California, Santa Barbara, USA

Issue’s Table of Contents

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 April 2019

Accepted: 01 October 2018

Revised: 01 September 2018

Received: 01 March 2018

Published in JETC Volume 15, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

EU COST Action
NYU/NYU-AD CCS

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
192
Total Downloads

Downloads (Last 12 months)8
Downloads (Last 6 weeks)1

Reflects downloads up to 15 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chaurasia RSengupta A(2023)Retinal Biometric for Securing JPEG-Codec Hardware IP Core for CE SystemsIEEE Transactions on Consumer Electronics10.1109/TCE.2023.326466969:3(441-457)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TCE.2023.3264669
Saravanan VSaeed S(2022)Pauli Error Propagation-Based Gate Rescheduling for Quantum Circuit Error MitigationIEEE Transactions on Quantum Engineering10.1109/TQE.2022.31611973(1-11)Online publication date: 2022
https://doi.org/10.1109/TQE.2022.3161197
Saeed SWille RKarri R(2019)Locking the Design of Building Blocks for Quantum CircuitsACM Transactions on Embedded Computing Systems10.1145/335818418:5s(1-15)Online publication date: 7-Oct-2019
https://dl.acm.org/doi/10.1145/3358184
Saeed SZulehner AWille RDrechsler RKarri R(2019)Reversible Circuits: IC/IP Piracy Attacks and CountermeasuresIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.293446527:11(2523-2535)Online publication date: 23-Oct-2019
https://dl.acm.org/doi/10.1109/TVLSI.2019.2934465

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

HTML Format

View this article in HTML Format.

Media

Figures

Other

Tables

View Issue’s Table of Contents