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Resilience analysis: tightening the CRPD bound for set-associative caches

Published: 13 April 2010 Publication History

Abstract

In preemptive real-time systems, scheduling analyses need - in addition to the worst-case execution time - the context-switch cost. In case of preemption, the preempted and the preempting task may interfere on the cache memory.
This interference leads to additional cache misses in the preempted task. The delay due to these cache misses is referred to as the cache-related preemption delay~(CRPD), which constitutes the major part of the context-switch cost.
In this paper, we present a new approach to compute tight bounds on the CRPD for LRU set-associative caches, based on analyses of both the preempted and the preempting task. Previous approaches analyzing both the preempted and the preempting task were either imprecise or unsound.
As the basis of our approach we introduce the notion of resilience: The resilience of a memory block of the preempted task is the maximal number of memory accesses a preempting task could perform without causing an additional miss to this block. By computing lower bounds on the resilience of blocks and an upper bound on the number of accesses by a preempting task, one can guarantee that some blocks may not contribute to the CRPD. The CRPD analysis based on resilience considerably outperforms previous approaches.

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  • (2022)Improving CRPD analysis for EDF schedulingProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507027(481-490)Online publication date: 25-Apr-2022
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Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 45, Issue 4
LCTES '10
April 2010
170 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1755951
Issue’s Table of Contents
  • cover image ACM Conferences
    LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
    April 2010
    184 pages
    ISBN:9781605589534
    DOI:10.1145/1755888
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 13 April 2010
Published in SIGPLAN Volume 45, Issue 4

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Author Tags

  1. cache-related preemption delay
  2. lru caches
  3. timing analysis

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Cited By

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  • (2022)Cache-aware Schedulability Analysis of PREM Compliant Tasks2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774670(1269-1274)Online publication date: 14-Mar-2022
  • (2022)Improving CRPD analysis for EDF schedulingProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507027(481-490)Online publication date: 25-Apr-2022
  • (2022)Profile-driven memory bandwidth management for accelerators and CPUs in QoS-enabled platformsReal-Time Systems10.1007/s11241-022-09382-x58:3(235-274)Online publication date: 1-Sep-2022
  • (2022)An Investigation of Microarchitectural Cache-Based Side-Channel Attacks from a Digital Forensic Perspective: Methods of Exploits and CountermeasuresArtificial Intelligence in Cyber Security: Impact and Implications10.1007/978-3-030-88040-8_11(281-306)Online publication date: 1-Jan-2022
  • (2020)Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data CachesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.293780739:10(2333-2346)Online publication date: Oct-2020
  • (2020)E-WarP: A System-wide Framework for Memory Bandwidth Profiling and Management2020 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS49844.2020.00039(345-357)Online publication date: Dec-2020
  • (2020)Cache-aware response time analysis for real-time tasks with fixed preemption points2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.00-19(30-42)Online publication date: Apr-2020
  • (2020)Resource-efficient cyber-physical systems design: A surveyMicroprocessors and Microsystems10.1016/j.micpro.2020.10318377(103183)Online publication date: Sep-2020
  • (2015)Towards compositionality in execution time analysisACM SIGBED Review10.1145/2752801.275280512:1(28-36)Online publication date: 27-Mar-2015
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