article

Voltage scheduling under unpredictabilities: a risk management paradigm

Authors:

Azadeh Davoodi,

Ankur SrivastavaAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10, Issue 2

Pages 354 - 368

https://doi.org/10.1145/1059876.1059884

Published: 01 April 2005 Publication History

Abstract

This article addresses the problem of voltage scheduling in unpredictable situations. The voltage scheduling problem assigns voltages to operations such that the power is minimized under a clock delay constraint. In the presence of unpredictabilities, meeting the clock latency constraint cannot be guaranteed. This article proposes a novel risk management based technique to solve this problem. Here, the risk management paradigm assigns a quantified value to the amount of risk the designer is willing to take on the clock cycle constraint. The algorithm then assigns voltages in order to meet the expected value of clock cycle constraint while keeping the maximum delay within the specified “risk” and minimizing the power. The proposed algorithm is based on dynamic programming and is optimal for trees. Experimental results show that the traditional voltage scheduling approach is incapable of handling unpredictabilities. Our approach is capable of generating an effective tradeoff between power and “risk”: the more the risk, the less the power. The results show that a small increase in design risk positively affects the power dissipation.

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Cited By

Wong JDavoodi AKhandelwal VSrivastava APotkonjak M(2006)A statistical methodology for wire-length predictionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85588525:7(1327-1336)Online publication date: 1-Jul-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.855885
Davoodi ASrivastava A(2005)Power-driven simultaneous resource binding and floorplanningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.85361813:8(934-942)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.853618
Davoodi ASrivastava A(2005)Simultaneous floorplanning and resource binding: a probabilistic approachProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466218(517-522)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466218
Show More Cited By

Index Terms

Voltage scheduling under unpredictabilities: a risk management paradigm
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
    2. Logic synthesis
      1. Circuit optimization

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 10, Issue 2

April 2005

244 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1059876

Issue’s Table of Contents

Copyright © 2005 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2005

Published in TODAES Volume 10, Issue 2

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Cited By

Wong JDavoodi AKhandelwal VSrivastava APotkonjak M(2006)A statistical methodology for wire-length predictionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85588525:7(1327-1336)Online publication date: 1-Jul-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.855885
Davoodi ASrivastava A(2005)Power-driven simultaneous resource binding and floorplanningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.85361813:8(934-942)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.853618
Davoodi ASrivastava A(2005)Simultaneous floorplanning and resource binding: a probabilistic approachProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466218(517-522)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466218
Davoodi AKhandelwal VSrivastava A(2004)Empirical models for net-length probability distribution and applicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.83423512:10(1066-1075)Online publication date: 1-Oct-2004
https://dl.acm.org/doi/10.1109/TVLSI.2004.834235

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