Routing algorithms: enhancing routability & enabling ECO (abstract only)
Page 266
Abstract
The routing channels of today's FPGAs consist of wire segments of various types. This routing architecture makes us capable of exploiting some new techniques to enhance the routability of net segments in channels in order to support engineering change order (ECO). In this paper we present an optimal greedy algorithm to switch the track, which each net segment is assigned to, in order to enhance the routability of newly added nets for enabling ECO. We used the routing architecture of Virtex II FPGAs from Xilinx as our target routing architecture and integrated our algorithm into VPR FPGA routing tool. The experimental result show that the algorithm reduces the number of Tracks by 9% in average. It allows 28.4% more rerouting than the existing router of VPR tool, which is based on Dijkestra's maze router algorithm.
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February 2005
288 pages
Copyright © 2005 ACM.
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 20 February 2005
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FPGA05: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005
February 20 - 22, 2005
California, Monterey, USA
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Overall Acceptance Rate 125 of 627 submissions, 20%
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