We present fast techniques for creating the netlist underlying a hierarchical schematic design. The methods can be used either for creating the netlist as a data structure for further online processing or for creating the netlist as a file for use with ...

A complete datamodel for an integrated VLSI design system is developed in a stepwise manner. This datamodel introduces a unified view of all design domains and hierarchy levels that result in a considerable simplification of the communication among the ...

The Cadlab Work Station Design Environment is an integrated CAD environment. Like other integrated CAD environments, it consists of a single design management sub-environment and a set of application sub-environments integrated into a CAD framework. ...

This paper describes the work to unify a data exchange environment based on EDIF. Concepts of common specification, common data structure, and common EDIF reader/writer to synchronize the interpretations of EDIF syntax and semantics in an EDIF-based ...

We present in this paper a new approach to the two-layer via minimization problem. Our approach is to systematically eliminate vias by modifying the routing layout. We have implemented our algorithm and applied it to benchmark routing layouts published ...

A new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algorithm minimizes the total area and simultaneously maximizes the performance by reducing the critical area which can potentially be the source of logical ...

A new routing technique DYNAJUST, Dynamic Wire Length Adjustment, is described. It accurately realizes specified wire lengths to fulfill delay conditions. The implementation, based on the combination of shortest path algorithms, is proposed to achieve a ...

This paper deals with the problem of sizing integrated-circuit power and ground distribution systems external to the logic modules constituting an integrated circuit. Several constraints associated with the reliability of the power and ground ...

This paper presents a fast and efficient method for sizing power/ground networks. No restrictions on network topology or number of supplying pads are imposed. Wire widths are calculated such that the weighted area of wire segments is minimized while ...

A parallel algorithm for symbolic compaction of two layered channels has been developed and implemented on the Connection Machine. It allows fast channel compaction with very little wasted space.

In this paper, we compare the performance of two popular graph bisection algorithms. We also present an empirical study of a new heuristic, first proposed in [B87], that dramatically improves the performance of these bisection algorithms on graphs with ...

We introduce a generalization of the min-cut partitioning problem, called Min-Cost Tree Partitioning, in which the nodes of an hypergraph G are to be mapped on to the vertices of a tree structure T, and the cost function to be minimized is the cost of ...

In the design of application specific integrated circuits (ASIC), it is often required to partition a logic complex into smaller subcomplexes satisfying a number of constraints. Due to the complexity of the problem, most existing algorithms try to ...

We present a new Ο(n²) heuristic for hypergraph min-cut bipartitioning, an important problem in circuit placement. Fastest previous methods for this problem are Ο(n² log n). Our approach is based on the intersection graph G dual to the input hypergraph. ...

This paper describes features of EXEL, a graphic language that gives the designer control over the behavioral synthesis process. Control is achieved by allowing the designer to partially specify the structural design into which the description is going ...

An automated system for creating and managing VHDL design units is described in this paper. This system helps the hardware designer to learn the syntax of the VHSIC Hardware Description Language (VHDL) and to produce code which can be used for ...

This paper presents a technique for describing the behavior of transmission gates (TGs) in VHDL. The concept of virtual signal is introduced into the TG's data structure to represent the nature of the connection. The model's semantics are coded in three ...

This paper reports on a research project to design a system for automatically interpreting English specifications of digital systems in terms of design representation formalisms currently employed in CAD systems. The necessary processes involve the ...

We propose a new approach to define a formal semantics of a hardware design language (HDL) in Japanese LSI design language standardization project. Our approach is to separate the definition of semantics from simulators. Since the semantics includes ...