Xiaoqing Xu

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David Zhigang O Pan (19)
Bei Yu (14)
Yibo Lin (11)
Jhih Rong Gao (5)
Meng Li (5)
Chelun Hsu (4)
Brian T Cline (3)
Wuxi Li (3)
Charles J Alpert (2)
David Z Pan (2)
Greg Yeric (2)
Jiaojiao Ou (2)
Ru Huang (2)
Runsheng Wang (2)
Shaofeng Guo (2)
Vinicius S Livramento (2)
Zhuo (Robert) Li (2)
Lars W Liebmann (1)
Shyam Ramji (1)

Publication

Journal/Magazine Names

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (5)
ACM Transactions on Design Automation of Electronic Systems (1)

Proceedings/Book Names

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (2)
ASPDAC '18: Proceedings of the 23rd Asia and South Pacific Design Automation Conference (2)
DAC '15: Proceedings of the 52nd Annual Design Automation Conference (2)
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design (2)
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (1)
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation Conference (1)
DAC '14: Proceedings of the 51st Annual Design Automation Conference (1)
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017 (1)
DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in Europe (1)
ICCAD '13: Proceedings of the International Conference on Computer-Aided Design (1)
ISPD '14: Proceedings of the 2014 on International symposium on physical design (1)
ISPD '16: Proceedings of the 2016 on International Symposium on Physical Design (1)

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Proceedings (16)
Other periodicals (5)
Journals (1)

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IEEE Press (12)
Association for Computing Machinery (9)
EDA Consortium (1)

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TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design
- Chen-Hao Hsu
  ECE Department, The University of Texas at Austin, Austin, TX, USA
  ,
- Xiaoqing Xu
  X, the moonshot factory, Mountain View, CA, USA
  ,
- Hao Chen
  X, the moonshot factory, Mountain View, CA, USA
  ,
- Dino Ruic
  X, the moonshot factory, Mountain View, CA, USA
  ,
- David Z. Pan
  ECE Department, The University of Texas at Austin, Austin, TX, USA
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation Conference•January 2024, pp 312-318• https://doi.org/10.1109/ASP-DAC58780.2024.10473978

The standard-cell methodology is widely adopted in the VLSI design flow due to its scalability, reusability, and compatibility with electronic design automation (EDA) tools. However, the fixed positions and confinement of PMOS and NMOS transistors within ...
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Self-aligned double-patterning aware legalization
- Hua Xiang
  IBM T.J. Watson Research Center
  ,
- Gi-Joon Nam
  IBM T.J. Watson Research Center
  ,
- Gustavo Tellez
  IBM T.J. Watson Research Center
  ,
- Shyam Ramji
  IBM T.J. Watson Research Center
  ,
- Xiaoqing Xu
  Univ of Texas at Austin
DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in Europe•March 2020, pp 1145-1150

Double patterning is a widely used technique for sub-22nm. Among various double patterning techniques, Self-Aligned Double Patterning (SADP) is a promising technique for good mask overlay control. Based on SADP, a new set of standard cells (T-cells) are ...
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A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion
- Meng Li
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Bei Yu
  Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong
  ,
- Yibo Lin
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Xiaoqing Xu
  ARM Inc., Austin, TX, USA
  ,
- Wuxi Li
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- David Z. Pan
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 38, Issue 9•Sept. 2019, pp 1585-1598 • https://doi.org/10.1109/TCAD.2018.2859402
Trojans and backdoors inserted by untrusted foundries have become serious threats to hardware security. Split manufacturing is proposed to hide important circuit structures and prevent Trojan insertion by fabricating partial interconnections in trusted ...
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A practical split manufacturing framework for trojan prevention via simultaneous wire lifting and cell insertion
- Meng Li
  University of Texas at Austin
  ,
- Bei Yu
  The Chinese University of Hong Kong, NT, Hong Kong
  ,
- Yibo Lin
  University of Texas at Austin
  ,
- Xiaoqing Xu
  University of Texas at Austin
  ,
- Wuxi Li
  University of Texas at Austin
  ,
- David Z. Pan
  University of Texas at Austin
ASPDAC '18: Proceedings of the 23rd Asia and South Pacific Design Automation Conference•January 2018, pp 265-270

Trojans and backdoors inserted by untrusted foundries have become serious threats to hardware security. Split manufacturing is proposed to prevent Trojan insertion proactively. Existing methods depend on wire lifting to hide partial circuit ...
3Citation
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research-article
Layout-dependent aging mitigation for critical path timing
- Che-Lun Hsu
  University of Texas at Austin
  ,
- Shaofeng Guo
  Peking University, Haidian, Beijing, China
  ,
- Yibo Lin
  University of Texas at Austin
  ,
- Xiaoqing Xu
  University of Texas at Austin
  ,
- Meng Li
  University of Texas at Austin
  ,
- Runsheng Wang
  Peking University, Haidian, Beijing, China
  ,
- Ru Huang
  Peking University, Haidian, Beijing, China
  ,
- David Z. Pan
  University of Texas at Austin
ASPDAC '18: Proceedings of the 23rd Asia and South Pacific Design Automation Conference•January 2018, pp 153-158

Layout-dependent effects (LDEs) are becoming increasingly important as technology node continues to shrink into the regime of FinFET transistors. Prior LDE studies mainly focus on accurate transistor modeling and fast circuit performance evaluations at ...
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research-article
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion
- Meng Li
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Bei Yu
  CSE Department, The Chinese University of Hong Kong, NT, Hong Kong
  ,
- Yibo Lin
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Xiaoqing Xu
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Wuxi Li
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- David Z. Pan
  ECE Department, University of Texas at Austin, Austin, TX, USA
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)•January 2018, pp 265-270• https://doi.org/10.1109/ASPDAC.2018.8297316
Trojans and backdoors inserted by untrusted foundries have become serious threats to hardware security. Split manufacturing is proposed to prevent Trojan insertion proactively. Existing methods depend on wire lifting to hide partial circuit ...
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Layout-dependent aging mitigation for critical path timing
- Che-Lun Hsu
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Shaofeng Guo
  Institute of Microelectronics, Peking University, Haidian, Beijing, China
  ,
- Yibo Lin
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Xiaoqing Xu
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Meng Li
  ECE Department, University of Texas at Austin, Austin, TX, USA
  ,
- Runsheng Wang
  Institute of Microelectronics, Peking University, Haidian, Beijing, China
  ,
- Ru Huang
  Institute of Microelectronics, Peking University, Haidian, Beijing, China
  ,
- David Z. Pan
  ECE Department, University of Texas at Austin, Austin, TX, USA
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)•January 2018, pp 153-158• https://doi.org/10.1109/ASPDAC.2018.8297298
Layout-dependent effects (LDEs) are becoming increasingly important as technology node continues to shrink into the regime of FinFET transistors. Prior LDE studies mainly focus on accurate transistor modeling and fast circuit performance evaluations at ...
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Redundant Local-Loop Insertion for Unidirectional Routing
- Xiaoqing Xu
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Yibo Lin
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Meng Li
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Jiaojiao Ou
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Brian Cline
  ARM Inc., Austin, TX, USA
  ,
- David Z. Pan
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 36, Issue 7•July 2017, pp 1113-1125 • https://doi.org/10.1109/TCAD.2017.2651811
As the semiconductor manufacturing technology continues to scale down to sub-10 nm, unidirectional layout style has become the mainstream for lower metal layers with tight pitches. Conventional redundant via (RV) insertion for yield improvement has become ...
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Incremental Layer Assignment Driven by an External Signoff Timing Engine
- Vinicius Livramento
  Automation and Systems Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil
  ,
- Derong Liu
  Electrical and Computer Engineering Department, University of Texas at Austin, Austin, TX, USA
  ,
- Salim Chowdhury
  Oracle Corporation, Austin, TX, USA
  ,
- Bei Yu
  Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong
  ,
- Xiaoqing Xu
  Electrical and Computer Engineering Department, University of Texas at Austin, Austin, TX, USA
  ,
- David Z. Pan
  Electrical and Computer Engineering Department, University of Texas at Austin, Austin, TX, USA
  ,
- José Luís Güntzel
  Computer Science Department, Federal University of Santa Catarina, Florianópolis, Brazil
  ,
- Luiz C. V dos Santos
  Automation and Systems Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 36, Issue 7•July 2017, pp 1126-1139 • https://doi.org/10.1109/TCAD.2016.2638450
Modern technologies provide wide and thick metal layers that must be wisely used to reduce the delay of critical interconnections. After global routing, incremental layer assignment can improve the circuit timing by properly selecting critical ...
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Published By ACM
Concurrent Pin Access Optimization for Unidirectional Routing
- Xiaoqing Xu
  University of Texas at Austin, Austin, TX, USA
  ,
- Yibo Lin
  University of Texas at Austin, Austin, TX, USA
  ,
- Vinicius Livramento
  Federal University of Santa Catarina, Brazil
  ,
- David Z. Pan
  University of Texas at Austin, Austin, TX, USA
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017•June 2017, Article No.: 20, pp 1-6• https://doi.org/10.1145/3061639.3062214

In advanced technology nodes, standard cell pin access is becoming challenging due to a small number of routing tracks and complex design-for-manufacturing constraints. Pin access interference is further exacerbated by unidirectional routing, which is ...
15Citation
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Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits
- Biying Xu
  University of Texas at Austin, Austin, TX, USA
  ,
- Shaolan Li
  University of Texas at Austin, Austin, TX, USA
  ,
- Xiaoqing Xu
  University of Texas at Austin, Austin, TX, USA
  ,
- Nan Sun
  University of Texas at Austin, Austin, TX, USA
  ,
- David Z. Pan
  University of Texas at Austin, Austin, TX, USA
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design•March 2017, pp 55-62• https://doi.org/10.1145/3036669.3036678

High-performance analog integrated circuits usually require minimizing critical parasitic loading, which can be modeled by the critical net wire length in the layout stage. In order to reduce post-layout circuit performance degradation, critical net ...
18Citation
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research-article
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DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment
- Jiaojiao Ou
  University of Texas at Austin, Austin, USA
  ,
- Bei Yu
  Chinese University of Hong Kong, Hong Kong, USA
  ,
- Xiaoqing Xu
  University of Texas at Austin, Austin, USA
  ,
- Joydeep Mitra
  Mentor Graphics Corporation, Austin, USA
  ,
- Yibo Lin
  University of Texas at Austin, Austin, USA
  ,
- David Z. Pan
  University of Texas at Austin, Austin, USA
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design•March 2017, pp 91-98• https://doi.org/10.1145/3036669.3036677

Directed self-assembly (DSA) is a promising solution for fabrication of contacts and vias for advanced technology nodes. In this paper, we study a DSA aware detailed routing problem, where DSA guiding pattern assignment and guiding pattern double ...
8Citation
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MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes
- Yibo Lin
  ECE Department, University of Texas at Austin, USA
  ,
- Bei Yu
  CSE Department, The Chinese University of Hong Kong, NT, Hong Kong
  ,
- Xiaoqing Xu
  ECE Department, University of Texas at Austin, USA
  ,
- Jhih-Rong Gao
  Cadence Design Systems Inc., Austin, TX, USA
  ,
- Natarajan Viswanathan
  Cadence Design Systems Inc., Austin, TX, USA
  ,
- Wen-Hao Liu
  Cadence Design Systems Inc., Austin, TX, USA
  ,
- Zhuo Li
  Cadence Design Systems Inc., Austin, TX, USA
  ,
- Charles J. Alpert
  Cadence Design Systems Inc., Austin, TX, USA
  ,
- David Z. Pan
  ECE Department, University of Texas at Austin, USA
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)•November 2016, pp 1-8• https://doi.org/10.1145/2966986.2967055
As VLSI technology shrinks to fewer tracks per standard cell, e.g., from 10-track to 7.5-track libraries (and lesser for 7nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design ...
33Citation
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Published By ACM
PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning
- Xiaoqing Xu
  The University of Texas at Austin, Austin, TX
  ,
- Bei Yu
  The Chinese University of Hong Kong, NT, Hong Kong
  ,
- Jhih-Rong Gao
  The University of Texas at Austin, Austin, TX
  ,
- Che-Lun Hsu
  The University of Texas at Austin, Austin, TX
  ,
- David Z. Pan
  The University of Texas at Austin, Austin, TX
ACM Transactions on Design Automation of Electronic Systems, Volume 21, Issue 3•July 2016, Article No.: 42, pp 1-21 • https://doi.org/10.1145/2842612

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, for example, in 14nm and below, for which double-patterning lithography has to be used for manufacturing lower metal routing layers with tight ...
23Citation
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Published By ACM
A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation
- Xiaoqing Xu
  University of Texas at Austin, Austin, TX, USA
  ,
- Tetsuaki Matsunawa
  Toshiba Corportation, Yokohama, Japan
  ,
- Shigeki Nojima
  Toshiba Corporation, Yokohama, Japan
  ,
- Chikaaki Kodama
  Toshiba Corporation, Yokohama, Japan
  ,
- Toshiya Kotani
  Toshiba Corporation, Yokohama, Japan
  ,
- David Z. Pan
  University of Texas at Austin, Austin, TX, USA
ISPD '16: Proceedings of the 2016 on International Symposium on Physical Design•April 2016, pp 161-168• https://doi.org/10.1145/2872334.2872357

Sub-Resolution Assist Feature (SRAF) generation is a very important resolution enhancement technique to improve yield in modern semiconductor manufacturing process. Model- based SRAF generation has been widely used to achieve high accuracy but it is ...
17Citation
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Published By ACM
Pushing multiple patterning in sub-10nm: are we ready?
- David Z. Pan
  University of Texas at Austin, Austin, TX
  ,
- Lars Liebmann
  IBM Corporation, East Fishkill, NY
  ,
- Bei Yu
  University of Texas at Austin, Austin, TX
  ,
- Xiaoqing Xu
  University of Texas at Austin, Austin, TX
  ,
- Yibo Lin
  University of Texas at Austin, Austin, TX
DAC '15: Proceedings of the 52nd Annual Design Automation Conference•June 2015, Article No.: 197, pp 1-6• https://doi.org/10.1145/2744769.2747940

Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple ...
25Citation
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PARR: pin access planning and regular routing for self-aligned double patterning
- Xiaoqing Xu
  Univ. of Texas at Austin, Austin, TX
  ,
- Bei Yu
  Univ. of Texas at Austin, Austin, TX
  ,
- Jhih-Rong Gao
  Univ. of Texas at Austin, Austin, TX
  ,
- Che-Lun Hsu
  Univ. of Texas at Austin, Austin, TX
  ,
- David Z. Pan
  Univ. of Texas at Austin, Austin, TX
DAC '15: Proceedings of the 52nd Annual Design Automation Conference•June 2015, Article No.: 28, pp 1-6• https://doi.org/10.1145/2744769.2744890

Pin access has become one of the most difficult challenges for detailed routing in 14nm technology node and beyond, where double patterning lithography has to be used for manufacturing lower metal layers with tight pitches. Self-aligned double ...
21Citation
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Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography
- Bei Yu
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Xiaoqing Xu
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Jhih-Rong Gao
  , Cadence Design Systems, Austin, TX, USA
  ,
- Yibo Lin
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
  ,
- Zhuo Li
  , Cadence Design Systems, Austin, TX, USA
  ,
- Charles J. Alpert
  , Cadence Design Systems, Austin, TX, USA
  ,
- David Z. Pan
  Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 34, Issue 5•May 2015, pp 726-739 • https://doi.org/10.1109/TCAD.2015.2401571
As the feature size of semiconductor process further scales to sub-16 nm technology node, triple patterning lithography (TPL) has been regarded as one of the most promising lithography candidates along with extreme ultraviolet, electron beam lithography, ...
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Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization
- Xiaoqing Xu
  Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
  ,
- Brian Cline
  ARM Inc., Austin, TX, USA
  ,
- Greg Yeric
  ARM Inc., Austin, TX, USA
  ,
- Bei Yu
  Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
  ,
- David Z. Pan
  Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 34, Issue 5•May 2015, pp 699-712 • https://doi.org/10.1109/TCAD.2015.2399439
Self-aligned double patterning (SADP) is being considered for use at the 10-nm technology node and below for routing layers with pitches down to ~50 nm because it has better line edge roughness and overlay control compared to other multiple patterning ...
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MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction
- Jhih-Rong Gao
  ECE Dept., Univ. of Texas at Austin, Austin, TX 78712
  ,
- Xiaoqing Xu
  ECE Dept., Univ. of Texas at Austin, Austin, TX 78712
  ,
- Bei Yu
  ECE Dept., Univ. of Texas at Austin, Austin, TX 78712
  ,
- David Z. Pan
  ECE Dept., Univ. of Texas at Austin, Austin, TX 78712
DAC '14: Proceedings of the 51st Annual Design Automation Conference•June 2014, pp 1-6• https://doi.org/10.1145/2593069.2593163

Optical Proximity Correction (OPC) has been widely adopted for resolution enhancement to achieve nanolithography. However, conventional rule-based and model-based OPCs encounter severe difficulties at advanced technology nodes. Inverse Lithography ...
53Citation
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A direct search interface for Author Profiles will be built.

An institutional view of works emerging from their faculty and researchers will be provided along with a relevant set of metrics.

It is possible, too, that the Author Profile page may evolve to allow interested authors to upload unpublished professional materials to an area available for search and free educational use, but distinct from the ACM Digital Library proper. It is hard to predict what shape such an area for user-generated content may take, but it carries interesting potential for input from the community.

Bibliometrics

The ACM DL is a comprehensive repository of publications from the entire field of computing.

It is ACM's intention to make the derivation of any publication statistics it generates clear to the user.

Average citations per article = The total Citation Count divided by the total Publication Count.
Citation Count = cumulative total number of times all authored works by this author were cited by other works within ACM's bibliographic database. Almost all reference lists in articles published by ACM have been captured. References lists from other publishers are less well-represented in the database. Unresolved references are not included in the Citation Count. The Citation Count is citations TO any type of work, but the references counted are only FROM journal and proceedings articles. Reference lists from books, dissertations, and technical reports have not generally been captured in the database. (Citation Counts for individual works are displayed with the individual record listed on the Author Page.)
Publication Count = all works of any genre within the universe of ACM's bibliographic database of computing literature of which this person was an author. Works where the person has role as editor, advisor, chair, etc. are listed on the page but are not part of the Publication Count.
Publication Years = the span from the earliest year of publication on a work by this author to the most recent year of publication of a work by this author captured within the ACM bibliographic database of computing literature (The ACM Guide to Computing Literature, also known as "the Guide".
Available for download = the total number of works by this author whose full texts may be downloaded from an ACM full-text article server. Downloads from external full-text sources linked to from within the ACM bibliographic space are not counted as 'available for download'.
Average downloads per article = The total number of cumulative downloads divided by the number of articles (including multimedia objects) available for download from ACM's servers.
Downloads (cumulative) = The cumulative number of times all works by this author have been downloaded from an ACM full-text article server since the downloads were first counted in May 2003. The counts displayed are updated monthly and are therefore 0-31 days behind the current date. Robotic activity is scrubbed from the download statistics.
Downloads (12 months) = The cumulative number of times all works by this author have been downloaded from an ACM full-text article server over the last 12-month period for which statistics are available. The counts displayed are usually 1-2 weeks behind the current date. (12-month download counts for individual works are displayed with the individual record.)
Downloads (6 weeks) = The cumulative number of times all works by this author have been downloaded from an ACM full-text article server over the last 6-week period for which statistics are available. The counts displayed are usually 1-2 weeks behind the current date. (6-week download counts for individual works are displayed with the individual record.)

ACM Author-Izer Service

Summary Description

ACM Author-Izer is a unique service that enables ACM authors to generate and post links on both their homepage and institutional repository for visitors to download the definitive version of their articles from the ACM Digital Library at no charge.

Downloads from these sites are captured in official ACM statistics, improving the accuracy of usage and impact measurements. Consistently linking to definitive version of ACM articles should reduce user confusion over article versioning.

ACM Author-Izer also extends ACM’s reputation as an innovative “Green Path” publisher, making ACM one of the first publishers of scholarly works to offer this model to its authors.

To access ACM Author-Izer, authors need to establish a free ACM web account. Should authors change institutions or sites, they can utilize the new ACM service to disable old links and re-authorize new links for free downloads from a different site.

How ACM Author-Izer Works

Authors may post ACM Author-Izer links in their own bibliographies maintained on their website and their own institution’s repository. The links take visitors to your page directly to the definitive version of individual articles inside the ACM Digital Library to download these articles for free.

The Service can be applied to all the articles you have ever published with ACM.

Depending on your previous activities within the ACM DL, you may need to take up to three steps to use ACM Author-Izer.

For authors who do not have a free ACM Web Account:

Go to the ACM DL http://dl.acm.org/ and click SIGN UP. Once your account is established, proceed to next step.

For authors who have an ACM web account, but have not edited their ACM Author Profile page:

Sign in to your ACM web account and go to your Author Profile page. Click "Add personal information" and add photograph, homepage address, etc. Click ADD AUTHOR INFORMATION to submit change. Once you receive email notification that your changes were accepted, you may utilize ACM Author-izer.

For authors who have an account and have already edited their Profile Page:

Sign in to your ACM web account, go to your Author Profile page in the Digital Library, look for the ACM Author-izer link below each ACM published article, and begin the authorization process. If you have published many ACM articles, you may find a batch Authorization process useful. It is labeled: "Export as: ACM Author-Izer Service"

ACM Author-Izer also provides code snippets for authors to display download and citation statistics for each “authorized” article on their personal pages. Downloads from these pages are captured in official ACM statistics, improving the accuracy of usage and impact measurements. Consistently linking to the definitive version of ACM articles should reduce user confusion over article versioning.

Note: You still retain the right to post your author-prepared preprint versions on your home pages and in your institutional repositories with DOI pointers to the definitive version permanently maintained in the ACM Digital Library. But any download of your preprint versions will not be counted in ACM usage statistics. If you use these AUTHOR-IZER links instead, usage by visitors to your page will be recorded in the ACM Digital Library and displayed on your page.

FAQ

Q. What is ACM Author-Izer?
A. ACM Author-Izer is a unique, link-based, self-archiving service that enables ACM authors to generate and post links on either their home page or institutional repository for visitors to download the definitive version of their articles for free.
Q. What articles are eligible for ACM Author-Izer?
A. ACM Author-Izer can be applied to all the articles authors have ever published with ACM. It is also available to authors who will have articles published in ACM publications in the future.

Q. Are there any restrictions on authors to use this service?
A. No. An author does not need to subscribe to the ACM Digital Library nor even be a member of ACM.

Q. What are the requirements to use this service?
A. To access ACM Author-Izer, authors need to have a free ACM web account, must have an ACM Author Profile page in the Digital Library, and must take ownership of their Author Profile page.

Q. What is an ACM Author Profile Page?
A. The Author Profile Page initially collects all the professional information known about authors from the publications record as known by the ACM Digital Library. The Author Profile Page supplies a quick snapshot of an author's contribution to the field and some rudimentary measures of influence upon it. Over time, the contents of the Author Profile page may expand at the direction of the community. Please visit the ACM Author Profile documentation page for more background information on these pages.

Q. How do I find my Author Profile page and take ownership?
A. You will need to take the following steps:
- Create a free ACM Web Account
- Sign-In to the ACM Digital Library
- Find your Author Profile Page by searching the ACM Digital Library for your name
- Find the result you authored (where your author name is a clickable link)
- Click on your name to go to the Author Profile Page
- Click the "Add Personal Information" link on the Author Profile Page
- Wait for ACM review and approval; generally less than 24 hours

Q. Why does my photo not appear?
A. Make sure that the image you submit is in .jpg or .gif format and that the file name does not contain special characters

Q. What if I cannot find the Add Personal Information function on my author page?
A. The ACM account linked to your profile page is different than the one you are logged into. Please logout and login to the account associated with your Author Profile Page.

Q. What happens if an author changes the location of his bibliography or moves to a new institution?
A. Should authors change institutions or sites, they can utilize ACM Author-Izer to disable old links and re-authorize new links for free downloads from a new location.

Q. What happens if an author provides a URL that redirects to the author’s personal bibliography page?
A. The service will not provide a free download from the ACM Digital Library. Instead the person who uses that link will simply go to the Citation Page for that article in the ACM Digital Library where the article may be accessed under the usual subscription rules.

However, if the author provides the target page URL, any link that redirects to that target page will enable a free download from the Service.

Q. What happens if the author’s bibliography lives on a page with several aliases?
A. Only one alias will work, whichever one is registered as the page containing the author’s bibliography. ACM has no technical solution to this problem at this time.

Q. Why should authors use ACM Author-Izer?
A. ACM Author-Izer lets visitors to authors’ personal home pages download articles for no charge from the ACM Digital Library. It allows authors to dynamically display real-time download and citation statistics for each “authorized” article on their personal site.

Q. Does ACM Author-Izer provide benefits for authors?
A. Downloads of definitive articles via Author-Izer links on the authors’ personal web page are captured in official ACM statistics to more accurately reflect usage and impact measurements.

Authors who do not use ACM Author-Izer links will not have downloads from their local, personal bibliographies counted. They do, however, retain the existing right to post author-prepared preprint versions on their home pages or institutional repositories with DOI pointers to the definitive version permanently maintained in the ACM Digital Library.

Q. How does ACM Author-Izer benefit the computing community?
A. ACM Author-Izer expands the visibility and dissemination of the definitive version of ACM articles. It is based on ACM’s strong belief that the computing community should have the widest possible access to the definitive versions of scholarly literature. By linking authors’ personal bibliography with the ACM Digital Library, user confusion over article versioning should be reduced over time.

In making ACM Author-Izer a free service to both authors and visitors to their websites, ACM is emphasizing its continuing commitment to the interests of its authors and to the computing community in ways that are consistent with its existing subscription-based access model.

Q. How do authors access ACM Author-Izer?
A. See How to Use

Q. Why can’t I find my most recent publication in my ACM Author Profile Page?
A. There is a time delay between publication and the process which associates that publication with an Author Profile Page. Right now, that process usually takes 4-8 weeks.

Q. How does ACM Author-Izer expand ACM’s “Green Path” Access Policies?
A. ACM Author-Izer extends the rights and permissions that authors retain even after copyright transfer to ACM, which has been among the “greenest” publishers. ACM enables its author community to retain a wide range of rights related to copyright and reuse of materials. They include:
- Posting rights that ensure free access to their work outside the ACM Digital Library and print publications
- Rights to reuse any portion of their work in new works that they may create
- Copyright to artistic images in ACM’s graphics-oriented publications that authors may want to exploit in commercial contexts
- All patent rights, which remain with the original owner

Xiaoqing Xu

Xiaoqing Xu

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TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design

Self-aligned double-patterning aware legalization

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion

A practical split manufacturing framework for trojan prevention via simultaneous wire lifting and cell insertion

Layout-dependent aging mitigation for critical path timing

A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion

Layout-dependent aging mitigation for critical path timing

Redundant Local-Loop Insertion for Unidirectional Routing

Incremental Layer Assignment Driven by an External Signoff Timing Engine

Concurrent Pin Access Optimization for Unidirectional Routing

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment

MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning

A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation

Pushing multiple patterning in sub-10nm: are we ready?

PARR: pin access planning and regular routing for self-aligned double patterning

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction