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RL4ReAl: Reinforcement Learning for Register Allocation

Authors:

S. VenkataKeerthy,

Siddharth Jain,

Rohit Aggarwal,

Ramakrishna UpadrastaAuthors Info & Claims

CC 2023: Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction

Pages 133 - 144

https://doi.org/10.1145/3578360.3580273

Published: 17 February 2023 Publication History

Abstract

We aim to automate decades of research and experience in register allocation, leveraging machine learning. We tackle this problem by embedding a multi-agent reinforcement learning algorithm within LLVM, training it with the state of the art techniques. We formalize the constraints that precisely define the problem for a given instruction-set architecture, while ensuring that the generated code preserves semantic correctness. We also develop a gRPC based framework providing a modular and efficient compiler interface for training and inference. Our approach is architecture independent: we show experimental results targeting Intel x86 and ARM AArch64. Our results match or out-perform the heavily tuned, production-grade register allocators of LLVM.

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Cited By

Maroun ESchoeberl MPuschner P(2024)Two-Step Register Allocation for Implementing Single-Path Code2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC61049.2024.10551362(1-12)Online publication date: 22-May-2024
https://doi.org/10.1109/ISORC61049.2024.10551362
Terci GAbdulhalik EBayrakci ABoz B(2024)BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register AllocationIEEE Access10.1109/ACCESS.2024.344659612(115497-115514)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3446596
Jain SVenkataKeerthy SAggarwal RDangeti TDas DUpadrasta R(2022)Reinforcement Learning assisted Loop Distribution for Locality and Vectorization2022 IEEE/ACM Eighth Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)10.1109/LLVM-HPC56686.2022.00006(1-12)Online publication date: Nov-2022
https://doi.org/10.1109/LLVM-HPC56686.2022.00006

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RL4ReAl: Reinforcement Learning for Register Allocation

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cover image ACM Conferences

CC 2023: Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction

February 2023

249 pages

ISBN:9798400700880

DOI:10.1145/3578360

General Chair:
Clark Verbrugge
McGill University, Canada
,
Program Chairs:
Ondřej Lhoták
University of Waterloo, Canada
,
Xipeng Shen
North Carolina State University, USA / Facebook, USA

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Published: 17 February 2023

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Cited By

Maroun ESchoeberl MPuschner P(2024)Two-Step Register Allocation for Implementing Single-Path Code2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC61049.2024.10551362(1-12)Online publication date: 22-May-2024
https://doi.org/10.1109/ISORC61049.2024.10551362
Terci GAbdulhalik EBayrakci ABoz B(2024)BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register AllocationIEEE Access10.1109/ACCESS.2024.344659612(115497-115514)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3446596
Jain SVenkataKeerthy SAggarwal RDangeti TDas DUpadrasta R(2022)Reinforcement Learning assisted Loop Distribution for Locality and Vectorization2022 IEEE/ACM Eighth Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)10.1109/LLVM-HPC56686.2022.00006(1-12)Online publication date: Nov-2022
https://doi.org/10.1109/LLVM-HPC56686.2022.00006

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