Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms

Large-scale graph analytics has gained importance due to emergence of new applications in different contexts such as web, social networks, and computational biology. It is known that typical CPU/GPU implementations for sparse graph applications cannot efficiently utilize the available compute resources. In our previous work, we have shown that significant performance and energy efficiency improvements can be achieved using custom hardware accelerators for graph applications. On the other hand, designing application-specific hardware is expensive in terms of engineering, manufacturing, and maintenance costs. Since FPGAs are known to provide a good tradeoff between customizability and efficiency, several prominent vendors have started offering data-center solutions with FPGAs.

In this talk, we present our recent and ongoing work on FPGA accelerators for graph analytics. Specifically, we propose a template-based optimized architecture that is targeted for both standalone FPGA and integrated CPU+FPGA platforms with coherent shared memory space.

For easier programmability, we propose a vertex-centric template model where the high-level application-specific data structures and functions are separated from low-level hardware-specific optimizations. Our methodology includes source-to-source transformation of user-defined graph data structures so that they can be shared by the host software and the FPGA hardware. We also propose several low-level architectural optimizations to improve both throughput of computation and work efficiency of graph applications. Our initial results show that these optimizations can lead to significant improvements with respect to state-of-the-art implementations.