3. (10 points) A circuit contains two 16-bit registers (RegA and RegB), a 16-bit wide bank of XORS, a 16-bit wide bank of inverters, a 16-bit-wide bank of AND gates, and a 16-bit 4:1 mux. The 16-bit inputs A and B are the inputs to RegA and RegB, respectively. The 16-bit mux output is DataOut. The two mux selects are CTL1 and CTL0. The circuit has this functionality: CTL1 CTLO 00 DataOut RegA 01 RegA & RegB 10 Λ 11 RegA ^ RegB RegA & ~RegB Note that the AND and XOR functions above are “bit-wise” operations, meaning the corresponding bits from the two busses feeding the functions are operated on, in this case yielding a 16-bit output. For example, for the XOR case, b15 of RegA would be XORed with b15 of RegB to yield b15 of the XOR outpt, b14 of RegA would be XORed with b14 of RegB to yield b14 of the XOR output, etc. a) Draw the circuit described. Show the bus widths on the diagram. For the 16-bit XOR, 16-bit AND and 16-bit bank of inverters, you can draw one logical symbol with buses going in and out of the symbol.
3. (10 points) A circuit contains two 16-bit registers (RegA and RegB), a 16-bit wide bank of XORS, a 16-bit wide bank of inverters, a 16-bit-wide bank of AND gates, and a 16-bit 4:1 mux. The 16-bit inputs A and B are the inputs to RegA and RegB, respectively. The 16-bit mux output is DataOut. The two mux selects are CTL1 and CTL0. The circuit has this functionality: CTL1 CTLO 00 DataOut RegA 01 RegA & RegB 10 Λ 11 RegA ^ RegB RegA & ~RegB Note that the AND and XOR functions above are “bit-wise” operations, meaning the corresponding bits from the two busses feeding the functions are operated on, in this case yielding a 16-bit output. For example, for the XOR case, b15 of RegA would be XORed with b15 of RegB to yield b15 of the XOR outpt, b14 of RegA would be XORed with b14 of RegB to yield b14 of the XOR output, etc. a) Draw the circuit described. Show the bus widths on the diagram. For the 16-bit XOR, 16-bit AND and 16-bit bank of inverters, you can draw one logical symbol with buses going in and out of the symbol.
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Question
Solve this problem and show all of the work
Transcribed Image Text:3. (10 points) A circuit contains two 16-bit registers (RegA and RegB), a 16-bit wide bank of XORS, a
16-bit wide bank of inverters, a 16-bit-wide bank of AND gates, and a 16-bit 4:1 mux. The 16-bit
inputs A and B are the inputs to RegA and RegB, respectively. The 16-bit mux output is DataOut. The
two mux selects are CTL1 and CTL0.
The circuit has this functionality:
CTL1 CTLO
00
DataOut
RegA
01
RegA & RegB
10
Λ
11
RegA ^ RegB
RegA & ~RegB
Note that the AND and XOR functions above are “bit-wise” operations, meaning the corresponding bits from
the two busses feeding the functions are operated on, in this case yielding a 16-bit output. For example, for
the XOR case, b15 of RegA would be XORed with b15 of RegB to yield b15 of the XOR outpt, b14 of RegA
would be XORed with b14 of RegB to yield b14 of the XOR output, etc.
a) Draw the circuit described. Show the bus widths on the diagram. For the 16-bit XOR, 16-bit AND and
16-bit bank of inverters, you can draw one logical symbol with buses going in and out of the symbol.
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