SPEC Seal of Reviewal OMPM2001 Result
Copyright © 1999-2008 Standard Performance Evaluation Corporation
HP
HP Proliant DL580 G7 Server Series, Intel Xeon L7555, 1.87 GHz
SPECompMpeak2001 = -- 
SPECompMbase2001 = 80989      
SPEC license # HPG3440A Tested by: Indiana University Test site: Indiana University Test date: Oct-2011 Hardware Avail: Jun-2010 Software Avail: Jan-2011
Benchmark Reference
Time
Base
Runtime
Base
Ratio
Peak
Runtime
Peak
Ratio
Graph Scale
310.wupwise_m 6000 37.3  160774             310.wupwise_m base result bar (160774)
312.swim_m 6000 74.2  80847            312.swim_m base result bar (80847)
314.mgrid_m 7300 87.7  83222            314.mgrid_m base result bar (83222)
316.applu_m 4000 26.1  153288             316.applu_m base result bar (153288)
318.galgel_m 5100 114    44802            318.galgel_m base result bar (44802)
320.equake_m 2600 47.9  54295            320.equake_m base result bar (54295)
324.apsi_m 3400 46.5  73134            324.apsi_m base result bar (73134)
326.gafort_m 8700 109    79651            326.gafort_m base result bar (79651)
328.fma3d_m 4600 92.8  49543            328.fma3d_m base result bar (49543)
330.art_m 6400 32.9  194318             330.art_m base result bar (194318)
332.ammp_m 7000 161    43469            332.ammp_m base result bar (43469)
SPECompMbase2001 80989        
  SPECompMpeak2001 --   

Hardware
Hardware Vendor: HP
Model Name: HP Proliant DL580 G7 Server Series, Intel Xeon L7555, 1.87 GHz
CPU: Intel Xeon L7555
CPU MHz: 1866
FPU: Integrated
CPU(s) enabled: 32 cores, 4 chips, 8 cores/chip (HT on)
CPU(s) orderable: 1-4 chips
Primary Cache: 32 KB I + 32 KB D on chip per core
Secondary Cache: 256 KB I+D on chip per core
L3 Cache: 24 MB I+D on chip per chip
Other Cache: None
Memory: 512 GB (64 x 8 GB 2Rx4 PC3-10600R, ECC, running at 1066 MHz and CL9)
Disk Subsystem: Two 500 GB 7200 RPM 2.5" SAS hard drives, in RAID 1 mirror
Other Hardware: None
Software
OpenMP Threads: 32
Parallel: OpenMP
Operating System: RHEL6.0 (x86_64) 2.6.32-71.14.1.el6
Kernel 2.6.32-71.14.1.el6
Compiler: Intel(R) C/C++ Composer XE 2011 for Linux, version 12.0.2, Build 20110112
Intel(R) Fortran Composer XE 2011 for Linux, version 12.0.2, Build 20110112
File System: NFSv3 (IBM N5500 NAS) over Gb ethernet
System State: Multi-user, run level 3
Notes / Tuning Information
 ulimit -s unlimited
     Removes limits on the maximum size of the automatically-
     extended stack region of the current process and each
     process it creates.
 Compiler flags for base level optimization
     COPTIMIZE : -O3 -xSSE4.1 -no-prec-div -openmp -ipo
     FOPTIMIZE : -O3 -xSSE4.1 -no-prec-div -openmp -ipo
     F77OPTIMIZE : -O3 -xSSE4.1 -no-prec-div -openmp -ipo
 Environment:
     KMP_AFFINITY=compact,1
      controls the binding of OpenMP threads to the physical processing units
     KMP_SCHEDULE=static,balanced
      used to fine tune the load balancing of parallel loops that are 
      statically scheduled under OpenMP with no chunk size specification
     KMP_BLOCKTIME=infinite
      Sets the time, in milliseconds, that a thread should wait, 
      after completing the execution of a parallel region, before sleeping.
     KMP_LIBRARY=throughput
      Selects the OpenMP run-time library
     KMP_STACKSIZE=31m
      Sets the number of bytes to allocate for each parallel thread to use as 
      to use as its provate stack
     OMP_NESTED=TRUE
      Enables (TRUE) or  disables  (FALSE)  nested  parallelism.
     OMP_DYNAMIC=FALSE
      Enables (true) or disables (false) the dynamic adjustment of the number of threads. 
     OMP_NUM_THREADS=32
      Sets  the maximum number of threads to use for OpenMP* parallel
      regions if no other value is specified in the  program  itself.
 Portability Flags:
     318.galgel_m=default=default=default:
      FFLAGS=-fixed -extend-source 132
 BIOS settings notes:
      Intel Hyper-Threading Technology (SMT): Enabled
      Intel Turbo Boost Technology (Turbo)  : Enabled (Max 2.533GHz)
 For compiler/openmp flags description please refer:
 Intel-ic12.0-intel64-linux-flags-file.html



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First published at SPEC.org on 16-Nov-2011

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