This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Intel Turbo boost Technology, Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.
The Intel Hyper-Threading knob has been renamed Enable LP [Global] to represent the number of logical processors (LP). This feature allows enabling or disabling of logical processor cores on processors supporting Intel Hyper-Threading. Recommended default setting is All LPs. In some cases, setting this option to Single LP can improve performance.
Values for this BIOS setting can be:
Enabled: Each physical processor core operates as two logical processor cores. Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.
Single LP: Each physical core operates as only one logical processor core.
Performance Profiles is a feature that allows customer to tune resources in their servers by selecting pre-configured performance profiles.
Values for this BIOS setting can be:
Custom: Allows the user to setup all of the BIOS options according to customer's requirement.
Performance: Maximize the performance of the server.
Efficiency: Maximize the power efficiency of the server.
Load Balance: The system's performance and power consumption will be adjusted automatically according to the loading.
Enable or disable reporting of the CPU C6 State (ACPI C3) to the OS.
When set to Enabled, the processor is allowed to switch to nimimum performance and save power when idle.
Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range,with each cluster bound to a subset of the memory controllers in the system.It improves average latency to the LLC.
Values for this BIOS option can be:
Disabled: SNC disabled will support 1-cluster and 4-way IMC interleave.
Enable SNC2 (2-clusters): SNC2 Enabled supports 2-clusters SNC and 2-way IMC interleave.
Enable SNC4 (4-clusters): SNC2 Enabled supports 4-clusters SNC and 1-way IMC interleave.
The last level cache (LLC) prefetch is a prefetcher added to the Intel Xeon Scalable processor family as a result of the non-inclusive cache architecture. The LLC prefetcher is an additional prefetch mechanism on top of the existing prefetchers that prefetch data into the core Data Cache Unit (DCU) and Mid-Level Cache (MLC or second-level cache (L2)). Enabling LLC prefetch gives the core prefetcher the ability to prefetch data directly into the LLC without necessarily filling into the L1 and L2 cache. In some cases, setting this option to disabled can improve performance.
Values for this BIOS option can be:
Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.
Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
Adaptive Double Device Data Correction (ADDDC), which is an enhanced feature to DDDC. This function is used to correct data errors on two memory particles, ADDDC still has single-particle multi-bit error correction capability after the first particle failure occurs and is replaced.
Values for this BIOS option can be:
Enabled: Enable the ADDDC Sparing function.
Disabled: Disable the ADDDC Sparing function.