SPEC CPU(R)2017 Floating Point Speed Result Cisco Systems Cisco UCS B200 M5 (Intel Xeon Bronze 3104, 1.70 GHz) CPU2017 License: 9019 Test date: Jun-2018 Test sponsor: Cisco Systems Hardware availability: Aug-2017 Tested by: Cisco Systems Software availability: Mar-2018 Base Base Base Peak Peak Peak Benchmarks Threads Run Time Ratio Threads Run Time Ratio --------------- ------- --------- --------- ------- --------- --------- 603.bwaves_s 12 259 228 S 12 259 228 S 603.bwaves_s 12 260 227 * 12 260 227 S 603.bwaves_s 12 260 227 S 12 260 227 * 607.cactuBSSN_s 12 356 46.9 S 12 352 47.4 S 607.cactuBSSN_s 12 355 46.9 * 12 353 47.3 * 607.cactuBSSN_s 12 355 46.9 S 12 353 47.2 S 619.lbm_s 12 199 26.4 S 12 198 26.4 S 619.lbm_s 12 198 26.5 S 12 198 26.4 S 619.lbm_s 12 198 26.4 * 12 198 26.4 * 621.wrf_s 12 454 29.1 * 12 461 28.7 * 621.wrf_s 12 455 29.1 S 12 463 28.6 S 621.wrf_s 12 453 29.2 S 12 459 28.8 S 627.cam4_s 12 645 13.7 S 12 646 13.7 S 627.cam4_s 12 647 13.7 S 12 647 13.7 S 627.cam4_s 12 646 13.7 * 12 646 13.7 * 628.pop2_s 12 396 30.0 * 12 382 31.0 S 628.pop2_s 12 395 30.0 S 12 384 30.9 S 628.pop2_s 12 396 30.0 S 12 383 31.0 * 638.imagick_s 12 653 22.1 S 12 649 22.2 S 638.imagick_s 12 649 22.2 S 12 650 22.2 * 638.imagick_s 12 650 22.2 * 12 650 22.2 S 644.nab_s 12 417 41.9 * 12 418 41.8 * 644.nab_s 12 417 41.9 S 12 418 41.8 S 644.nab_s 12 417 41.9 S 12 417 41.9 S 649.fotonik3d_s 12 202 45.2 S 12 201 45.4 * 649.fotonik3d_s 12 201 45.3 * 12 201 45.4 S 649.fotonik3d_s 12 201 45.3 S 12 201 45.4 S 654.roms_s 12 396 39.7 * 12 376 41.9 S 654.roms_s 12 396 39.8 S 12 374 42.1 S 654.roms_s 12 397 39.6 S 12 375 42.0 * ================================================================================= 603.bwaves_s 12 260 227 * 12 260 227 * 607.cactuBSSN_s 12 355 46.9 * 12 353 47.3 * 619.lbm_s 12 198 26.4 * 12 198 26.4 * 621.wrf_s 12 454 29.1 * 12 461 28.7 * 627.cam4_s 12 646 13.7 * 12 646 13.7 * 628.pop2_s 12 396 30.0 * 12 383 31.0 * 638.imagick_s 12 650 22.2 * 12 650 22.2 * 644.nab_s 12 417 41.9 * 12 418 41.8 * 649.fotonik3d_s 12 201 45.3 * 12 201 45.4 * 654.roms_s 12 396 39.7 * 12 375 42.0 * SPECspeed(R)2017_fp_base 37.6 SPECspeed(R)2017_fp_peak 37.9 HARDWARE -------- CPU Name: Intel Xeon Bronze 3104 Max MHz: 1700 Nominal: 1700 Enabled: 12 cores, 2 chips Orderable: 1,2 Chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 8.25 MB I+D on chip per chip Other: None Memory: 384 GB (24 x 16 GB 2Rx4 PC4-2666V-R, running at 2133) Storage: 1 x 1 TB SAS HDD, 7.2K RPM Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 12 SP2 (x86_64) 4.4.103-92.56-default Compiler: C/C++: Version 18.0.2.199 of Intel C/C++ Compiler for Linux; Fortran: Version 18.0.2.199 of Intel Fortran Compiler for Linux Parallel: Yes Firmware: Version 3.2.3c released Mar-2018 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: 64-bit Other: None Power Management: -- Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" General Notes ------------- Environment variables set by runcpu before the start of the run: KMP_AFFINITY = "granularity=fine,compact" LD_LIBRARY_PATH = "/home/cpu2017/lib/ia32:/home/cpu2017/lib/intel64:/home/cpu2017/je5.0.1-32:/home/cpu2017/je5.0.1-64" OMP_STACKSIZE = "192M" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.4 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches Yes: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. Platform Notes -------------- BIOS Settings: CPU performance set to Enterprise Power Performance Tuning set to OS Controls SNC set to Disabled Patrol Scrub set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r5797 of 2017-06-14 96c45e4568ad54c135fd618bcc091c0f running on linux-uezu Fri Jun 8 20:44:06 2018 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Bronze 3104 CPU @ 1.70GHz 2 "physical id"s (chips) 12 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 6 siblings : 6 physical 0: cores 0 1 2 3 4 5 physical 1: cores 0 1 2 3 4 5 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 12 On-line CPU(s) list: 0-11 Thread(s) per core: 1 Core(s) per socket: 6 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Bronze 3104 CPU @ 1.70GHz Stepping: 4 CPU MHz: 1217.291 CPU max MHz: 1700.0000 CPU min MHz: 800.0000 BogoMIPS: 3400.00 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 8448K NUMA node0 CPU(s): 0-5 NUMA node1 CPU(s): 6-11 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch arat epb invpcid_single pln pts dtherm hwp hwp_act_window hwp_epp hwp_pkg_req intel_pt spec_ctrl kaiser tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc /proc/cpuinfo cache data cache size : 8448 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 node 0 size: 192074 MB node 0 free: 191776 MB node 1 cpus: 6 7 8 9 10 11 node 1 size: 193504 MB node 1 free: 193172 MB node distances: node 0 1 0: 10 21 1: 21 10 From /proc/meminfo MemTotal: 394832568 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-uezu 4.4.103-92.56-default #1 SMP Wed Dec 27 16:24:31 UTC 2017 (2fd2155) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Jan 4 23:04 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda1 xfs 894G 119G 776G 14% / Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. B200M5.3.2.3c.0.0307181316 03/07/2018 Memory: 24x 0xCE00 M393A2G40EB2-CTD 16 GB 2 rank 2666, configured at 2133 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== C | 619.lbm_s(base, peak) 638.imagick_s(base, peak) | 644.nab_s(base, peak) ------------------------------------------------------------------------------ icc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++, C, Fortran | 607.cactuBSSN_s(base, peak) ------------------------------------------------------------------------------ icpc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. icc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ifort (IFORT) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran | 603.bwaves_s(base, peak) 649.fotonik3d_s(base, peak) | 654.roms_s(base, peak) ------------------------------------------------------------------------------ ifort (IFORT) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran, C | 621.wrf_s(base, peak) 627.cam4_s(base, peak) | 628.pop2_s(base, peak) ------------------------------------------------------------------------------ ifort (IFORT) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. icc (ICC) 18.0.2 20180210 Copyright (C) 1985-2018 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 Fortran benchmarks: ifort -m64 Benchmarks using both Fortran and C: ifort -m64 icc -m64 -std=c11 Benchmarks using Fortran, C, and C++: icpc -m64 icc -m64 -std=c11 ifort -m64 Base Portability Flags ---------------------- 603.bwaves_s: -DSPEC_LP64 607.cactuBSSN_s: -DSPEC_LP64 619.lbm_s: -DSPEC_LP64 621.wrf_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian 627.cam4_s: -DSPEC_LP64 -DSPEC_CASE_FLAG 628.pop2_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian -assume byterecl 638.imagick_s: -DSPEC_LP64 644.nab_s: -DSPEC_LP64 649.fotonik3d_s: -DSPEC_LP64 654.roms_s: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -qopenmp -DSPEC_OPENMP Fortran benchmarks: -DSPEC_OPENMP -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -qopenmp -nostandard-realloc-lhs -align array32byte Benchmarks using both Fortran and C: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs -align array32byte Benchmarks using Fortran, C, and C++: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs -align array32byte Peak Compiler Invocation ------------------------ C benchmarks: icc -m64 -std=c11 Fortran benchmarks: ifort -m64 Benchmarks using both Fortran and C: ifort -m64 icc -m64 -std=c11 Benchmarks using Fortran, C, and C++: icpc -m64 icc -m64 -std=c11 ifort -m64 Peak Portability Flags ---------------------- Same as Base Portability Flags Peak Optimization Flags ----------------------- C benchmarks: 619.lbm_s: -prof-gen(pass 1) -prof-use(pass 2) -O2 -xCORE-AVX512 -qopt-prefetch -ipo -O3 -ffinite-math-only -no-prec-div -qopt-mem-layout-trans=3 -DSPEC_SUPPRESS_OPENMP -qopenmp -DSPEC_OPENMP 638.imagick_s: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -qopenmp -DSPEC_OPENMP 644.nab_s: Same as 638.imagick_s Fortran benchmarks: -prof-gen(pass 1) -prof-use(pass 2) -DSPEC_SUPPRESS_OPENMP -DSPEC_OPENMP -O2 -xCORE-AVX512 -qopt-prefetch -ipo -O3 -ffinite-math-only -no-prec-div -qopt-mem-layout-trans=3 -qopenmp -nostandard-realloc-lhs -align array32byte Benchmarks using both Fortran and C: 621.wrf_s: -prof-gen(pass 1) -prof-use(pass 2) -O2 -xCORE-AVX512 -qopt-prefetch -ipo -O3 -ffinite-math-only -no-prec-div -qopt-mem-layout-trans=3 -DSPEC_SUPPRESS_OPENMP -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs -align array32byte 627.cam4_s: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=3 -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs -align array32byte 628.pop2_s: Same as 621.wrf_s Benchmarks using Fortran, C, and C++: -prof-gen(pass 1) -prof-use(pass 2) -O2 -xCORE-AVX512 -qopt-prefetch -ipo -O3 -ffinite-math-only -no-prec-div -qopt-mem-layout-trans=3 -DSPEC_SUPPRESS_OPENMP -qopenmp -DSPEC_OPENMP -nostandard-realloc-lhs -align array32byte The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2018-06-13.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2018-06-13.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.xml SPEC CPU and SPECspeed are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2023 Standard Performance Evaluation Corporation Tested with SPEC CPU(R)2017 v1.0.2 on 2018-06-08 20:44:05-0400. Report generated on 2023-03-03 16:10:57 by CPU2017 text formatter v6255. Originally published on 2018-06-26.