SPEC CPU2006 Platform Settings for SGI Intel-based systems
- dplace -c cpulist -r A $command
- dplace is a tool for binding processes to cpus
Here is a brief description of options used in the config file:
- -c cpulist: pin processes to the specified comma-separated list or range of cpus. These are logical cpus, relative to the enclosing cpuset.
- -r A: specifies that text should be replicated on the NUMA node or nodes where the process is running. 'A' indicates that all library and DSO text and read/write data should be replicated.
- For full details on using dplace, please refer to your Linux documentation, 'man dplace'.
- Transparent Huge Pages
- On SLES11 SP2 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads.
If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/transparent_hugepage/enabled field is changed from its default of 'always' to 'never' or 'madvise'.
- Hardware Prefetch:
-
This BIOS option allows the enabling/disabling of a processor mechanism
to prefetch data into the cache according to a pattern-recognition algorithm
In some cases, setting this option to Disabled may improve performance.
Users should only disable this option after performing application benchmarking
to verify improved performance in their environment.
- Adjacent Sector Prefetch:
-
This BIOS option allows the enabling/disabling of a processor mechanism
to fetch the adjacent cache line within a 128-byte sector that contains the
data needed due to a cache line miss.
In some cases, setting this option to Disabled may improve performance.
Users should only disable this option after performing application benchmarking
to verify improved performance in their environment.
- High Bandwidth:
- Enabling this option allows the chipset to defer memory transactions and
process them out of order for optimal performance.