CPU2017 Flag Description
Fujitsu PRIMERGY RX4770 M5, Intel Xeon Platinum 8270, 2.70GHz

Copyright © 2016 Intel Corporation. All Rights Reserved.

Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++

Base Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r

Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++

Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.

Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:
submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"
Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.
KMP_STACKSIZE
Specify stack size to be allocated for each thread.
KMP_AFFINITY
Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
Set stack size to unlimited
The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.
Free the file system page cache
The command "echo 1> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache.

Red Hat Specific features

Transparent Huge Pages
On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Operating System Tuning Parameters

cpupower frequency-set
cpupower utility is a collection of tools for power efficiency of processor. frequency-set sub-command controls settings for processor frequency. "-g [governor]" specifies a policy to select processor frequency. The performance governor statically sets frequency of the processor cores specified by "-c" option to the highest possible for maximum performance.
cpupower idle-set
idle-set sub-command of cpupower utility controls a processor idle state (C-state) of the kernel. "-d [state_no]>" option disables a specific processor idle state. Disabling idle state can reduce the idle-wakeup delay, but it results in substantially higher power consumption. By default, processor idle states of all CPU cores are set.
isolcpus
This kernel option excludes a specified processor from load balancing by the kernel scheduler. This prevents the scheduler from scheduling any user-space threads on this processor.
nohz_full
This kernel option sets adaptive tick mode (NOHZ_FULL) to specified processors. Since the number of interrupts is reduced to ones per second, latency-sensitive applications can take advantage of it.
numa_balancing
This OS setting controls automatic NUMA balancing on memory mapping and process placement. Setting 0 disables this feature. It is enabled by default (1).
sched_min_granularity_ns
This OS setting controls the minimal preemption granularity for CPU bound tasks. As the number of runnable tasks increases, CFS(Complete Fair Scheduler), the scheduler of the Linux kernel, decreases the timeslices of tasks. If the number of runnable tasks exceeds sched_latency_ns/sched_min_granularity_ns, the timeslice becomes number_of_running_tasks * sched_min_granularity_ns. The default value is 8000000(ns).
sched_wakeup_granularity_ns
This OS setting controls the wake-up preemption granularity. Increasing this variable reduces wake-up preemption, reducing disturbance of compute bound tasks. Lowering it improves wake-up latency and throughput for latency critical tasks, particularly when a short duty cycle load component must compete with CPU bound components. The default value is 10000000 (ns).

Firmware / BIOS / Microcode Settings

Adjacent Cache Line Prefetch
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
This prefetcher always collects cache line pairs (128 bytes) from the main memory, providing that the data is not already contained in the cache. If this prefetcher is disabled, only one chace line (64 bytes) is collected, which contains the data required by the processor.
CPU C1E Support
Enabling this option which is the default allows the processor to transmit to its minimum frequency when entering the power state C1. If the switch is disabled the CPU stays at its maximum frequency in C1. Because of the increase of power consumption users should only select this option after performing application benchmarking to verify improved performance in their environment.
DCU Ip Prefetcher
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
This L1-cache prefether looks for sequential load history and attempts on this basis to determine the next data to be expected and, if necessary, to prefetch this data from the L2 cache or the main memory into the L1 cache.
DCU Streamer Prefetcher
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
This prefetcher is a L1 data cache prefetcher, which detects multiple loads from the same cache line done within a time limit, in order to then prefetch the next line from the L2 cache or the main memory into the L1 cache based on the assumption that the next cache line will also be needed.
DDR4 Write Data CRC Protection
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default setting is "Enabled" (PRIMERGY servers) or "Disabled" (PRIMEQUEST servers).
This BIOS option enables or disable DDR4 CRC write feature. When "Enabled" is selected, memroy controller generates a CRC code from the data to write.
Energy Performance:
This BIOS switch allows 4 options: "Balanced performance", "Performance", "Balanced Energy" and "Energy Efficient". The default is "Balanced Performance" optimized to maximum power savings with minimal impact on performance. "Performance" disables all power management options with any impact on performance. "Balanced Energy" is optimized for power efficiency and "Energy Efficient" for power savings. The BIOS switch is only selectable if the BIOS switch "Power Technology" is selectable and set to "Custom".
The two options "Balanced Performance" and "Balanced Energy" should always be the first choice as both options optimize the efficiency of the system. In cases where the performance is not sufficient or the power consumption is too high the two options "Performance" or "Energy Efficient" could be an alternative.
Fan Control
This BIOS switch allows 2 options: "Auto" and "Full". The default setting is "Auto", which allows the system to control the fan speed according to the system temperature. If "Full" is selected, the system runs fans at 100% speed and it may improve the system performance. But it increases the power consumption of the system.
IMC Interleaving
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs). There are two IMCs per socket in Skylake Server. If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs. If IMC Interleaving is set to 1-way, there will be no interleaving. If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way. Default setting is "Auto".
Intel Virtualization Technology
This BIOS option enables or disables additional virtualization functions of the CPU. If the server is not used for virtualization, this option should be set to "Disabled". This can result in energy savings. Default setting is "Enabled".
IO Directory Cache (IODC)
This BIOS switch allows 2 options: "Auto" and "Disabled". The default is "Auto".
IODC eliminates directory cache reads for remote IO writes and reduces access overhead to directory cache. This feature improves stream throughput.
Hardware Prefetcher
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
This prefetcher looks for data streams on the assumption that if the data is requested at address A and A+1, the data will also presumably be required at address A+2. This data is then prefetched into the L2 cache from the main memory.
HWPM Support
This BIOS switch allows 4 options: "Native Mode", "Disabled", "Out of Band Mode" and "Native Mode with No legacy Support". The default is "Native Mode".
With Hardware Power Management(HWPM) the processors provides a flexible interface between Hardware and Platform for performance management and improving energy efficiency.
In Native Mode the HWPM operates cooperatively with the OS via a software interface to provide constraints and hints.
When disabled, system does not use HWPM.
Hyper-Threading
This BIOS option enables or disables additional hardware thread which shares same physical core. Generally "Enabled" is recommended but disabling it makes sense for the application which requires the shortest possible response times. Default setting is "Enabled".
Link Frequency Select
This switch allows the configuration of the Intel Ultra Path Interconnect (UPI) link speed. Default is auto, which configures the optimal link speed automatically. It can be set "9.6 GT/s", "10.4 GT/s" or "Auto".
Max Page Table Size Select
This BIOS switch allows 2 options: "2M" adn "1G". The default is "1G".
This switch selects maximum page table size to use in virtual memory system of OS.
LLC Dead Line Alloc
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled". In the Cascadelake non-inclusive cache scheme, the mid-level cache (MLC) evictions are filled into the last-level cache (LLC). When lines are evicted from the MLC, the core can flag them as "dead" (i.e., not likely to be read again). The LLC has the option to drop dead lines and not fill them in the LLC. If the Dead Line LLC Alloc feature is disabled, dead lines will always be dropped and will never fill into the LLC. This can help save space in the LLC and prevent the LLC from evicting useful data. However, if the Dead Line LLC Alloc feature is enabled, the LLC can opportunistically fill dead lines into the LLC if there is free space available.
LLC Prefetcher
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Enabled".
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit(DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance. If this prefetcher is enabled, the core can prefetch data directly to the LLC and if disabled, the other core prefetchers are unaffected.
Local/Remote Threshold
This BIOS switch allows 5 options: "Disable", "Auto", "Low", "Medium", and "High". PRIMEQUEST servers doen't have options of "Disable", "Medium", and "High". The default is "Auto".
This BIOS option changes the threshold number of requests in remote/local-to-remote request queues to cause the throttling.
Override OS Energy Performance
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Disabled". The power control unit (PCU) in the processors takes on the central role of controlling the energy-saving options. The PCU can be parameterized in order to consequently control the settings more in the direction of energy efficiency or in the direction of maximum performance. The default setting allows you to control energy-saving options through the operating system by its power plan. If enabled, PCU overrides the setting of the operating system and controls the energy-saving options based on the settings in the BIOS.
P-State Coordination
This BIOS switch allows 3 options: "HW_ALL", "SW_ALL", and "SW_ANY". The default is "HW_ALL". This switch controls how BIOS communicates the P-state support model to the operating system.
If this switch is set to "HW_ALL", the processor hardware is responsible for coodinating the P-state among logical processors in a package. If this is set to "SW_ALL", operating system power management is responsible for coordinating P-state among logical processors and must initiate the transition on all of the logical processors. And if "SW_ANY" is selected, operating system power management is responsible for coordinating the P-state among logical processors and may initiate the transistion on any of the logical processors in the domain.
Package C State limit
This BIOS option allows 6 options: "C0", "C2", "C6", "C6(Retention)", "No Limit" and "Auto". The default setting is "Auto". Package C-states is one of energy-saving options of the processor, which not only allow the individual cores of a processor, but the entire processor chip to be put into a type of sleep state. As a result, power consumption is even further reduced. But the "waking-up time" that is required to change from the lower package C-states to the active (C0) state is even longer in comparison with the CPU or core C-states. If the "C0" setting is made in the BIOS, the processor chip always remains active. It can improve the performance of latency sensitive workloads.
Patrol Scrub
This BIOS option enables or disables the so-called memory scrubbing, which cyclically accesses the main memory of the system in the background regardless of the operating system in order to detect and correct memory errors in a preventive way. The time of this memory test cannot be influenced and can under certain circumstances result in losses in performance. The disabling of the Patrol Scrub option increases the probability of discovering memory errors in case of active accesses by the operating system. Until these errors are correctable, the ECC technology of the memory modules ensures that the system continues to run in a stable way. However, too many correctable memory errors increase the risk of discovering non-correctable errors, which then result in a system standstill.
Power Technology
This BIOS switch allows 3 options: "Disabled", "Energy Efficient" and "Custom". The default setting is "Energy Efficient" (PRIMERGY CX servers), or "Custom" (PRIMEQUEST servers).
The BIOS option "Power Technology" is a superset of different BIOS options, which control the performance and power management functions of the processors. In order to see and individually set the corresponding relevant options, select the setting "Custom".
Stale AtoS (Directory AtoS)
This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Disabled".
The in-memory directory has three states: I, A, and S. I (invalid) state means the data is clean and does not exist in any other socket's cache. A (snoopAll) state means the data may exist in another socket in exclusive or modified state. S (Shared) state means the data is clean and may be shared across one or more socket's caches.
When doing a read to memory, if the directory line is in the A state we must snoop all the other sockets because another socket may have the line in modified state. If this is the case, the snoop will return the modified data. However, it may be the case that a line is read in A state and all the snoops come back a miss. This can happen if another socket read the line earlier and then silently dropped it from its cache without modifying it.
If Stale AtoS feature is enabled, in the situation where a line in A state returns only snoop misses, the line will transition to S state. That way, subsequent reads to the line will encounter it in S state and not have to snoop, saving latency and snoop bandwidth. Stale AtoS may be beneficial in a workload where there are many cross-socket reads.
Sub NUMA Clustering
Sub NUMA Clustering (SNC) breaks up the last-level cache (LLC) into two disjoint clusters based on address range, with each cluster bound to one memory controller. SNC improves average latency to the LLC/memory and is a replacement for the "Cluster On Die" (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA domains. IMC Interleaving must be set to the correct value to correspond with SNC enable/disable. If SNC and IMC Interleave are both set to Auto, the result will be SNC disabled (only one cluster per socket) with 2-way IMC interleave. If SNC is set to Enable, IMC Interleave should be set to 1-way, which will result in two clusters per socket. The BIOS switch "Sub NUMA Clustering" allows 3 options: "auto", "enabled" and "disabled". The default setting is "Enabled" (PRIMERGY servers), or "auto" (PRIMEQUEST servers).
Uncore Frequency Override:
This BIOS switch allows 4 options: "Disabled", "Maximum", "Nominal", and "Power balanced". The default is "Disabled" optimized for energy efficiency. "Maximum" sets the uncore frequency to the fixed maximum uncore frequency available. "Nominal" reduces the uncore frequency to the nominal value.
Setting this option to "Maximum" may improve performance but also increase the power consumption of the system. Users should only select this option after performing application benchmarking to verify improved performance in their environment.
Uncore Frequency Scaling:
This BIOS switch allows 2 options: "Disabled" and "Enabled". The default is "Enabled" which sets the uncore frequency to the fixed maximum uncore frequency available. "Disabled" ensures that the uncore frequency is regulated by CPU itself.
Default setting of "Enabled" may improve performance but also increase the power consumption of the system. Users should only select this option after performing application benchmarking to verify improved performance in their environment.
UPI Link Frequency Select:
See "Link Frequency Select".
UPI Link L0p
This BIOS switch allows 3 options: "Auto", "Disabled", and "Enabled". The default setting is "Auto" (PRIMERGY servers) or "Enabled" (PRIMEQUEST servers).
This switch enables or disables Intel Ultra Path Interconnect (UPI) link L0p state for power saving.
UPI Link L1
This BIOS switch allows 3 options: "Auto", "Disabled", and "Enabled". The default setting is "Auto" (PRIMERGY servers) or "Enabled" (PRIMEQUEST servers).
This switch enables or disables Intel Ultra Path Interconnect (UPI) link L1 state for power saving.
Utilization Profile:
This BIOS switch allows 2 options: "Even" and "Unbalanced". The default is "Even" and the best choice for all workloads utilizing the whole system. In cases where the utilization is highly concentrated on few resources of the system the performance of the application could be improved by setting to "Unbalanced".
Setting this option to "Unbalanced" may improve performance but also increase the power consumption of the system. Users should only select this option after performing application benchmarking to verify improved performance in their environment.
VT-d
This BIOS option enables or disables I/O virtualization functions of the CPU. If the server is not used for virtualization, this option should be set to "Disabled". Default setting is "Enabled".
WR CRC Feature Control
See "DDR4 Write Data CRC Protection".
XPT Prefetch
This BIOS switch allows 3 options: "Disabled", "Enabled", and "Auto". The default is "Enabled".
The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic19.0-official-linux64.2019-01-15.html,
http://www.spec.org/cpu2017/flags/Fujitsu-Platform-Settings-V1.0-CSL-RevE.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic19.0-official-linux64.2019-01-15.xml,
http://www.spec.org/cpu2017/flags/Fujitsu-Platform-Settings-V1.0-CSL-RevE.xml.

For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2019 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.0.5.
Report generated on 2019-10-15 14:40:37 by SPEC CPU2017 flags formatter v5178.