This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Intel Turbo boost Technology, Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.
The Intel Hyper-Threading knob has been renamed Enable LP [Global] to represent the number of logical processors (LP). Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.
ALL LPs: Hyper-Threading is enabled, each physical processor core functions as two logical processor cores.
Single LP: Run a single logical processor per core.
Values for this BIOS setting can be:
Custom: Allows the user to setup all of the BIOS options according to their requirement.
Performance: Maximize the performance of the server.
Efficiency: Maximize the power efficiency of the server.
Load Balance: The system's performance and power consumption will be adjusted automatically according to the loading.
Enable or disable reporting of the CPU C6 State (ACPI C3) to the OS.
When set to Enabled, the processor is allowed to switch to nimimum performance and save power when idle.
Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range,with each cluster bound to a subset of the memory controllers in the system.It improves average latency to the LLC.
Values for this BIOS option can be:
Disabled: SNC disabled will support 1-cluster and 4-way IMC interleave.
Enable SNC2 (2-clusters): SNC2 Enabled supports 2-clusters SNC and 2-way IMC interleave.
Enable SNC4 (4-clusters): SNC4 Enabled supports 4-clusters SNC and 1-way IMC interleave.
The last level cache (LLC) prefetch is a prefetcher added to the Intel Xeon Scalable processor family as a result of the non-inclusive cache architecture. The LLC prefetcher is an additional prefetch mechanism on top of the existing prefetchers that prefetch data into the core Data Cache Unit (DCU) and Mid-Level Cache (MLC or second-level cache (L2)). Enabling LLC prefetch gives the core prefetcher the ability to prefetch data directly into the LLC without necessarily filling into the L1 and L2 cache. In some cases, setting this option to disabled can improve performance.
Values for this BIOS option can be:
Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.
Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
Adaptive Double Device Data Correction (ADDDC), which is an enhanced feature to DDDC. This function is used to correct data errors on two memory particles, ADDDC still has single-particle multi-bit error correction capability after the first particle failure occurs and is replaced.
Values for this BIOS option can be:
Enabled: Enable the ADDDC Sparing function.
Disabled: Disable the ADDDC Sparing function.
LLC dead line allocation. The processor marks the row replaced by the MLC as dead, indicating that the row will not be read again. This function is used to set the allocation policy for the data marked as dead in the LLC.
Values for this BIOS option can be:
Enabled: Allows the LLC to fill dead lines into the LLC if there is free space.
Disabled: The dead lines are dropped and are never filled into the LLC, saving the LLC space.
The in-memory directory has three states: invalid (I), snoopAll (A), and shared (S). Invalid (I) state means the data is clean and does not exist in any other socket`s cache. The snoopAll (A) state means the data may exist in another socket in exclusive or modified state. Shared (S) state means the data is clean and may be shared across one or more socket`s caches. When doing a read to memory, if the directory line is in the A state we must snoop all the other sockets because another socket may have the line in modified state. If this is the case, the snoop will return the modified data. However, it may be the case that a line is read in A state and all the snoops come back a miss. This can happen if another socket read the line earlier and then silently dropped it from its cache without modifying it.
Values for this BIOS option can be:
Auto: The SnoopAll (A) state is used by default. During uncore post MRC, the state is reconfigured based on the setup knob, number of sockets, and BPS memory.
Enabled: The SnoopAll (A) state is changed to the Shared (S) state.
Disabled: The SnoopAll (A) state is used.