SPEC CPU2017 Platform Settings for Lenovo Systems

Operating System Tuning Parameters

sched_cfs_bandwidth_slice_us

This OS setting controls the amount of run-time(bandwidth) transferred to a run queue from the task's control group bandwidth pool. Small values allow the global bandwidth to be shared in a fine-grained manner among tasks, larger values reduce transfer overhead. The default value is 5000 (ns).

sched_latency_ns

This OS setting configures targeted preemption latency for CPU bound tasks. The default value is 24000000 (ns).

sched_migration_cost_ns

Amount of time after the last execution that a task is considered to be "cache hot" in migration decisions. A "hot" task is less likely to be migrated to another CPU, so increasing this variable reduces task migrations. The default value is 500000 (ns).

sched_min_granularity_ns

This OS setting controls the minimal preemption granularity for CPU bound tasks. As the number of runnable tasks increases, CFS(Complete Fair Scheduler), the scheduler of the Linux kernel, decreases the timeslices of tasks. If the number of runnable tasks exceeds sched_latency_ns/sched_min_granularity_ns, the timeslice becomes number_of_running_tasks * sched_min_granularity_ns. The default value is 8000000 (ns).

sched_wakeup_granularity_ns

This OS setting controls the wake-up preemption granularity. Increasing this variable reduces wake-up preemption, reducing disturbance of compute bound tasks. Lowering it improves wake-up latency and throughput for latency critical tasks, particularly when a short duty cycle load component must compete with CPU bound components. The default value is 10000000 (ns).

numa_balancing

This OS setting controls automatic NUMA balancing on memory mapping and process placement. Setting 0 disables this feature. It is enabled by default (1).

Firmware / BIOS / Microcode Settings

Choose Operating Mode: (Default="Maximum Efficiency")

Select the operating mode based on your preference. Note, power savings and performance are also highly dependent on hardware and software running on system.

• "Maximum Efficiency" 'Efficiency' balances performance and power consumption.
• "Maximum Performance"'Performance' maxmizes performance minimizes latency with little regard to power consumption.
• "Custom Mode" When a preset mode is selected, the low-level settings are not changeable and will be grayed out. If user would like to change the settings, please choose Custom Mode.

Determinism Slider:

• "Performance" When set to Performance, performance is more predictable (deterministic) and operates at the lowest common denominator among the cores. But aggregate peak performance may be reduced. Aggregate performance may be higher, but predictability is lower.
• "Power" When set to Power, cores can scale frequency independently.

Global C-state Control:

Controls IO based C-state generation and DF C-states.

cTDP:

Sets the maximum power consumption for CPU. cTDP is only configurable before OS boot.

• "Auto" Sets cTDP=TDP for the installed CPU SKU.
• "Maximum" Maximum sets the maximum allowed cTDP value for the installed CPU SKU.
• "Manual" Usually, maximum is greater than TDP. If a manual value is entered that is larger than the max value allowed, the value will be internally limited to the maximum allowable value.

cTDP Manual:

cTDP is the acronym for Configurable TDP. Some Rome CPU skus support a default TDP and a higher cTDP expressed in Watts. Model Normal TDP Minimum cTDP Maximum cTDP EPYC 7H12 280 225 280 EPYC 7742 225 225 240 EPYC 7702 200 165 200 EPYC 7702P 200 165 200 EPYC 7662 225 225 240 EPYC 7642 225 225 240 EPYC 7502 180 165 200 EPYC 7502P 180 165 200 EPYC 7542 225 225 240 EPYC 7402 180 165 200 EPYC 7402P 180 165 200 EPYC 7302 155 155 180 EPYC 7302P 155 155 180 EPYC 7252 120 120 150

Memory Speed:

Select the desired memory speed. Faster speeds offer better performance but consume more power.

NUMA nodes per socket:

Specifies the number of desired NUMA nodes per socket. Zero will attempt to interleave the two sockets together.

• "NPS2"NPS2 sets two NUMA nodes per socket, one per Left/Right Half of the SoC.
• "NPS4"NPS4 sets four NUMA nodes per socket, one per Quadrant.

Package Power Limit Control:

Auto = Use the fused PPT\nManual = User can set customized PPT\n***PPT will be used as the ASIC power limit***

SMT Mode:

Can be used to disable symmetric multithreading. To re-enable SMT, a POWER CYCLE is needed after selecting Enable.

CCD Control:

Sets the number of CCDs to be used. Once this option has been used to remove any CCDs, a POWER CYCLE is required in order for future selections to take effect.

Efficiency Mode:

This setting enables an energy efficient mode of operation internal to AMD EPYC Gen2 processors at the expense of performance. The settings should be enabled when energy efficient operation is desired from the processor.

• "Disable" Use performance optimized CCLX DPM settings
• "Enable(default)"Use power efficiency optimized CCLX DPM settings

LCC as NUMA Node:

Exposes the processor's last level caches as NUMA nodes. When enabled, can improve performance for highly NUMA optimized workloads if workloads or components of workloads can be pinned into the caches.

Zero Output:

When zero output is set to 'Advanced mode' and multiple power supplies are installed in the server, some of the PSUs will be automatically placed into a low power state under light load conditions. This helps to save power

SOC P-states:

When Auto is selected the CPU SOC P-states(uncore P-states) will be dynamically adjusted. That is, their frequency will dynamically change based on the workload. Selecting P0, P1, P2, or P3 forces the SOC to a specific P-state frequency.

L1 Stream HW Prefetcher:

Enable/Disable L1 Stream HW Prefetcher. Fetches the next cache line int to the L1 cache when cached lines are reused within a certain time period or accessed sequentially.

L2 Stream HW Prefetcher:

Enable/Disable L2 Stream HW Prefetcher. Fetches the next cache line int to the L2 cache when cached lines are reused within a certain time period or accessed sequentially.