C States:
C States allow the processor to enter lower power states when idle. When set to Enabled (OS controlled) or when set to Autonomous (if Hardware controlled is supported), the processor can operate in all available Power States to save power, but my increase memory latency and frequency jitter.
Determinism Slider:
It controls whether BIOS will enable determinism to control performance. Performance: BIOS will enable 100% deterministic performance control. Power: BIOS will not enable deterministic performance control.
CPU Power Management set to Maximum Performance:
Allows selection of CPU power management methodology. Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C0state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred for latency-sensitive environments. OS DBPM is another performance-per-watt option that relies on the operating system to dynamically control individual cores in order to save power.
Memory Frequency set to Maximum Performance:
Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance. Read-only unless System Profile is set to Custom.
Efficiency Optimized Mode Disabled:
This field enables/disabled Efficiency Optimized Mode. Efficiency Optimized Mode maximizes Performance-per-Watt by opportunistically reducing frequency/power.
NUMA Nodes Per Socket:
This field specifies the number of NUMA nodes per socket. The Zero option is for 2 socket configurations.
CCX as NUMA Domain:
This field specifies that each CCX within the processor will be declared as a NUMA Domain.
Adaptive Double DRAM Device Correction (ADDDC):
When Adaptive Double DRAM Device Correction (ADDDC) is enabled, failing DRAM’s are dynamically mapped out. When set to enabled, it can have some impact to system performance under certain workloads. This feature is applicable for x4 DIMMs only.
DCU Streamer Prefetcher:
Enables or disables Data Cache Unit (DCU) Streamer Prefetcher. This setting can affect performance, depending on the application running on the server. DCU streamer prefetchers detect multiple reads to a single cache line in a certain period of time and choose to load the following cache line to the L1 data caches. Recommended for High Performance Computing applications.
Memory Frequency:
Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance.
Turbo Boost:
Governs the Boost Technology. This feature allows teh processor cores to be automatically clocked up in frequency beyond the advertised processor speed. The amount of increased frequency (or 'turbo upside') one can expect from an EPYC processor depends on the fewer cores being exercised with work the higher the potential turbo upside. The potential drawback for Boost are mainly centered on increased power consumption and possible frequency jitter that can affect a small minority of latency-sensitive environments.
C1E:
When set to Enabled, the processor is allowed to switch to minimum performance state when idle.
CPU Interconnect Bus Link Power Management:
When Enabled, CPU interconnect bus link power management can reduce overall system power a bit while slightly reducing system performance.
CPU Performance:
Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C-state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred.
Energy Efficient Policy:
The CPU uses the setting to manipulate the internal behavior of the processor and determines
whether to target higher performance or better power savings. The possible settings are: Performance, Balanced Performance, Balanced Energy, Energy Efficient.
Energy Efficient Turbo:
Permits Energy Efficient Turbo to be Enabled or Disabled.
Energy Efficient Turbo (EET) is a mode of operation where a processor's core frequency is adjusted within the turbo range based on workload.
Logical Processor:
Each processor core supports up to two logical processors. When set to Enabled, the BIOS reports all logical processors. When set to Disabled, the BIOS only reports one logical processor per core. Generally, higher processor count results in increased performance for most multi-threaded workloads and the recommendation is to keep this enabled. However, there are some floating point/scientific workloads, including HPC workloads, where disabling this feature may result in higher performance.
Memory Patrol Scrub:
Patrol Scrubbing searches the memory for errors and repairs correctable errors to prevent the accumulation of memory errors. When set to Disabled, no patrol scrubbing will occur. When set to Standard Mode, the entire memory array will be scrubbed once in a 24 hour period. When set to Extended Mode, the entire memory array will be scrubbed more frequently to further increase system reliability.
Memory Refresh Rate:
The memory controller will periodically refresh the data in memory. The frequency at which memory is normally refreshed is referred to as 1X refresh rate. When memory modules are operating at a higher than normal temperature or to further increase system reliability, the refresh rate can be set to 2X, but may have a negative impact on memory subsystem performance under some circumstances.
PCI ASPM L1 Link Power Management:
When Enabled, PCIe Advanced State Power Management (ASPM) can reduce overall system power
a bit while slightly reducing system performance.
NOTE: Some devices may not perform properly (they may hang or cause the system to hang)
when ASPM is enabled, for this reason L1 will only be enabled for validated qualified cards.
System Profile:
When set to Custom, you can change setting of each option. Under Custom mode when C States is enabled, Monitor/Mwait should also be Enabled.
Monitor/Mwait:
Specifies whether Monitor/Mwait instructions are enabled. Monitor/Mwait is only active when C States is set to Disabled.
Sub NUMA Cluster:
When Enabled, Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. It improves average latency to the LLC.
Uncore Frequency:
Selects the Processor Uncore Frequency.
Dynamic mode allows processor to optimize power resources across the cores and uncore during runtime.
The optimization of the uncore frequency to either save power or optimize performance is influenced
by the setting of the Energy Efficient Policy.
Virtualization technology:
When set to Enabled, the BIOS will enable processor Virtualization features and provide the virtualization support to the Operating System (OS) through the DMAR table. In general, only virtualized environments such as VMware(r) ESX (tm), Microsoft Hyper-V(r) , Red Hat(r) KVM, and other virtualized operating systems will take advantage of these features. Disabling this feature is not known to significantly alter the performance or power characteristics of the system, so leaving this option Enabled is advised for most cases.
nohz_full:
This kernel option sets adaptive tick mode (NOHZ_FULL) to specified processors. Since the number of interrupts is reduced to ones per second, latency-sensitive applications can take advantage of it.
Memory Interleaving:
When Enabled, memory interleaving is supported if a symmetric memory configuration is installed. When set to Disabled, the system supports Non-Uniform Memory Access (NUMA) (asymmetric) memory configurations. Channel interleaving is available with all configurations and is the intra-die memory interleave option. With channel interleaving the memory behind each UMC will be interleaved and seen as 1 NUMA domain per die.