SPEC CPU2006 Platform Settings for Intel-based systems

Shell, Environment, and Other Software Settings

OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -openmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
ulimit -s <n>
Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

Firmware / BIOS / Microcode Settings

Hardware Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Adjacent Sector Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Adjacent Cache Line Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
L1 Data Prefetch: Enabled:
This BIOS option allows the enabling/disabling L1 cache Data prefetch.
C-State : Disabled
Enable/Disable CPUs to enter C-State (lower power CPU state) while the system is idle. This helps to lower power consumption when enabled.
Data Reuse Optimization : Disabled
Enabling this BIOS option reduces the frequency of L3 cache updates from L1. This may improve performance by reducing the internal bandwidth consumed by constantly updating L1 cache lines in L3. Since this results in more fetches to main memory, setting this option to Disabled may improve performance in some cases. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Intel HT Technology : Disabled
This BIOS setting disables/enables Intel Hyper-Threading (HT) Technology. With Intel HT Technology, the operating system can execute two threads in parallel within each processor core.