SPEC CPU2006 Software OS and BIOS tuning Descriptions for Servidor Itautec Intel-based systems
- Platform settings
- One or more of the following settings may have been set. If so, the "General Notes"
section of the report will say so; and you can read below to find out more about what
these settings mean.
- Hardware Prefetch:
-
This BIOS option allows the enabling/disabling of a processor mechanism to
prefetch data into the cache according to a pattern-recognition algorithm.
In some cases, setting this option to Disabled may improve
performance. Users should only disable this option
after performing application benchmarking to verify improved
performance in their environment.
- Adjacent Cache Line Prefetch:
-
This BIOS option allows the enabling/disabling of a processor mechanism to
fetch the adjacent cache line within a 128-byte sector that contains
the data needed due to a cache line miss.
In some cases, setting this option to Disabled may improve
performance. Users should only disable this option
after performing application benchmarking to verify improved
performance in their environment.
- DCU prefetcher:
- Detects multiple reading from a single cache line for a determined period of time
and decides to load the following line in the L1 cache.
In some cases, setting this option to Disabled may improve
performance. Users should only disable this option
after performing application benchmarking to verify improved
performance in their environment.
- Data Reuse:
-
Enabling this BIOS option reduces the frequency of L3 cache updates from L1.
This may improve performance by reducing the internal bandwidth consumed
by constantly updating L1 cache lines in L3.
Since this results in more fetches to main memory,
setting this option to Disabled may improve performance in some cases.
In some cases, setting this option to Disabled may improve
performance. Users should only disable this option
after performing application benchmarking to verify improved
performance in their environment.
- High Bandwidth:
-
Enabling this option allows the chipset to defer memory transactions and
process them out of order for optimal performance.
- Logical Processor:
-
This BIOS setting enables/disables Intel's Hyper-Threading (HT) Technology.
With HT Technology, the operating system can execute two threads in parallel
within each processor core.
- Node Interleaving:
-
This BIOS option allows the enabling/disabling of memory interleaving across
CPU nodes. When disabled, each CPU chip can only access memory within its own node.