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Selecting one of the following will take you directly to that section:
Enables optimizations for speed and disables some optimizations that
increase code size and affect speed.
To limit code size, this option:
- Enables global optimization; this includes data-flow analysis,
code motion, strength reduction and test replacement, split-lifetime
analysis, and instruction scheduling.
- Disables intrinsic recognition and intrinsics inlining.
The O1 option may improve performance for applications with very large
code size, many branches, and execution time not dominated by code within loops.
On IA-32 Windows platforms, -O1 sets the following:
/Qunroll0, /Oi-, /Op-, /Oy, /Gy, /Os, /GF (/Qvc7 and above), /Gf (/Qvc6 and below), /Ob2, and /Og
Enables optimizations for speed. This is the generally recommended
optimization level. This option also enables:
- Inlining of intrinsics
- Intra-file interprocedural optimizations, which include:
- inlining
- constant propagation
- forward substitution
- routine attribute propagation
- variable address-taken analysis
- dead static function elimination
- removal of unreferenced variables
- The following capabilities for performance gain:
- constant propagation
- copy propagation
- dead-code elimination
- global register allocation
- global instruction scheduling and control speculation
- loop unrolling
- optimized code selection
- partial redundancy elimination
- strength reduction/induction variable simplification
- variable renaming
- exception handling optimizations
- tail recursions
- peephole optimizations
- structure assignment lowering and optimizations
- dead store elimination
On IA-32 Windows platforms, -O2 sets the following:
/Og, /Oi-, /Os, /Oy, /Ob2, /GF (/Qvc7 and above), /Gf (/Qvc6 and below), /Gs, and /Gy.
Enables O2 optimizations plus more aggressive optimizations,
such as prefetching, scalar replacement, and loop and memory
access transformations. Enables optimizations for maximum speed,
such as:
- Loop unrolling, including instruction scheduling
- Code replication to eliminate branches
- Padding the size of certain power-of-two arrays to allow
more efficient cache use.
On IA-32 and Intel EM64T processors, when O3 is used with options
-ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler
performs more aggressive data dependency analysis than for O2, which
may result in longer compilation times.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets. On IA-32
Windows platforms, -O3 sets the following:
/GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2
This option enables additional interprocedural optimizations for single file compilation. These optimizations are a subset of full intra-file interprocedural optimizations. One of these optimizations enables the compiler to perform inline function expansion for calls to functions defined within the current source file.
Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion
The -fast option enhances execution speed across the entire program by including the following options that can improve run-time performance:
-O3 (maximum speed and high-level optimizations)
-Qipo (enables interprocedural optimizations across files)
-QxP (generate code specialized for Intel Pentium 4 processor and compatible Intel processors with Streaming SIMD Extensions 3)
-Qprec-div- (disable -Qprec-div) where -Qprec-div improves precision of FP divides (some speed impact)
To override one of the options set by /fast, specify that option after the -fast option on the command line. The exception is the xP or QxP option which can't be overridden. The options set by /fast may change from release to release.
Code is optimized for Intel Core Duo processors, Intel Core Solo processors, Intel Pentium 4 processors with Streaming SIMD Extensions 3, and compatible Intel processors with Streaming SIMD Extensions 3. The resulting code may contain unconditional use of features that are not supported on other processors. This option also enables new optimizations in addition to Intel processor-specific optimizations including advanced data layout and code restructuring optimizations to improve memory accesses for Intel processors.
Do not use this option if you are executing a program on a processor that is not an Intel processor. If you use this option on a non-compatible processor to compile the main program (in Fortran) or the function main() in C/C++, the program will display a fatal run-time error if they are executed on unsupported processors.
Optimizes for Intel Pentium 4 and compatible processors with Streaming SIMD Extensions 2 (SSE2).
-Qprec-dev improves precision of floating-point divides. It has a slight impact on speed. -Qprec-dev- disables this option and enables optimizations that give slightly less precise results than full IEEE division.
When you specify -Qprec-dev- along with some optimizations, such as -xN and -xB (Linux) or /QxN and /QxB (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.
However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, do not use -Qprec-dev- which will enable the default -Qprec-dev and the result is more accurate, with some loss of performance.
Instrument program for profiling for the first phase of two-phase profile guided otimization. This instrumentation gathers information about a program's execution paths and data values but does not gather information from hardware performance counters. The profile instrumentation also gathers data for optimizations which are unique to profile-feedback optimization.
Instructs the compiler to produce a profile-optimized
executable and merges available dynamic information (.dyn)
files into a pgopti.dpi file. If you perform multiple
executions of the instrumented program, -Qprof_use merges
the dynamic information files again and overwrites the
previous pgopti.dpi file.
Without any other options, the current directory is
searched for .dyn files
Enable C++ Exception Handling and RTTI
This option has the same effect as specifying /GX /GR.
This option enables C++ exception handling.
Enables C++ Run Time Type Information (RTTI).
Enable SmartHeap library usage by forcing the linker to ignore multiple definitions
Enable SmartHeap library usage by forcing the linker to ignore multiple definitions
MicroQuill SmartHeap Library 8.0 available from http://www.microquill.com/
set the stack reserve amount specified to the linker
Tells the compiler the maximum number of times to unroll loops.
Disables inline expansion of all intrinsic functions.
Disables conformance to the ANSI C and IEEE 754 standards for floating-point arithmetic.
Allows use of EBP as a general-purpose register in optimizations.
This option enables most speed optimizations, but disables some that increase code size for a small speed benefit.
This option enables global optimizations.
Specifies the level of inline function expansion.
Ob0 - Disables inlining of user-defined functions. Note that statement functions are always inlined.
Ob1 - Enables inlining when an inline keyword or an inline attribute is specified. Also enables inlining according to the C++ language.
Ob2 - Enables inlining of any function at the compiler's discretion.
This option tells the compiler to separate functions into COMDATs for the linker.
This option enables read only string-pooling optimization.
This option enables read/write string-pooling optimization.
This option disables stack-checking for routines with 4096 bytes of local variables and compiler temporaries.
For mixed-language benchmarks, tell the compiler to convert routine names to lowercase for compatibility
For mixed-language benchmarks, tell the compiler to assume that routine names end with an underscore
Tell the compiler to treat source files as C++ regardless of the file extension
Invoke the Intel C++ compiler for 32 bit applications
Invoke the Intel Fortran compiler for 32 bit applications
Invoke the Intel C++ compiler in C99 mode
Invoke the Intel C++ compiler in .Net 2003 compatibility mode
Memory Array Setting:
High Redundant Bit Steering (RBS)(default setting):
This option enables Memory ProteXion and is the default/standard setting.
Select RBS if you are not using mirroring, hot-swap, or hot-add. Redundant
bit steering is the technical term for Memory ProteXion.
When a single bit in a memory DIMM fails, the function known as redundant bit
steering (RBS) automatically moves the affected bit to an unused bit in the
memory array, removing the need to perform the ECC correction and thereby
returning the memory subsystem to peak performance. The number of RBS
actions that can be performed depends on the type of DIMMs installed in the
server
Full Array Memory Mirroring (FAMM):
Select FAMM to enable memory mirroring (and to enable hot-swap).
Memory mirroring reduces the amount of addressable memory by half on
each chassis in the partition, but provides complete redundancy of all
addressable memory. RBS is available in this mode.
Hot-Add Memory (HAM):
Select HAM to enable the use of the hot-add in the future.
HAM provides an array layout that supports runtime hot memory add within
an OS that supports that feature. This setting has lower performance and may
also restrict the amount of memory that can be installed in each chassis, as
addressable ranges must be reserved on each chassis for the hot add
function. RBS is available in this mode.
High Performance Memory Array (HPMA):
HPMA optimizes the installed memory array on each chassis in the partition
for maximum memory performance. Hardware correction (ECC) of a single
correctable error per chip select group (CSG) is provided, but RBS is not
available.
Hardware Prefetch:
Enables a processor mechanism that automatically fetches
data and instructions into the unified second-level cache.
Enabling this feature can result in higher performance on
some applications and operating systems. Disabled by default.