SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2007 Standard Performance Evaluation Corporation
Hewlett-Packard Company
ProLiant DL380 G5 (1.86 GHz, Intel Xeon processor E5320)
SPECint_rate2000 = 148    
SPECint_rate_base2000 = 148    
SPEC license # 3 Tested by: Hewlett-Packard Company Test date: Feb-2007 Hardware Avail: Nov-2006 Software Avail: Nov-2006
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (102)
164.gzip peak result bar (103)		 164.gzip 8 127    102     8 126    103    
175.vpr base result bar (107)
175.vpr peak result bar (108)		 175.vpr 8 122    107     8 120    108    
176.gcc base result bar (166)
176.gcc peak result bar (166)		 176.gcc 8 61.4  166     8 61.4  166    
181.mcf base result bar (108)
181.mcf peak result bar (111)		 181.mcf 8 154    108     8 150    111    
186.crafty base result bar (157)
186.crafty peak result bar (157)		 186.crafty 8 59.0  157     8 59.0  157    
197.parser base result bar (128)
197.parser peak result bar (128)		 197.parser 8 131    128     8 131    128    
252.eon base result bar (223)
252.eon peak result bar (224)		 252.eon 8 54.0  223     8 53.8  224    
253.perlbmk base result bar (198)
253.perlbmk peak result bar (199)		 253.perlbmk 8 84.3  198     8 83.8  199    
254.gap base result bar (109)
254.gap peak result bar (110)		 254.gap 8 93.4  109     8 93.2  110    
255.vortex base result bar (255)
255.vortex peak result bar (255)		 255.vortex 8 69.2  255     8 69.3  255    
256.bzip2 base result bar (110)
256.bzip2 peak result bar (110)		 256.bzip2 8 127    110     8 127    110    
300.twolf base result bar (201)
300.twolf peak result bar (201)		 300.twolf 8 139    201     8 139    201    
  SPECint_rate_base2000 148      
  SPECint_rate2000 148    

Hardware
Hardware Vendor: Hewlett-Packard Company
Model Name: ProLiant DL380 G5 (1.86 GHz, Intel Xeon processor E5320)
CPU: Intel Xeon processor E5320 (1.86 GHz, 2x4 MB L2 shared, 1066 MHz bus)
CPU MHz: 1860
FPU: Integrated
CPU(s) enabled: 8 cores, 2 chips, 4 cores/chip
CPU(s) orderable: 1,2 chips
Parallel: No
Primary Cache: 32 KB I + 32 KB D on chip per core
Secondary Cache: 8 MB I+D on chip per chip (4 MB shared per 2 cores)
L3 Cache: N/A
Other Cache: N/A
Memory: 16 GB (8x2 GB PC2-5300F CL5)
Disk Subsystem: 4x36 GB 10 K SAS
Other Hardware:
Software
Operating System: Windows Server 2003 Enterprise X64 Edition SP1
Compiler: Intel C++ Compiler for 32-bit applications,
(Version 9.1 Build 20061103Z)
Microsoft Visual Studio .NET 2003 (v7.1.3088, for libraries)
MicroQuill Smartheap Library 8.0
File System: NTFS
System State: Default
Notes / Tuning Information 
 +FDO: PASS1=-Qprof_gen  PASS2=-Qprof_use

 Base tuning for C programs:   -fast         +FDO  ONESTEP=yes shlw32M.lib
 Base tuning for C++ programs: -fast -Qcxx_features +FDO  ONESTEP=yes
 Portability flags:
   176.gcc: -Dalloca=_alloca /F10000000 
   186.crafty: -DNT_i386
   253.perlbmk: -DSPEC_CPU2000_NTOS -DPERLDLL /MT
   254.gap: -DSYS_HAS_CALLOC_PROTO -DSYS_HAS_MALLOC_PROTO
 Peak tuning:
   164.gzip:     -fast               +FDO  ONESTEP=yes 
   175.vpr:      -fast               +FDO  ONESTEP=yes
   176.gcc:      basepeak=1
   181.mcf:      -fast               +FDO  
   186.crafty:   -fast -Oa           +FDO  ONESTEP=yes shlw32M.lib 
   197.parser:   -fast               +FDO  ONESTEP=yes
   252.eon:      -fast               +FDO
   253.perlbmk:  -fast -Oa           +FDO  ONESTEP=yes shlw32M.lib
   254.gap:      -fast               +FDO  ONESTEP=yes
   255.vortex:   -fast               +FDO  ONESTEP=yes shlw32M.lib
   256.bzip2:    basepeak=1
   300.twolf:    -fast               +FDO              shlw32M.lib
 BIOS Configuration Notes
   Power Regulator set to Static High Performance Mode
   Adjacent Sector Prefetch disabled
 Other Configuration Notes
   The start /b /wait /affinity command is used to bind CPU(s) to processes.

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Copyright © 1999-2007 Standard Performance Evaluation Corporation

First published at SPEC.org on 20-Mar-2007

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