SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2005 Standard Performance Evaluation Corporation
IBM Corporation
IBM System p5 550Q (1500 MHz, 8 CPU)
SPECint_rate2000 = 124    
SPECint_rate_base2000 = 122    
SPEC license # 11 Tested by: IBM Test date: Sep-2005 Hardware Avail: Oct-2005 Software Avail: Oct-2005
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (84.4)
164.gzip peak result bar (84.4)		 164.gzip 16 308    84.4   16 308    84.4  
175.vpr base result bar (105)
175.vpr peak result bar (104)		 175.vpr 16 248    105     16 249    104    
176.gcc base result bar (132)
176.gcc peak result bar (131)		 176.gcc 16 155    132     16 156    131    
181.mcf base result bar (175)
181.mcf peak result bar (178)		 181.mcf 16 191    175     16 188    178    
186.crafty base result bar (95.5)
186.crafty peak result bar (95.5)		 186.crafty 16 194    95.5   16 194    95.5  
197.parser base result bar (120)
197.parser peak result bar (120)		 197.parser 16 278    120     16 279    120    
252.eon base result bar (137)
252.eon peak result bar (142)		 252.eon 16 177    137     16 170    142    
253.perlbmk base result bar (95.6)
253.perlbmk peak result bar (102)		 253.perlbmk 16 349    95.6   16 328    102    
254.gap base result bar (119)
254.gap peak result bar (118)		 254.gap 16 171    119     16 174    118    
255.vortex base result bar (186)
255.vortex peak result bar (212)		 255.vortex 16 189    186     16 166    212    
256.bzip2 base result bar (134)
256.bzip2 peak result bar (138)		 256.bzip2 16 207    134     16 201    138    
300.twolf base result bar (116)
300.twolf peak result bar (116)		 300.twolf 16 481    116     16 481    116    
  SPECint_rate_base2000 122      
  SPECint_rate2000 124    

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM System p5 550Q (1500 MHz, 8 CPU)
CPU: POWER5+
CPU MHz: 1500
FPU: Integrated
CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip (SMT on)
CPU(s) orderable: 4,8
Parallel: None
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 2x36MB unified (off-chip)/QCM, 2 QCM/SUT
Other Cache: None
Memory: 16x4GB
Disk Subsystem: 1x36GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 8.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information 
  Portability Flags:
    176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
    186.crafty:   -DAIX
    252.eon:      srcalt=fmax_errno
    253.perlbmk:  -DSPEC_CPU2000_AIX
    254.gap:      -DSYS_IS_BSD -DSYS_STRING_H
                  -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
    300.twolf:    -DHAVE_SIGNED_CHAR
 
  Base Optimization Flags:
    C:    -qpdf1/pdf2
          -O5 -blpdata -D_ILS_MACROS
    C++:  -qpdf1/pdf2
          -O5 -lhmu -qalign=natural
 
  Peak Optimization Flags
    164.gzip:     basepeak=1
    175.vpr:      -qpdf1/pdf2
                  -O5 -lhmu -blpdata -D_ILS_MACROS
    176.gcc:      -qpdf1/pdf2
                  -O5 -blpdata -qalign=natural -D_ILS_MACROS
    181.mcf:      -O5 -blpdata -qfdpr
                  fdpr -q -O3
    186.crafty:   basepeak=1
    197.parser:   -qpdf1/pdf2
                  -O5 -blpdata -D_ILS_MACROS
    252.eon:      -qpdf1/pdf2
                  -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
    253.perlbmk:  -qpdf1/pdf2
                  -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
    254.gap:      -qpdf1/pdf2
                  -O5 -qalign=natural -lhmu -blpdata -qfdpr -Q
    255.vortex:   -qpdf1/pdf2
                  -O5 -lhmu -blpdata
    256.bzip2:    -O5 -blpdata -qfdpr -D_ILS_MACROS
                  fdpr -q -O3
    300.twolf:    basepeak=1
 
 
  Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
  was used with 252.eon for POSIX-compatibility.

  The installed OS level is AIX 5L for POWER version 5.3 with the 5300-03 Recommended Maintenance package.

  SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
        the simultaneous execution of multiple thread contexts within a single processor
        core. (Enabled by default)
  QCM:  Acronym for "Quad-Core Module" (two dual-core processor chips + two L3-cache chips)
  SUT:  Acronym for "System Under Test"

  Extended C:     IBM XL C for AIX invoked as cc
  ANSI C89:       IBM XL C for AIX invoked as xlc
  C++:            IBM XL C for AIX invoked as xlC

  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
      vmo -r -o lgpg_regions=1600 -o lgpg_size=16777216
      chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
      reboot -q
      export MEMORY_AFFINITY=MCM

  The following config-file entry was used to assign each benchmark process to a core:
       submit = let "MYCPU=2*\$SPECUSERNUM"; if (("\$MYCPU > 15")) then let "MYCPU-=15"; fi; bindprocessor \$\$ \$MYCPU; $command
  The "bindprocessor" AIX command binds a process to a CPU core.

  Use flags-description file IBM-20050919-AIX.txt.

For questions about this result, please contact the tester.
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Copyright © 1999-2005 Standard Performance Evaluation Corporation

First published at SPEC.org on 18-Oct-2005

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