SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
Hewlett-Packard Company
AlphaServer GS1280 7/1150
SPECint2000 = 877    
SPECint_base2000 = 795    
SPEC license # 2 Tested by: HP Test date: Dec-2002 Hardware Avail: Jan-2003 Software Avail: Jan-2003
Benchmark Reference
Time
Base
Runtime
Base
Ratio
Runtime Ratio Graph Scale
164.gzip 1400 240    583     236    592     164.gzip base result bar (583)
164.gzip peak result bar (592)
175.vpr 1400 170    822     165    846     175.vpr base result bar (822)
175.vpr peak result bar (846)
176.gcc 1100 128    859     115    960     176.gcc base result bar (859)
176.gcc peak result bar (960)
181.mcf 1800 253    712     157    1147      181.mcf base result bar (712)
181.mcf peak result bar (1147)
186.crafty 1000 102    982     102    982     186.crafty base result bar (982)
186.crafty peak result bar (982)
197.parser 1800 351    514     277    650     197.parser base result bar (514)
197.parser peak result bar (650)
252.eon 1300 136    958     137    947     252.eon base result bar (958)
252.eon peak result bar (947)
253.perlbmk 1800 234    768     224    805     253.perlbmk base result bar (768)
253.perlbmk peak result bar (805)
254.gap 1100 173    636     153    718     254.gap base result bar (636)
254.gap peak result bar (718)
255.vortex 1900 174    1094      158    1201      255.vortex base result bar (1094)
255.vortex peak result bar (1201)
256.bzip2 1500 182    824     172    872     256.bzip2 base result bar (824)
256.bzip2 peak result bar (872)
300.twolf 3000 295    1018      292    1028      300.twolf base result bar (1018)
300.twolf peak result bar (1028)
SPECint_base2000 795      
  SPECint2000 877      

Hardware
Hardware Vendor: Hewlett-Packard Company
Model Name: AlphaServer GS1280 7/1150
CPU: Alpha 21364
CPU MHz: 1150
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip
CPU(s) orderable: 2 to 16
Parallel: No
Primary Cache: 64KB(I)+64KB(D) on chip
Secondary Cache: 1.75MB on chip per CPU
L3 Cache: None
Other Cache: None
Memory: 4GB
Disk Subsystem: 36GB SCSI
Other Hardware: None
Software
Operating System: Tru64 UNIX V5.1B (Rev. 2650)
+IPK
Compiler: Compaq C V6.5-011-48C5K
Program Analysis Tools V2.0
Spike V5.2 (506A)
Compaq C++ V6.5-028
File System: UFS
System State: Multi-user
Notes / Tuning Information
 Baseline C  : cc  -arch ev7 -fast +CFB ONESTEP 
          C++: cxx -arch ev7 -O2        ONESTEP 
 
 Peak: 
   The following use: -g3 -arch ev7 ONESTEP
       175.vpr 181.mcf 197.parser 253.perlbmk
   
   The following use: -g3 -arch ev6 ONESTEP
       164.gzip 176.gcc 254.gap 255.vortex 256.bzip2 300.twolf
   
   Individual benchmark tuning:
      164.gzip: -fast -O4 -non_shared +CFB 
       175.vpr: -fast -O4 -assume restricted_pointers +CFB 
       176.gcc: -fast -O4 -xtaso_short -all -ldensemalloc -none
                +CFB +IFB 
       181.mcf: -fast -xtaso_short +CFB +IFB +PFB
    186.crafty: same as base
    197.parser: -fast -O4 -xtaso_short -non_shared +CFB
       252.eon: -arch ev7 -O2 -all -ldensemalloc -none 
   253.perlbmk: -fast -non_shared +CFB +IFB 
       254.gap: -fast -O4 -non_shared +CFB +IFB +PFB 
    255.vortex: -fast -non_shared +CFB +IFB
     256.bzip2: -fast -O4 -non_shared +CFB 
     300.twolf: -fast -O4 
                -ldensemalloc -non_shared +CFB +IFB

 Most benchmarks are built using one or more types of 
 profile-driven feedback.  The types used are designated
 by abbreviations in the notes:

 +CFB: Code generation is optimized by the compiler, using 
       feedback from a training run.  These commands are
       done before the first compile (in phase "fdo_pre0"):

            mkdir /tmp/pp
            rm -f /tmp/pp/${baseexe}*

       and these flags are added to the first and second compiles:

            PASS1_CFLAGS = -prof_gen_noopt -prof_dir /tmp/pp
            PASS2_CFLAGS = -prof_use       -prof_dir /tmp/pp
 
      (Peak builds use /tmp/pp above; base builds use /tmp/pb.)

 +IFB: Icache usage is improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These commands
       are used (in phase "fdo_postN"):  

            mv ${baseexe} oldexe
            spike oldexe -feedback oldexe -o ${baseexe}
 
 +PFB: Prefetches are improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These
       commands are used (in phase "fdo_post_makeN"):
 
            rm -f *Counts*
            mv ${baseexe} oldexe
            pixie -stats dstride oldexe 1>pixie.out 2>pixie.err
            mv oldexe.pixie ${baseexe}

       A training run is carried out (in phase "fdo_runN"), and 
       then this command (in phase "fdo_postN"):
 
            spike oldexe -fb oldexe -stride_prefetch -o ${baseexe}
 
 When Spike is used for both Icache and Prefetch improvements, 
 only one spike command is actually issued, with the Icache 
 options followed by the Prefetch options.
 
 
 vm:
         vm_bigpg_enabled = 1
         vm_bigpg_thresh=16
         vm_swap_eager = 0
 
 proc:
         max_per_proc_address_space = 0x40000000000
         max_per_proc_data_size = 0x40000000000
         max_per_proc_stack_size = 0x40000000000
         max_proc_per_user = 2048
         max_threads_per_user = 0
         maxusers = 16384
         per_proc_address_space = 0x40000000000
         per_proc_data_size = 0x40000000000
         per_proc_stack_size = 0x40000000000
 
 
 Portability: gcc: -Dalloca=__builtin_alloca; crafty: -DALPHA
 perlbmk: -DSPEC_CPU2000_DUNIX; vortex: -DSPEC_CPU2000_LP64
 gap: -DSYS_HAS_CALLOC_PROTO -DSYS_IS_BSD -DSYS_HAS_IOCTL_PROTO 
      -DSPEC_CPU2000_LP64
  
 Information on UNIX V5.1B Patches can be found at
 http://ftp1.service.digital.com/public/unix/v5.1b/
  
 Processes were bound to CPUs using 'runon'.
 In the GS1280, there are two CPUs per shelf. Each CPU 
 has its own 4GB of memory. Neither of the CPUs can be
 physically removed. For 1 CPU result measurements, 
 one CPU was turned off at boot time using the
 /etc/sysconfigtab setting "cpu_enabled_mask=0". The
 second CPU's 4GB of memory was also physically removed.


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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 28-Jan-2003

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