SPEC CPU(R)2017 Floating Point Speed Result Cisco Systems Cisco UCS X210c M6 (Intel Xeon Gold 6342, 2.80GHz) CPU2017 License: 9019 Test date: Dec-2021 Test sponsor: Cisco Systems Hardware availability: Sep-2021 Tested by: Cisco Systems Software availability: Sep-2021 Base Base Base Peak Peak Peak Benchmarks Threads Run Time Ratio Threads Run Time Ratio --------------- ------- --------- --------- ------- --------- --------- 603.bwaves_s 48 86.9 679 S 48 88.2 669 S 603.bwaves_s 48 87.1 677 * 48 87.1 678 * 603.bwaves_s 48 88.0 671 S 48 86.6 681 S 607.cactuBSSN_s 48 69.0 241 S 48 69.0 241 S 607.cactuBSSN_s 48 67.1 248 S 48 67.1 248 S 607.cactuBSSN_s 48 68.8 242 * 48 68.8 242 * 619.lbm_s 48 37.8 138 S 48 37.8 138 S 619.lbm_s 48 38.1 137 * 48 38.1 137 * 619.lbm_s 48 39.8 132 S 48 39.8 132 S 621.wrf_s 48 81.5 162 S 48 78.4 169 * 621.wrf_s 48 81.1 163 S 48 78.3 169 S 621.wrf_s 48 81.3 163 * 48 78.4 169 S 627.cam4_s 48 61.4 144 S 48 61.4 144 S 627.cam4_s 48 61.4 144 * 48 61.4 144 * 627.cam4_s 48 62.2 143 S 48 62.2 143 S 628.pop2_s 48 146 81.2 * 48 146 81.2 * 628.pop2_s 48 146 81.4 S 48 146 81.4 S 628.pop2_s 48 148 80.1 S 48 148 80.1 S 638.imagick_s 48 65.7 220 * 48 65.7 220 * 638.imagick_s 48 65.5 220 S 48 65.5 220 S 638.imagick_s 48 65.8 219 S 48 65.8 219 S 644.nab_s 48 48.5 360 * 48 46.3 377 * 644.nab_s 48 48.5 360 S 48 46.2 378 S 644.nab_s 48 48.6 360 S 48 46.3 377 S 649.fotonik3d_s 48 79.6 115 S 48 78.5 116 S 649.fotonik3d_s 48 78.5 116 S 48 79.0 115 * 649.fotonik3d_s 48 79.2 115 * 48 79.3 115 S 654.roms_s 48 67.2 234 * 48 67.2 234 * 654.roms_s 48 67.5 233 S 48 67.5 233 S 654.roms_s 48 67.1 235 S 48 67.1 235 S ================================================================================= 603.bwaves_s 48 87.1 677 * 48 87.1 678 * 607.cactuBSSN_s 48 68.8 242 * 48 68.8 242 * 619.lbm_s 48 38.1 137 * 48 38.1 137 * 621.wrf_s 48 81.3 163 * 48 78.4 169 * 627.cam4_s 48 61.4 144 * 48 61.4 144 * 628.pop2_s 48 146 81.2 * 48 146 81.2 * 638.imagick_s 48 65.7 220 * 48 65.7 220 * 644.nab_s 48 48.5 360 * 48 46.3 377 * 649.fotonik3d_s 48 79.2 115 * 48 79.0 115 * 654.roms_s 48 67.2 234 * 48 67.2 234 * SPECspeed(R)2017_fp_base 198 SPECspeed(R)2017_fp_peak 200 HARDWARE -------- CPU Name: Intel Xeon Gold 6342 Max MHz: 3500 Nominal: 2800 Enabled: 48 cores, 2 chips Orderable: 1,2 Chips Cache L1: 32 KB I + 48 KB D on chip per core L2: 1.25 MB I+D on chip per core L3: 36 MB I+D on chip per chip Other: None Memory: 2 TB (32 x 64 GB 2Rx4 PC4-3200AA-R) Storage: 1 x 240 GB M.2 SSD SATA Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 15 SP3 5.3.18-57-default Compiler: C/C++: Version 2021.4.0 of Intel oneAPI DPC++/C++ Compiler Build 20210924 for Linux; Fortran: Version 2021.4.0 of Intel Fortran Compiler Classic Build 20210910 for Linux; C/C++: Version 2021.4.0 of Intel C/C++ Compiler Classic Build 20210910 for Linux; Parallel: Yes Firmware: Version 5.0.1d released Aug-2021 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: 64-bit Other: jemalloc memory allocator V5.0.1 Power Management: BIOS and OS set to prefer performance at the cost of additional power usage Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Environment Variables Notes --------------------------- Environment variables set by runcpu before the start of the run: KMP_AFFINITY = "granularity=fine,compact" LD_LIBRARY_PATH = "/home/intel/tbb/2021.4.0/env/../lib/intel64/gcc4.8:/home/intel/mpi/2021 .4.0//libfabric/lib:/home/intel/mpi/2021.4.0//lib/release:/home/intel/mp i/2021.4.0//lib:/home/intel/compiler/2021.4.0/linux/compiler/lib/intel64 _lin:/home/intel/compiler/2021.4.0/linux/lib:/home/intel/clck/2021.4.0/l ib/intel64:/home/cpu2017/je5.0.1-64" MALLOC_CONF = "retain:true" OMP_STACKSIZE = "192M" General Notes ------------- Binaries compiled on a system with 1x Intel Core i9-7980XE CPU + 64GB RAM memory using Redhat Enterprise Linux 8.0 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. jemalloc, a general purpose malloc implementation built with the RedHat Enterprise 7.5, and the system compiler gcc 4.8.5 sources available from jemalloc.net or https://github.com/jemalloc/jemalloc/releases Platform Notes -------------- BIOS Settings: Adjacent Cache Line Prefetcher set to Disabled DCU Streamer Prefetch set to Disabled Sub NUMA Clustering set to Enabled LLC Dead Line set to Disabled Memory Refresh Rate set to 1x Refresh ADDDC Sparing set to Disabled Patrol Scrub set to Disabled Intel Hyper-Threading Technology set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r6622 of 2021-04-07 982a61ec0915b55891ef0e16acafc64d running on perf-blade1 Fri Dec 3 01:12:58 2021 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 6342 CPU @ 2.80GHz 2 "physical id"s (chips) 48 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 24 siblings : 24 physical 0: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 physical 1: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 From lscpu from util-linux 2.36.2: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian Address sizes: 46 bits physical, 57 bits virtual CPU(s): 48 On-line CPU(s) list: 0-47 Thread(s) per core: 1 Core(s) per socket: 24 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 106 Model name: Intel(R) Xeon(R) Gold 6342 CPU @ 2.80GHz Stepping: 6 CPU MHz: 1253.533 CPU max MHz: 3500.0000 CPU min MHz: 800.0000 BogoMIPS: 5600.00 Virtualization: VT-x L1d cache: 2.3 MiB L1i cache: 1.5 MiB L2 cache: 60 MiB L3 cache: 72 MiB NUMA node0 CPU(s): 0-23 NUMA node1 CPU(s): 24-47 Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced IBRS, IBPB conditional, RSB filling Vulnerability Srbds: Not affected Vulnerability Tsx async abort: Not affected Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 invpcid_single ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid fsrm md_clear pconfig flush_l1d arch_capabilities From lscpu --cache: NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE L1d 48K 2.3M 12 Data 1 64 1 64 L1i 32K 1.5M 8 Instruction 1 64 1 64 L2 1.3M 60M 20 Unified 2 1024 1 64 L3 36M 72M 12 Unified 3 49152 1 64 /proc/cpuinfo cache data cache size : 36864 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 node 0 size: 1031745 MB node 0 free: 1024688 MB node 1 cpus: 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 node 1 size: 1032182 MB node 1 free: 1031061 MB node distances: node 0 1 0: 10 20 1: 20 10 From /proc/meminfo MemTotal: 2113462016 kB HugePages_Total: 0 Hugepagesize: 2048 kB /sys/devices/system/cpu/cpu*/cpufreq/scaling_governor has performance From /etc/*release* /etc/*version* os-release: NAME="SLES" VERSION="15-SP3" VERSION_ID="15.3" PRETTY_NAME="SUSE Linux Enterprise Server 15 SP3" ID="sles" ID_LIKE="suse" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:15:sp3" uname -a: Linux perf-blade1 5.3.18-57-default #1 SMP Wed Apr 28 10:54:41 UTC 2021 (ba3c2e9) x86_64 x86_64 x86_64 GNU/Linux Kernel self-reported vulnerability status: CVE-2018-12207 (iTLB Multihit): Not affected CVE-2018-3620 (L1 Terminal Fault): Not affected Microarchitectural Data Sampling: Not affected CVE-2017-5754 (Meltdown): Not affected CVE-2018-3639 (Speculative Store Bypass): Mitigation: Speculative Store Bypass disabled via prctl and seccomp CVE-2017-5753 (Spectre variant 1): Mitigation: usercopy/swapgs barriers and __user pointer sanitization CVE-2017-5715 (Spectre variant 2): Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling CVE-2020-0543 (Special Register Buffer Data Sampling): Not affected CVE-2019-11135 (TSX Asynchronous Abort): Not affected run-level 3 Dec 2 21:05 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda3 xfs 181G 60G 122G 34% /home From /sys/devices/virtual/dmi/id Vendor: Cisco Systems Inc Product: UCSX-210C-M6 Serial: FCH25057AMV Additional information from dmidecode 3.2 follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. Memory: 32x 0xCE00 M393A8G40AB2-CWE 64 GB 2 rank 3200 BIOS: BIOS Vendor: Cisco Systems, Inc. BIOS Version: X210M6.5.0.1d.0.0816211754 BIOS Date: 08/16/2021 BIOS Revision: 5.22 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== C | 619.lbm_s(base, peak) 638.imagick_s(base, peak) | 644.nab_s(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C | 644.nab_s(peak) ------------------------------------------------------------------------------ Intel(R) oneAPI DPC++/C++ Compiler for applications running on Intel(R) 64, Version 2021.4.0 Build 20210924 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C | 619.lbm_s(base, peak) 638.imagick_s(base, peak) | 644.nab_s(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C | 644.nab_s(peak) ------------------------------------------------------------------------------ Intel(R) oneAPI DPC++/C++ Compiler for applications running on Intel(R) 64, Version 2021.4.0 Build 20210924 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++, C, Fortran | 607.cactuBSSN_s(base, peak) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran | 603.bwaves_s(base, peak) 649.fotonik3d_s(base, peak) | 654.roms_s(base, peak) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran, C | 621.wrf_s(base, peak) 627.cam4_s(base, peak) | 628.pop2_s(base, peak) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.4.0 Build 20210910_000000 Copyright (C) 1985-2021 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc Fortran benchmarks: ifort Benchmarks using both Fortran and C: ifort icc Benchmarks using Fortran, C, and C++: icpc icc ifort Base Portability Flags ---------------------- 603.bwaves_s: -DSPEC_LP64 607.cactuBSSN_s: -DSPEC_LP64 619.lbm_s: -DSPEC_LP64 621.wrf_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian 627.cam4_s: -DSPEC_LP64 -DSPEC_CASE_FLAG 628.pop2_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian -assume byterecl 638.imagick_s: -DSPEC_LP64 644.nab_s: -DSPEC_LP64 649.fotonik3d_s: -DSPEC_LP64 654.roms_s: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -m64 -std=c11 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries Fortran benchmarks: -m64 -Wl,-z,muldefs -DSPEC_OPENMP -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -nostandard-realloc-lhs -mbranches-within-32B-boundaries -L/home/cpu2017/je5.0.1-64 -ljemalloc Benchmarks using both Fortran and C: -m64 -std=c11 -Wl,-z,muldefs -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries -nostandard-realloc-lhs -L/home/cpu2017/je5.0.1-64 -ljemalloc Benchmarks using Fortran, C, and C++: -m64 -std=c11 -Wl,-z,muldefs -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries -nostandard-realloc-lhs -L/home/cpu2017/je5.0.1-64 -ljemalloc Peak Compiler Invocation ------------------------ C benchmarks (except as noted below): icc 644.nab_s: icx Fortran benchmarks: ifort Benchmarks using both Fortran and C: ifort icc Benchmarks using Fortran, C, and C++: icpc icc ifort Peak Portability Flags ---------------------- Same as Base Portability Flags Peak Optimization Flags ----------------------- C benchmarks: 619.lbm_s: basepeak = yes 638.imagick_s: basepeak = yes 644.nab_s: -m64 -Wl,-z,muldefs -xCORE-AVX2 -Ofast -ffast-math -flto -mfpmath=sse -funroll-loops -fiopenmp -DSPEC_OPENMP -qopt-mem-layout-trans=4 -fimf-accuracy-bits=14:sqrt -mbranches-within-32B-boundaries -L/home/cpu2017/je5.0.1-64 -ljemalloc Fortran benchmarks: 603.bwaves_s: -m64 -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -DSPEC_SUPPRESS_OPENMP -DSPEC_OPENMP -ipo -xCORE-AVX2 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -nostandard-realloc-lhs -mbranches-within-32B-boundaries -L/home/cpu2017/je5.0.1-64 -ljemalloc 649.fotonik3d_s: Same as 603.bwaves_s 654.roms_s: basepeak = yes Benchmarks using both Fortran and C: 621.wrf_s: -m64 -std=c11 -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX2 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -DSPEC_SUPPRESS_OPENMP -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries -nostandard-realloc-lhs -L/home/cpu2017/je5.0.1-64 -ljemalloc 627.cam4_s: basepeak = yes 628.pop2_s: basepeak = yes Benchmarks using Fortran, C, and C++: 607.cactuBSSN_s: basepeak = yes The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic2021-official-linux64_revA.2021-12-22.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.0-ICX-revJ.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic2021-official-linux64_revA.2021-12-22.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.0-ICX-revJ.xml SPEC CPU and SPECspeed are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2021 Standard Performance Evaluation Corporation Tested with SPEC CPU(R)2017 v1.1.8 on 2021-12-03 04:12:58-0500. Report generated on 2021-12-22 12:30:54 by CPU2017 text formatter v6255. Originally published on 2021-12-21.