Changeset 763

Timestamp:

Apr 6, 2025, 3:30:42 AM (4 months ago)

Author:

Paul Smedley

Message:

Make it compile

Location:

GPL/branches/uniaud32-exp

Files:

• alsa-kernel/core/init.c (modified) (1 diff)
• alsa-kernel/core/memory.c (modified) (2 diffs)
• alsa-kernel/core/pcm_lib.c (modified) (8 diffs)
• alsa-kernel/core/rawmidi.c (modified) (4 diffs)
• alsa-kernel/core/seq/seq_clientmgr.c (modified) (3 diffs)
• alsa-kernel/hda/hdac_stream.c (modified) (2 diffs)
• alsa-kernel/include/sound/asequencer.h (modified) (1 diff)
• alsa-kernel/include/sound/control.h (modified) (1 diff)
• alsa-kernel/include/sound/emu10k1.h (modified) (13 diffs)
• alsa-kernel/include/sound/hdaudio.h (modified) (2 diffs)
• alsa-kernel/include/uapi/sound/asound.h (modified) (1 diff)
• alsa-kernel/pci/emu10k1/emu10k1_main.c (modified) (3 diffs)
• alsa-kernel/pci/emu10k1/emufx.c (modified) (1 diff)
• alsa-kernel/pci/emu10k1/emumixer.c (modified) (18 diffs)
• alsa-kernel/pci/emu10k1/emuproc.c (modified) (1 diff)
• alsa-kernel/pci/es1938.c (modified) (2 diffs)
• alsa-kernel/pci/hda/hda_component2.h (modified) (1 diff)
• alsa-kernel/pci/hda/hda_intel.c (modified) (2 diffs)
• alsa-kernel/pci/hda/patch_ca0132.c (modified) (1 diff)
• alsa-kernel/pci/hda/patch_realtek.c (modified) (3 diffs)
• alsa-kernel/pci/nm256/nm256.c (modified) (2 diffs)
• alsa-kernel/pci/ymfpci/ymfpci.h (modified) (1 diff)
• include/asm/uaccess.h (modified) (3 diffs)
• include/linux/fs.h (modified) (1 diff)
• include/linux/ioport.h (modified) (1 diff)
• include/linux/kernel.h (modified) (1 diff)
• include/linux/lockdep.h (modified) (1 diff)
• include/linux/minmax.h (added)
• include/linux/pci_ids.h (modified) (55 diffs)
• include/linux/pm.h (modified) (2 diffs)
• include/linux/regmap.h (modified) (2 diffs)
• include/linux/uaccess.h (modified) (1 diff)
• include/linux/uio.h (modified) (3 diffs)
• lib32/regcache.c (modified) (1 diff)

GPL/branches/uniaud32-exp/alsa-kernel/core/init.c

@@ -23 +23 @@
 
 #ifdef TARGET_OS2
-struct class *sound_class;
+const struct class sound_class;
 #endif
 

GPL/branches/uniaud32-exp/alsa-kernel/core/memory.c

@@ -12 +12 @@
 #include <sound/pcm.h>
 
+#ifndef TARGET_OS2
 /**
  * copy_to_user_fromio - copy data from mmio-space to user-space
@@ -114 +115 @@
 }
 EXPORT_SYMBOL(copy_from_iter_toio);
+#else // TARGET_OS2
+/**
+ * copy_to_user_fromio - copy data from mmio-space to user-space
+ * @dst: the destination pointer on user-space
+ * @src: the source pointer on mmio
+ * @count: the data size to copy in bytes
+ *
+ * Copies the data from mmio-space to user-space.
+ *
+ * Return: Zero if successful, or non-zero on failure.
+ */
+int copy_to_user_fromio(void __user *dst, const volatile void __iomem *src, size_t count)
+{
+#if defined(__i386__) || defined(CONFIG_SPARC32)
+        return copy_to_user(dst, (const void __force*)src, count) ? -EFAULT : 0;
+#else
+        char buf[256];
+        while (count) {
+                size_t c = count;
+                if (c > sizeof(buf))
+                        c = sizeof(buf);
+                memcpy_fromio(buf, (void __iomem *)src, c);
+                if (copy_to_user(dst, buf, c))
+                        return -EFAULT;
+                count -= c;
+                dst += c;
+                src += c;
+        }
+        return 0;
+#endif
+}
+EXPORT_SYMBOL(copy_to_user_fromio);
+
+/**
+ * copy_from_user_toio - copy data from user-space to mmio-space
+ * @dst: the destination pointer on mmio-space
+ * @src: the source pointer on user-space
+ * @count: the data size to copy in bytes
+ *
+ * Copies the data from user-space to mmio-space.
+ *
+ * Return: Zero if successful, or non-zero on failure.
+ */
+int copy_from_user_toio(volatile void __iomem *dst, const void __user *src, size_t count)
+{
+#if defined(__i386__) || defined(CONFIG_SPARC32)
+        return copy_from_user((void __force *)dst, src, count) ? -EFAULT : 0;
+#else
+        char buf[256];
+        while (count) {
+                size_t c = count;
+                if (c > sizeof(buf))
+                        c = sizeof(buf);
+                if (copy_from_user(buf, src, c))
+                        return -EFAULT;
+                memcpy_toio(dst, buf, c);
+                count -= c;
+                dst += c;
+                src += c;
+        }
+        return 0;
+#endif
+}
+EXPORT_SYMBOL(copy_from_user_toio);
+#endif // TARGET_OS2

GPL/branches/uniaud32-exp/alsa-kernel/core/pcm_lib.c

@@ -2025 +2025 @@
 
 /* default copy ops for write; used for both interleaved and non- modes */
+#ifndef TARGET_OS2
 static int default_write_copy(struct snd_pcm_substream *substream,
                               int channel, unsigned long hwoff,
@@ -2034 +2035 @@
         return 0;
 }
+#else
+static int default_write_copy(struct snd_pcm_substream *substream,
+                              int channel, unsigned long hwoff,
+                              void *buf, unsigned long bytes)
+{
+        if (copy_from_user(get_dma_ptr(substream->runtime, channel, hwoff),
+                           (void __user *)buf, bytes))
+                return -EFAULT;
+        return 0;
+}
+#endif
 
 /* fill silence instead of copy data; called as a transfer helper
@@ -2058 +2070 @@
 
 /* default copy ops for read; used for both interleaved and non- modes */
+#ifndef TARGET_OS2
 static int default_read_copy(struct snd_pcm_substream *substream,
                              int channel, unsigned long hwoff,
@@ -2081 +2094 @@
                 type = ITER_DEST;
 
+#if 0 //FIXME
         if (in_kernel) {
                 struct kvec kvec = { data, bytes };
@@ -2087 +2101 @@
                 return transfer(substream, c, hwoff, &iter, bytes);
         }
-
+#endif
         err = import_ubuf(type, (__force void __user *)data, bytes, &iter);
         if (err)
@@ -2093 +2107 @@
         return transfer(substream, c, hwoff, &iter, bytes);
 }
+#else
+static int default_read_copy(struct snd_pcm_substream *substream,
+                             int channel, unsigned long hwoff,
+                             void *buf, unsigned long bytes)
+{
+        if (copy_to_user((void __user *)buf,
+                         get_dma_ptr(substream->runtime, channel, hwoff),
+                         bytes))
+                return -EFAULT;
+        return 0;
+}
+#endif
 
 /* call transfer function with the converted pointers and sizes;
@@ -2111 +2137 @@
         frames = frames_to_bytes(runtime, frames);
 
+#ifndef TARGET_OS2
         return do_transfer(substream, 0, hwoff, data + off, frames, transfer,
                            in_kernel);
+#else
+        return transfer(substream, 0, hwoff, data + off, frames);
+#endif
 }
 
@@ -2141 +2171 @@
                         err = fill_silence(substream, c, hwoff, NULL, frames);
                 else
+#ifndef TARGET_OS2
                         err = do_transfer(substream, c, hwoff, *bufs + off,
                                           frames, transfer, in_kernel);
+#else
+                        err = transfer(substream, c, hwoff, *bufs + off,
+                                       frames);
+#endif
                 if (err < 0)
                         return err;

GPL/branches/uniaud32-exp/alsa-kernel/core/rawmidi.c

@@ -87 +87 @@
 #define SNDRV_RAWMIDI_IOCTL_STATUS64    _IOWR('W', 0x20, struct snd_rawmidi_status64)
 
+#ifndef TARGET_OS2
 #define rawmidi_is_ump(rmidi) \
         (IS_ENABLED(CONFIG_SND_UMP) && ((rmidi)->info_flags & SNDRV_RAWMIDI_INFO_UMP))
+#else
+#define rawmidi_is_ump(rmidi) \
+        (0 && ((rmidi)->info_flags & SNDRV_RAWMIDI_INFO_UMP))
+#endif
 
 static struct snd_rawmidi *snd_rawmidi_search(struct snd_card *card, int device)
@@ -206 +211 @@
 static inline int get_align(struct snd_rawmidi_runtime *runtime)
 {
+#ifndef TARGET_OS2
         if (IS_ENABLED(CONFIG_SND_UMP))
                 return runtime->align;
         else
+#endif
                 return 0;
 }
@@ -1065 +1072 @@
 }
 
-#if IS_ENABLED(CONFIG_SND_UMP)
+#if IS_ENABLED(CONFIG_SND_UMP) || defined(CONFIG_SND_UMP)
 /* inquiry of UMP endpoint and block info via control API */
 static int snd_rawmidi_call_ump_ioctl(struct snd_card *card, int cmd,
@@ -1796 +1803 @@
         rmidi = entry->private_data;
         snd_iprintf(buffer, "%s\n\n", rmidi->name);
+#ifndef TARGET_OS2
         if (IS_ENABLED(CONFIG_SND_UMP))
                 snd_iprintf(buffer, "Type: %s\n",
                             rawmidi_is_ump(rmidi) ? "UMP" : "Legacy");
+#endif
         if (rmidi->ops && rmidi->ops->proc_read)
                 rmidi->ops->proc_read(entry, buffer);

GPL/branches/uniaud32-exp/alsa-kernel/core/seq/seq_clientmgr.c

@@ -180 +180 @@
 static struct snd_seq_client *client_load_and_use_ptr(int clientid)
 {
+#ifndef TARGET_OS2
         return client_use_ptr(clientid, IS_ENABLED(CONFIG_MODULES));
+#else
+        return client_use_ptr(clientid, 0);
+#endif
 }
 
@@ -466 +470 @@
         snd_seq_fifo_lock(fifo);
 
+#ifndef TARGET_OS2
         if (IS_ENABLED(CONFIG_SND_SEQ_UMP) && client->midi_version > 0)
                 aligned_size = sizeof(struct snd_seq_ump_event);
         else
+#endif
                 aligned_size = sizeof(struct snd_seq_event);
 
@@ -1306 +1312 @@
                         return -EINVAL;
 
+#ifndef TARGET_OS2
                 /* check if UMP is supported in kernel */
                 if (!IS_ENABLED(CONFIG_SND_SEQ_UMP) &&
                     client_info->midi_version > 0)
+#endif
                         return -EINVAL;
         }

GPL/branches/uniaud32-exp/alsa-kernel/hda/hdac_stream.c

@@ -881 +881 @@
 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
 
+#ifndef TARGET_OS2
 /*
  * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
@@ -902 +903 @@
 }
 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
+#endif
 
 /**

GPL/branches/uniaud32-exp/alsa-kernel/include/sound/asequencer.h

@@ -67 +67 @@
 
 /* check whether the given event is a UMP event */
+#ifndef TARGET_OS2
 #define snd_seq_ev_is_ump(ev) \
         (IS_ENABLED(CONFIG_SND_SEQ_UMP) && ((ev)->flags & SNDRV_SEQ_EVENT_UMP))
-
+#else
+#define snd_seq_ev_is_ump(ev) \
+        (0 && ((ev)->flags & SNDRV_SEQ_EVENT_UMP))
+#endif
 /* queue sync port */
 #define snd_seq_queue_sync_port(q)      ((q) + 16)

GPL/branches/uniaud32-exp/alsa-kernel/include/sound/control.h

@@ -161 +161 @@
 snd_ctl_find_id_mixer(struct snd_card *card, const char *name)
 {
-        struct snd_ctl_elem_id id = {};
+        struct snd_ctl_elem_id id = {0};
 
         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;

GPL/branches/uniaud32-exp/alsa-kernel/include/sound/emu10k1.h

@@ -182 +182 @@
 
 #define WC                      0x10            /* Wall Clock register                          */
+#ifndef TARGET_OS2
 SUB_REG(WC, SAMPLECOUNTER,      0x03FFFFC0)     /* Sample periods elapsed since reset           */
 SUB_REG(WC, CURRENTCHANNEL,     0x0000003F)     /* Channel [0..63] currently being serviced     */
@@ -187 +188 @@
                                                 /* period to be serviced.                       */
 
+#else
+#define WC_SAMPLECOUNTER_MASK   0x03FFFFC0      /* Sample periods elapsed since reset           */
+#define WC_SAMPLECOUNTER        0x14060010
+#define WC_CURRENTCHANNEL       0x0000003F      /* Channel [0..63] currently being serviced     */
+                                                /* NOTE: Each channel takes 1/64th of a sample  */
+                                                /* period to be serviced.                       */
+#endif
 #define HCFG                    0x14            /* Hardware config register                     */
                                                 /* NOTE: There is no reason to use the legacy   */
@@ -257 +265 @@
 #define HCFG_LOCKSOUNDCACHE     0x00000008      /* 1 = Cancel bustmaster accesses to soundcache */
                                                 /* NOTE: This should generally never be used.   */
+#ifndef TARGET_OS2
 SUB_REG(HCFG, LOCKTANKCACHE,    0x00000004)     /* 1 = Cancel bustmaster accesses to tankcache  */
                                                 /* NOTE: This should generally never be used.   */
+#else
+#define HCFG_LOCKTANKCACHE_MASK 0x00000004      /* 1 = Cancel bustmaster accesses to tankcache  */
+                                                /* NOTE: This should generally never be used.   */
+#define HCFG_LOCKTANKCACHE      0x01020014
+#endif
 #define HCFG_MUTEBUTTONENABLE   0x00000002      /* 1 = Master mute button sets AUDIOENABLE = 0. */
                                                 /* NOTE: This is a 'cheap' way to implement a   */
@@ -421 +435 @@
 
 #define CPF                     0x00            /* Current pitch and fraction register                  */
+#ifndef TARGET_OS2
 SUB_REG(CPF, CURRENTPITCH,      0xffff0000)     /* Current pitch (linear, 0x4000 == unity pitch shift)  */
+#else
+#define CPF_CURRENTPITCH_MASK   0xffff0000      /* Current pitch (linear, 0x4000 == unity pitch shift)  */
+#define CPF_CURRENTPITCH        0x10100000
+#endif
 #define CPF_STEREO_MASK         0x00008000      /* 1 = Even channel interleave, odd channel locked      */
+#ifndef TARGET_OS2
 SUB_REG(CPF, STOP,              0x00004000)     /* 1 = Current pitch forced to 0                        */
                                                 /* Can be set only while matching bit in SOLEx is 1     */
+#else
+#define CPF_STOP                0x00004000      /* 1 = Current pitch forced to 0                        */
+#define CPF_STOP_MASK           0x00004000      /* 1 = Current pitch forced to 0                        */
+#endif
 #define CPF_FRACADDRESS_MASK    0x00003fff      /* Linear fractional address of the current channel     */
 
 #define PTRX                    0x01            /* Pitch target and send A/B amounts register           */
+#ifndef TARGET_OS2
 SUB_REG(PTRX, PITCHTARGET,      0xffff0000)     /* Pitch target of specified channel                    */
 SUB_REG(PTRX, FXSENDAMOUNT_A,   0x0000ff00)     /* Linear level of channel output sent to FX send bus A */
 SUB_REG(PTRX, FXSENDAMOUNT_B,   0x000000ff)     /* Linear level of channel output sent to FX send bus B */
+#else
+#define PTRX_PITCHTARGET_MASK   0xffff0000      /* Pitch target of specified channel                    */
+#define PTRX_PITCHTARGET        0x10100001
+#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00     /* Linear level of channel output sent to FX send bus A */
+#define PTRX_FXSENDAMOUNT_A     0x08080001
+#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff     /* Linear level of channel output sent to FX send bus B */
+#define PTRX_FXSENDAMOUNT_B     0x08000001
+#endif
 
 // Note: the volumes are raw multpliers, so real 100% is impossible.
 #define CVCF                    0x02            /* Current volume and filter cutoff register            */
+#ifndef TARGET_OS2
 SUB_REG(CVCF, CURRENTVOL,       0xffff0000)     /* Current linear volume of specified channel           */
 SUB_REG(CVCF, CURRENTFILTER,    0x0000ffff)     /* Current filter cutoff frequency of specified channel */
+#else
+#define CVCF_CURRENTVOL_MASK    0xffff0000      /* Current linear volume of specified channel           */
+#define CVCF_CURRENTVOL         0x10100002
+#define CVCF_CURRENTFILTER_MASK 0x0000ffff      /* Current filter cutoff frequency of specified channel */
+#define CVCF_CURRENTFILTER      0x10000002
+#endif
 
 #define VTFT                    0x03            /* Volume target and filter cutoff target register      */
+#ifndef TARGET_OS2
 SUB_REG(VTFT, VOLUMETARGET,     0xffff0000)     /* Volume target of specified channel                   */
 SUB_REG(VTFT, FILTERTARGET,     0x0000ffff)     /* Filter cutoff target of specified channel            */
+#else
+#define VTFT_VOLUMETARGET_MASK  0xffff0000      /* Volume target of specified channel                   */
+#define VTFT_VOLUMETARGET       0x10100003
+#define VTFT_FILTERTARGET_MASK  0x0000ffff      /* Filter cutoff target of specified channel            */
+#define VTFT_FILTERTARGET       0x10000003
+#endif
 
 #define Z1                      0x05            /* Filter delay memory 1 register                       */
@@ -446 +493 @@
 
 #define PSST                    0x06            /* Send C amount and loop start address register        */
+#ifndef TARGET_OS2
 SUB_REG(PSST, FXSENDAMOUNT_C,   0xff000000)     /* Linear level of channel output sent to FX send bus C */
 SUB_REG(PSST, LOOPSTARTADDR,    0x00ffffff)     /* Loop start address of the specified channel          */
+#else
+#define PSST_FXSENDAMOUNT_C_MASK 0xff000000     /* Linear level of channel output sent to FX send bus C */
+
+#define PSST_FXSENDAMOUNT_C     0x08180006
+
+#define PSST_LOOPSTARTADDR_MASK 0x00ffffff      /* Loop start address of the specified channel          */
+#define PSST_LOOPSTARTADDR      0x18000006
+#endif
 
 #define DSL                     0x07            /* Send D amount and loop end address register  */
+#ifndef TARGET_OS2
 SUB_REG(DSL, FXSENDAMOUNT_D,    0xff000000)     /* Linear level of channel output sent to FX send bus D */
 SUB_REG(DSL, LOOPENDADDR,       0x00ffffff)     /* Loop end address of the specified channel            */
+#else
+#define DSL_FXSENDAMOUNT_D_MASK 0xff000000      /* Linear level of channel output sent to FX send bus D */
+
+#define DSL_FXSENDAMOUNT_D      0x08180007
+
+#define DSL_LOOPENDADDR_MASK    0x00ffffff      /* Loop end address of the specified channel            */
+#define DSL_LOOPENDADDR         0x18000007
+#endif
 
 #define CCCA                    0x08            /* Filter Q, interp. ROM, byte size, cur. addr register */
+#ifndef TARGET_OS2
 SUB_REG(CCCA, RESONANCE,        0xf0000000)     /* Lowpass filter resonance (Q) height                  */
+#else
+#define CCCA_RESONANCE          0xf0000000      /* Lowpass filter resonance (Q) height                  */
+#endif
 #define CCCA_INTERPROM_MASK     0x0e000000      /* Selects passband of interpolation ROM                */
                                                 /* 1 == full band, 7 == lowpass                         */
@@ -471 +540 @@
 #define CCCA_8BITSELECT         0x01000000      /* 1 = Sound memory for this channel uses 8-bit samples */
                                                 /* 8-bit samples are unsigned, 16-bit ones signed       */
+#ifndef TARGET_OS2
 SUB_REG(CCCA, CURRADDR,         0x00ffffff)     /* Current address of the selected channel              */
+#else
+#define CCCA_CURRADDR_MASK      0x00ffffff      /* Current address of the selected channel              */
+#define CCCA_CURRADDR           0x18000008
+#endif
 
 #define CCR                     0x09            /* Cache control register                               */
+#ifndef TARGET_OS2
 SUB_REG(CCR, CACHEINVALIDSIZE,  0xfe000000)     /* Number of invalid samples before the read address    */
+#else
+#define CCR_CACHEINVALIDSIZE    0x07190009
+#define CCR_CACHEINVALIDSIZE_MASK       0xfe000000      /* Number of invalid samples cache for this channel     */
+#endif
 #define CCR_CACHELOOPFLAG       0x01000000      /* 1 = Cache has a loop service pending                 */
 #define CCR_INTERLEAVEDSAMPLES  0x00800000      /* 1 = A cache service will fetch interleaved samples   */
@@ -480 +559 @@
 #define CCR_WORDSIZEDSAMPLES    0x00400000      /* 1 = A cache service will fetch word sized samples    */
                                                 /* Auto-set from CCCA_8BITSELECT                        */
+#ifndef TARGET_OS2
 SUB_REG(CCR, READADDRESS,       0x003f0000)     /* Next cached sample to play                           */
 SUB_REG(CCR, LOOPINVALSIZE,     0x0000fe00)     /* Number of invalid samples in cache prior to loop     */
+#else
+#define CCR_READADDRESS         0x06100009
+#define CCR_READADDRESS_MASK    0x003f0000      /* Location of cache just beyond current cache service  */
+#define CCR_LOOPINVALSIZE       0x0000fe00      /* Number of invalid samples in cache prior to loop     */
+                                                /* NOTE: This is valid only if CACHELOOPFLAG is set     */
+#endif
                                                 /* NOTE: This is valid only if CACHELOOPFLAG is set     */
 #define CCR_LOOPFLAG            0x00000100      /* Set for a single sample period when a loop occurs    */
+#ifndef TARGET_OS2
 SUB_REG(CCR, CACHELOOPADDRHI,   0x000000ff)     /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set  */
+#else
+#define CCR_CACHELOOPADDRHI     0x000000ff      /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set  */
+#endif
 
 #define CLP                     0x0a            /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
                                                 /* NOTE: This register is normally not used             */
+#ifndef TARGET_OS2
 SUB_REG(CLP, CACHELOOPADDR,     0x0000ffff)     /* Cache loop address low word                          */
+#else
+#define CLP_CACHELOOPADDR       0x0000ffff      /* Cache loop address (DSL_LOOPSTARTADDR [0..15])       */
+#endif
 
 #define FXRT                    0x0b            /* Effects send routing register                        */
@@ -558 +652 @@
 
 #define IFATN                   0x19            /* Initial filter cutoff and attenuation register       */
+#ifndef TARGET_OS2
 SUB_REG(IFATN, FILTERCUTOFF,    0x0000ff00)     /* Initial filter cutoff frequency in exponential units */
                                                 /* 6 most significant bits are semitones                */
@@ -563 +658 @@
 SUB_REG(IFATN, ATTENUATION,     0x000000ff)     /* Initial attenuation in 0.375dB steps                 */
 
+#else
+#define IFATN_FILTERCUTOFF_MASK 0x0000ff00      /* Initial filter cutoff frequency in exponential units */
+                                                /* 6 most significant bits are semitones                */
+                                                /* 2 least significant bits are fractions               */
+#define IFATN_FILTERCUTOFF      0x08080019
+#define IFATN_ATTENUATION_MASK  0x000000ff      /* Initial attenuation in 0.375dB steps                 */
+#define IFATN_ATTENUATION       0x08000019
+#endif
 #define PEFE                    0x1a            /* Pitch envelope and filter envelope amount register   */
+#ifndef TARGET_OS2
 SUB_REG(PEFE, PITCHAMOUNT,      0x0000ff00)     /* Pitch envlope amount                                 */
                                                 /* Signed 2's complement, +/- one octave peak extremes  */
 SUB_REG(PEFE, FILTERAMOUNT,     0x000000ff)     /* Filter envlope amount                                */
                                                 /* Signed 2's complement, +/- six octaves peak extremes */
+#else
+#define PEFE_PITCHAMOUNT_MASK   0x0000ff00      /* Pitch envlope amount                                 */
+                                                /* Signed 2's complement, +/- one octave peak extremes  */
+#define PEFE_PITCHAMOUNT        0x0808001a
+#define PEFE_FILTERAMOUNT_MASK  0x000000ff      /* Filter envlope amount                                */
+                                                /* Signed 2's complement, +/- six octaves peak extremes */
+#define PEFE_FILTERAMOUNT       0x0800001a
+#endif
 
 
@@ -814 +926 @@
 
 #define MICIDX                  0x63            /* Microphone recording buffer index register   */
+#ifndef TARGET_OS2
 SUB_REG(MICIDX, IDX,            0x0000ffff)
+#else
+#define MICIDX_MASK             0x0000ffff      /* 16-bit value                                 */
+#define MICIDX_IDX              0x10000063
+#endif
 
 #define ADCIDX                  0x64            /* ADC recording buffer index register          */
+#ifndef TARGET_OS2
 SUB_REG(ADCIDX, IDX,            0x0000ffff)
+#else
+#define ADCIDX_MASK             0x0000ffff      /* 16 bit index field                           */
+#define ADCIDX_IDX              0x10000064
+#endif
 
 #define A_ADCIDX                0x63
+#ifndef TARGET_OS2
 SUB_REG(A_ADCIDX, IDX,          0x0000ffff)
+#else
+#define A_ADCIDX_IDX            0x10000063
+#endif
 
 #define A_MICIDX                0x64
+#ifndef TARGET_OS2
 SUB_REG(A_MICIDX, IDX,          0x0000ffff)
+#else
+#define A_MICIDX_IDX            0x10000064
+#endif
 
 #define FXIDX                   0x65            /* FX recording buffer index register           */
+#ifndef TARGET_OS2
 SUB_REG(FXIDX, IDX,             0x0000ffff)
+#else
+#define FXIDX_MASK              0x0000ffff      /* 16-bit value                                 */
+#define FXIDX_IDX               0x10000065
+#endif
 
 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status                     */
@@ -870 +1005 @@
 #define A_SPDIF_MUTED           0x000000c0
 
+#ifndef TARGET_OS2
 SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00)  /* This sets the capture PCM rate, but it is  */
                                                    /* unclear if this sets the ADC rate as well. */
+#else
+#define A_I2S_CAPTURE_RATE      0x00000e00
+#define A_I2S_CAPTURE_RATE_MASK 0x00000e00      /* This sets the capture PCM rate, but it is    */
+                                                   /* unclear if this sets the ADC rate as well. */
+#endif
 #define A_I2S_CAPTURE_48000     0x0
 #define A_I2S_CAPTURE_192000    0x1
@@ -1647 +1788 @@
         unsigned char revision;
         unsigned char emu_model;        /* EMU model type */
+#ifndef TARGET_OS2
         unsigned int emu10k1_chip:1;    /* Original SB Live. Not SB Live 24bit. */
                                         /* Redundant with emu10k2_chip being unset. */
@@ -1666 +1808 @@
         unsigned int adc_1361t:1;       /* Use Philips 1361T ADC */
         unsigned int invert_shared_spdif:1;  /* analog/digital switch inverted */
+#else
+        unsigned int emu10k1_chip;      /* Original SB Live. Not SB Live 24bit. */
+                                        /* Redundant with emu10k2_chip being unset. */
+        unsigned int emu10k2_chip;      /* Audigy 1 or Audigy 2. */
+        unsigned int ca0102_chip;       /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
+                                        /* Redundant with ca0108_chip being unset. */
+        unsigned int ca0108_chip;       /* Audigy 2 Value */
+        unsigned int ca_cardbus_chip;   /* Audigy 2 ZS Notebook */
+        unsigned int ca0151_chip;       /* P16V */
+        unsigned int spk20;             /* Stereo only */
+        unsigned int spk71;             /* Has 7.1 speakers */
+        unsigned int no_adat;           /* Has no ADAT, only SPDIF */
+        unsigned int sblive51;          /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
+        unsigned int spdif_bug;         /* Has Spdif phasing bug */
+        unsigned int ac97_chip;         /* Has an AC97 chip: 1 = mandatory, 2 = optional */
+        unsigned int ecard;             /* APS EEPROM */
+        unsigned int spi_dac;           /* SPI interface for DAC; requires ca0108_chip */
+        unsigned int i2c_adc;           /* I2C interface for ADC; requires ca0108_chip */
+        unsigned int adc_1361t;         /* Use Philips 1361T ADC */
+        unsigned int invert_shared_spdif;  /* analog/digital switch inverted */
+#endif
         const char *driver;
         const char *name;

GPL/branches/uniaud32-exp/alsa-kernel/include/sound/hdaudio.h

@@ -724 +724 @@
  */
 
+#ifndef TARGET_OS2
 #define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \
                         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \
@@ -744 +745 @@
                         { } \
                 }, pci) || HDA_CONTROLLER_IS_HSW(pci))
-
+#else
+#define HDA_CONTROLLER_IS_HSW(pci) 0
+#define HDA_CONTROLLER_IS_APL(pci) 0
+#define HDA_CONTROLLER_IN_GPU(pci) 0
+#endif
 #endif /* __SOUND_HDAUDIO_H */

GPL/branches/uniaud32-exp/alsa-kernel/include/uapi/sound/asound.h

@@ -28 +28 @@
 #ifndef __bitwise
 #define __bitwise
+#endif
+
+#ifndef __packed
+#define __packed
 #endif
 

GPL/branches/uniaud32-exp/alsa-kernel/pci/emu10k1/emu10k1_main.c

@@ -197 +197 @@
                 /* Hacks for Alice3 to work independent of haP16V driver */
                 /* Setup SRCMulti_I2S SamplingRate */
+#ifndef TARGET_OS2
                 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000);
-
+#else
+                tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
+                tmp &= 0xfffff1ff;
+                tmp |= (0x2<<9);
+                snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
+#endif
                 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
                 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
@@ -213 +219 @@
                 dev_info(emu->card->dev, "Audigy2 value: Special config.\n");
                 /* Setup SRCMulti_I2S SamplingRate */
+#ifndef TARGET_OS2
                 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, 0, A_I2S_CAPTURE_96000);
-
+#else
+                tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
+                tmp &= 0xfffff1ff;
+                tmp |= (0x2<<9);
+                snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
+#endif
                 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
                 snd_emu10k1_ptr20_write(emu, P17V_SRCSel, 0, 0x14);
@@ -780 +792 @@
 }
 
-+static void emu1010_dock_event(struct snd_emu10k1 *emu)
-+{
-+       u32 reg;
-+
+static void emu1010_dock_event(struct snd_emu10k1 *emu)
+{
+        u32 reg;
+
         snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg); /* OPTIONS: Which cards are attached to the EMU */
         if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) {

GPL/branches/uniaud32-exp/alsa-kernel/pci/emu10k1/emufx.c

@@ -1396 +1396 @@
         // We need to double the volume, as we configure the voices for half volume,
         // which is necessary for bit-identical reproduction.
-        { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); }
+        //{ static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); }
         for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++)
                 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000);

GPL/branches/uniaud32-exp/alsa-kernel/pci/emu10k1/emumixer.c

@@ -167 +167 @@
         EMU32_SRC_REGS,
 };
-static_assert(ARRAY_SIZE(emu1010_src_regs) == ARRAY_SIZE(emu1010_src_texts));
+//static_assert(ARRAY_SIZE(emu1010_src_regs) == ARRAY_SIZE(emu1010_src_texts));
 
 /* 1010 rev2 */
@@ -199 +199 @@
         EMU32_SRC_REGS,
 };
-static_assert(ARRAY_SIZE(emu1010b_src_regs) == ARRAY_SIZE(emu1010b_src_texts));
+//static_assert(ARRAY_SIZE(emu1010b_src_regs) == ARRAY_SIZE(emu1010b_src_texts));
 
 /* 1616(m) cardbus */
@@ -225 +225 @@
         EMU32_SRC_REGS,
 };
-static_assert(ARRAY_SIZE(emu1616_src_regs) == ARRAY_SIZE(emu1616_src_texts));
+//static_assert(ARRAY_SIZE(emu1616_src_regs) == ARRAY_SIZE(emu1616_src_texts));
 
 /* 0404 rev1 & rev2 */
@@ -245 +245 @@
         EMU32_SRC_REGS,
 };
-static_assert(ARRAY_SIZE(emu0404_src_regs) == ARRAY_SIZE(emu0404_src_texts));
+//static_assert(ARRAY_SIZE(emu0404_src_regs) == ARRAY_SIZE(emu0404_src_texts));
 
 /*
@@ -268 +268 @@
         ADAT_CTLS("1010 "),
 };
-static_assert(ARRAY_SIZE(emu1010_output_texts) <= NUM_OUTPUT_DESTS);
+//static_assert(ARRAY_SIZE(emu1010_output_texts) <= NUM_OUTPUT_DESTS);
 
 static const unsigned short emu1010_output_dst[] = {
@@ -281 +281 @@
         ADAT_REGS(EMU_DST_HANA_ADAT),
 };
-static_assert(ARRAY_SIZE(emu1010_output_dst) == ARRAY_SIZE(emu1010_output_texts));
+//static_assert(ARRAY_SIZE(emu1010_output_dst) == ARRAY_SIZE(emu1010_output_texts));
 
 static const unsigned short emu1010_output_dflt[] = {
@@ -295 +295 @@
         EMU_SRC_ALICE_EMU32A+4, EMU_SRC_ALICE_EMU32A+5, EMU_SRC_ALICE_EMU32A+6, EMU_SRC_ALICE_EMU32A+7,
 };
-static_assert(ARRAY_SIZE(emu1010_output_dflt) == ARRAY_SIZE(emu1010_output_dst));
+//static_assert(ARRAY_SIZE(emu1010_output_dflt) == ARRAY_SIZE(emu1010_output_dst));
 
 /* 1010 rev2 */
@@ -309 +309 @@
         ADAT_CTLS("1010 "),
 };
-static_assert(ARRAY_SIZE(snd_emu1010b_output_texts) <= NUM_OUTPUT_DESTS);
+//static_assert(ARRAY_SIZE(snd_emu1010b_output_texts) <= NUM_OUTPUT_DESTS);
 
 static const unsigned short emu1010b_output_dst[] = {
@@ -321 +321 @@
         ADAT_REGS(EMU_DST_HANA_ADAT),
 };
-static_assert(ARRAY_SIZE(emu1010b_output_dst) == ARRAY_SIZE(snd_emu1010b_output_texts));
+//static_assert(ARRAY_SIZE(emu1010b_output_dst) == ARRAY_SIZE(snd_emu1010b_output_texts));
 
 static const unsigned short emu1010b_output_dflt[] = {
@@ -346 +346 @@
         LR_CTLS("Mana DAC"),
 };
-static_assert(ARRAY_SIZE(snd_emu1616_output_texts) <= NUM_OUTPUT_DESTS);
+//static_assert(ARRAY_SIZE(snd_emu1616_output_texts) <= NUM_OUTPUT_DESTS);
 
 static const unsigned short emu1616_output_dst[] = {
@@ -356 +356 @@
         EMU_DST_MANA_DAC_LEFT, EMU_DST_MANA_DAC_RIGHT,
 };
-static_assert(ARRAY_SIZE(emu1616_output_dst) == ARRAY_SIZE(snd_emu1616_output_texts));
+//static_assert(ARRAY_SIZE(emu1616_output_dst) == ARRAY_SIZE(snd_emu1616_output_texts));
 
 static const unsigned short emu1616_output_dflt[] = {
@@ -367 +367 @@
         EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1,
 };
-static_assert(ARRAY_SIZE(emu1616_output_dflt) == ARRAY_SIZE(emu1616_output_dst));
+//static_assert(ARRAY_SIZE(emu1616_output_dflt) == ARRAY_SIZE(emu1616_output_dst));
 
 /* 0404 rev1 & rev2 */
@@ -375 +375 @@
         LR_CTLS("SPDIF"),
 };
-static_assert(ARRAY_SIZE(snd_emu0404_output_texts) <= NUM_OUTPUT_DESTS);
+//static_assert(ARRAY_SIZE(snd_emu0404_output_texts) <= NUM_OUTPUT_DESTS);
 
 static const unsigned short emu0404_output_dst[] = {
@@ -381 +381 @@
         LR_REGS(EMU_DST_HANA_SPDIF),
 };
-static_assert(ARRAY_SIZE(emu0404_output_dst) == ARRAY_SIZE(snd_emu0404_output_texts));
+//static_assert(ARRAY_SIZE(emu0404_output_dst) == ARRAY_SIZE(snd_emu0404_output_texts));
 
 static const unsigned short emu0404_output_dflt[] = {
@@ -387 +387 @@
         EMU_SRC_ALICE_EMU32A+0, EMU_SRC_ALICE_EMU32A+1,
 };
-static_assert(ARRAY_SIZE(emu0404_output_dflt) == ARRAY_SIZE(emu0404_output_dst));
+//static_assert(ARRAY_SIZE(emu0404_output_dflt) == ARRAY_SIZE(emu0404_output_dst));
 
 /*
@@ -420 +420 @@
         "DSP 15 Capture Enum",
 };
-static_assert(ARRAY_SIZE(emu1010_input_texts) <= NUM_INPUT_DESTS);
+//static_assert(ARRAY_SIZE(emu1010_input_texts) <= NUM_INPUT_DESTS);
 
 static const unsigned short emu1010_input_dst[] = {
@@ -447 +447 @@
         EMU_DST_ALICE_I2S2_RIGHT,
 };
-static_assert(ARRAY_SIZE(emu1010_input_dst) == ARRAY_SIZE(emu1010_input_texts));
+//static_assert(ARRAY_SIZE(emu1010_input_dst) == ARRAY_SIZE(emu1010_input_texts));
 
 static const unsigned short emu1010_input_dflt[] = {
@@ -477 +477 @@
         EMU_SRC_DOCK_ADC3_RIGHT1,
 };
-static_assert(ARRAY_SIZE(emu1010_input_dflt) == ARRAY_SIZE(emu1010_input_dst));
+//static_assert(ARRAY_SIZE(emu1010_input_dflt) == ARRAY_SIZE(emu1010_input_dst));
 
 static const unsigned short emu0404_input_dflt[] = {

GPL/branches/uniaud32-exp/alsa-kernel/pci/emu10k1/emuproc.c

@@ -430 +430 @@
                 "Unused", "EFX", "EFX IRQ", "PCM", "PCM IRQ", "Synth"
         };
-        static_assert(ARRAY_SIZE(types) == EMU10K1_NUM_TYPES);
+        //static_assert(ARRAY_SIZE(types) == EMU10K1_NUM_TYPES);
 
         snd_iprintf(buffer, "ch\tdirty\tlast\tuse\n");

GPL/branches/uniaud32-exp/alsa-kernel/pci/es1938.c

@@ -835 +835 @@
         if (snd_BUG_ON(pos + count > chip->dma1_size))
                 return -EINVAL;
+#ifndef TARGET_OS2
         if (pos + count < chip->dma1_size) {
                 if (copy_to_iter(runtime->dma_area + pos + 1, count, dst) != count)
@@ -844 +845 @@
                         return -EFAULT;
         }
+#else
+        if (pos + count < chip->dma1_size) {
+                if (copy_to_user(dst, runtime->dma_area + pos + 1, count))
+                        return -EFAULT;
+        } else {
+                if (copy_to_user(dst, runtime->dma_area + pos + 1, count - 1))
+                        return -EFAULT;
+                if (put_user(runtime->dma_area[0],
+                             ((unsigned char __user *)dst) + count - 1))
+                        return -EFAULT;
+        }
+#endif
         return 0;
 }

GPL/branches/uniaud32-exp/alsa-kernel/pci/hda/hda_component2.h

@@ -16 +16 @@
         char name[HDA_MAX_NAME_SIZE];
         struct hda_codec *codec;
+        void (*pre_playback_hook)(struct device *dev, int action);
         void (*playback_hook)(struct device *dev, int action);
-        int (*suspend_hook)(struct device *dev);
-        int (*resume_hook)(struct device *dev);
+        void (*post_playback_hook)(struct device *dev, int action);
 };

GPL/branches/uniaud32-exp/alsa-kernel/pci/hda/hda_intel.c

@@ -583 +583 @@
         snd_hdac_set_codec_wakeup(bus, false);
 
+#ifndef TARGET_OS2
         /* reduce dma latency to avoid noise */
         if (HDA_CONTROLLER_IS_APL(pci))
                 bxt_reduce_dma_latency(chip);
-
+#endif
         if (bus->mlcap != NULL)
                 intel_init_lctl(chip);
@@ -2212 +2213 @@
 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
 
-#ifndef CONFIG_SND_HDA_I915
+#if !defined(CONFIG_SND_HDA_I915) && !defined(TARGET_OS2)
         if (HDA_CONTROLLER_IN_GPU(pci))
                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");

GPL/branches/uniaud32-exp/alsa-kernel/pci/hda/patch_ca0132.c

@@ -1331 +1331 @@
         { .id = QUIRK_AE5, .name = "ae5" },
         { .id = QUIRK_AE7, .name = "ae7" },
-        {}
+        {0}
 };
 

GPL/branches/uniaud32-exp/alsa-kernel/pci/hda/patch_realtek.c

@@ -5616 +5616 @@
                                              const struct hda_fixup *fix, int action)
 {
-#if IS_ENABLED(CONFIG_INPUT)
+#if IS_ENABLED(CONFIG_INPUT) && !defined(TARGET_OS2)
         struct alc_spec *spec = codec->spec;
 
@@ -5652 +5652 @@
                                              const struct hda_fixup *fix, int action)
 {
+#if IS_ENABLED(CONFIG_INPUT)
         struct alc_spec *spec = codec->spec;
 
@@ -5673 +5674 @@
                 spec->kb_dev = NULL;
         }
+#endif
 }
 

GPL/branches/uniaud32-exp/alsa-kernel/pci/nm256/nm256.c

@@ -701 +701 @@
         struct nm256_stream *s = runtime->private_data;
 
+#ifndef TARGET_OS2
         return copy_from_iter_toio(s->bufptr + pos, src, count);
+#else
+        if (copy_from_user_toio(s->bufptr + pos, src, count))
+                return -EFAULT;
+        return 0;
+#endif
 }
 
@@ -715 +721 @@
         struct nm256_stream *s = runtime->private_data;
 
+#ifndef TARGET_OS2
         return copy_to_iter_fromio(dst, s->bufptr + pos, count);
+#else
+        if (copy_to_user_fromio(dst, s->bufptr + pos, count))
+                return -EFAULT;
+        return 0;
+#endif
 }
 

GPL/branches/uniaud32-exp/alsa-kernel/pci/ymfpci/ymfpci.h

@@ -310 +310 @@
 #define DSXG_PCI_NUM_SAVED_REGS ARRAY_SIZE(pci_saved_regs_index)
 #define DSXG_PCI_NUM_SAVED_LEGACY_REGS  2
+#ifndef TARGET_OS2
 static_assert(DSXG_PCI_NUM_SAVED_LEGACY_REGS <= DSXG_PCI_NUM_SAVED_REGS);
+#endif
 
 struct snd_ymfpci {

GPL/branches/uniaud32-exp/include/asm/uaccess.h

@@ -44 +44 @@
 int is_access_ok(int type, void *addr, unsigned long size);
 
-#define access_ok(type, addr, size) __access_ok((unsigned long)(addr),(size))
-
 /*
  * The architecture should really override this if possible, at least
@@ -54 +52 @@
         return 1;
 }
+
+#define access_ok(addr, size) __access_ok(addr, size)
 
 #define verify_area(type, addr, size) (access_ok(type, (void *)addr,size) ? 0 : -EFAULT)
@@ -235 +235 @@
 #define strlen_user(str) strnlen_user(str, ~0UL >> 1)
 long strnlen_user(const char *str, long n);
-unsigned long clear_user(void *mem, unsigned long len);
-unsigned long __clear_user(void *mem, unsigned long len);
+/*
+ * Zero Userspace
+ */
+#ifndef __clear_user
+static inline __must_check unsigned long
+__clear_user(void __user *to, unsigned long n)
+{
+        memset((void __force *)to, 0, n);
+        return 0;
+}
+#endif
+
+static inline __must_check unsigned long
+clear_user(void __user *to, unsigned long n)
+{
+        if (!access_ok(to, n))
+                return n;
+
+        return __clear_user(to, n);
+}
 
 #endif /* __i386_UACCESS_H */

GPL/branches/uniaud32-exp/include/linux/fs.h

@@ -336 +336 @@
 }
 
+#define MAX_RW_COUNT (INT_MAX & PAGE_MASK)
+
 #endif /* _LINUX_FS_H */

GPL/branches/uniaud32-exp/include/linux/ioport.h

@@ -12 +12 @@
 
 #include <linux/types.h>
+#include <linux/minmax.h>
+
 /*
  * Resources are tree-like, allowing

GPL/branches/uniaud32-exp/include/linux/kernel.h

@@ -17 +17 @@
 #include <linux/string.h>
 #include <linux/math.h>
+#include <linux/minmax.h>
 #include <linux/export.h>
 

GPL/branches/uniaud32-exp/include/linux/lockdep.h

@@ -19 +19 @@
                 do { (void)(key); (void)(name); } while (0)
 struct lock_class_key {int not_used; };
+
+#define lockdep_assert_held(l)
+#define lockdep_assert_not_held(l)
+#define lockdep_assert_held_write(l)
+#define lockdep_assert_held_read(l)
+#define lockdep_assert_held_once(l)
+#define lockdep_assert_none_held_once()
+
 #endif /* __LINUX_LOCKDEP_H */

GPL/branches/uniaud32-exp/include/linux/pci_ids.h

@@ -3 +3 @@
  *      PCI Class, Vendor and Device IDs
  *
- *      Please keep sorted.
+ *      Please keep sorted by numeric Vendor ID and Device ID.
  *
  *      Do not add new entries to this file unless the definitions
@@ -52 +52 @@
 #define PCI_CLASS_MEMORY_RAM            0x0500
 #define PCI_CLASS_MEMORY_FLASH          0x0501
+#define PCI_CLASS_MEMORY_CXL            0x0502
 #define PCI_CLASS_MEMORY_OTHER          0x0580
 
@@ -60 +61 @@
 #define PCI_CLASS_BRIDGE_MC             0x0603
 #define PCI_CLASS_BRIDGE_PCI            0x0604
+#define PCI_CLASS_BRIDGE_PCI_NORMAL             0x060400
+#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE        0x060401
 #define PCI_CLASS_BRIDGE_PCMCIA         0x0605
 #define PCI_CLASS_BRIDGE_NUBUS          0x0606
@@ -72 +75 @@
 #define PCI_CLASS_COMMUNICATION_MODEM   0x0703
 #define PCI_CLASS_COMMUNICATION_OTHER   0x0780
+
+/* Interface for SERIAL/MODEM */
+#define PCI_SERIAL_16550_COMPATIBLE     0x02
 
 #define PCI_BASE_CLASS_SYSTEM           0x08
@@ -82 +88 @@
 #define PCI_CLASS_SYSTEM_PCI_HOTPLUG    0x0804
 #define PCI_CLASS_SYSTEM_SDHCI          0x0805
+#define PCI_CLASS_SYSTEM_RCEC           0x0807
 #define PCI_CLASS_SYSTEM_OTHER          0x0880
 
@@ -118 +125 @@
 #define PCI_CLASS_SERIAL_FIBER          0x0c04
 #define PCI_CLASS_SERIAL_SMBUS          0x0c05
+#define PCI_CLASS_SERIAL_IPMI           0x0c07
+#define PCI_CLASS_SERIAL_IPMI_SMIC      0x0c0700
+#define PCI_CLASS_SERIAL_IPMI_KCS       0x0c0701
+#define PCI_CLASS_SERIAL_IPMI_BT        0x0c0702
 
 #define PCI_BASE_CLASS_WIRELESS                 0x0d
@@ -141 +152 @@
 #define PCI_CLASS_SP_OTHER              0x1180
 
+#define PCI_BASE_CLASS_ACCELERATOR      0x12
+#define PCI_CLASS_ACCELERATOR_PROCESSING        0x1200
+
 #define PCI_CLASS_OTHERS                0xff
 
 /* Vendors and devices.  Sort key: vendor first, device next. */
+#define PCI_VENDOR_ID_PCI_SIG           0x0001
+
+#define PCI_VENDOR_ID_LOONGSON          0x0014
+
+#define PCI_DEVICE_ID_LOONGSON_HDA      0x7a07
+#define PCI_DEVICE_ID_LOONGSON_HDMI     0x7a37
+
+#define PCI_VENDOR_ID_SOLIDIGM          0x025e
 
 #define PCI_VENDOR_ID_TTTECH            0x0357
@@ -150 +172 @@
 #define PCI_VENDOR_ID_DYNALINK          0x0675
 #define PCI_DEVICE_ID_DYNALINK_IS64PH   0x1702
+
+#define PCI_VENDOR_ID_UBIQUITI          0x0777
 
 #define PCI_VENDOR_ID_BERKOM                    0x0871
@@ -156 +180 @@
 #define PCI_DEVICE_ID_BERKOM_A4T                0xffa4
 #define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO      0xffa8
+
+#define PCI_VENDOR_ID_ITTIM             0x0b48
 
 #define PCI_VENDOR_ID_COMPAQ            0x0e11
@@ -540 +566 @@
 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
+#define PCI_DEVICE_ID_AMD_17H_DF_F3     0x1463
+#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
+#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b
+#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
+#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3 0x1727
+#define PCI_DEVICE_ID_AMD_19H_DF_F3     0x1653
+#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
+#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
+#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
+#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F3 0x14e3
+#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F3 0x14f3
+#define PCI_DEVICE_ID_AMD_19H_M78H_DF_F3 0x12fb
+#define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3 0x12c3
+#define PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3 0x16fb
+#define PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3 0x124b
+#define PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3 0x12bb
+#define PCI_DEVICE_ID_AMD_MI200_DF_F3   0x14d3
+#define PCI_DEVICE_ID_AMD_VANGOGH_USB   0x163a
 #define PCI_DEVICE_ID_AMD_CNB17H_F3     0x1703
 #define PCI_DEVICE_ID_AMD_LANCE         0x2000
@@ -560 +605 @@
 #define PCI_DEVICE_ID_AMD_VIPER_7443    0x7443
 #define PCI_DEVICE_ID_AMD_OPUS_7445     0x7445
+#define PCI_DEVICE_ID_AMD_GOLAM_7450    0x7450
 #define PCI_DEVICE_ID_AMD_8111_PCI      0x7460
 #define PCI_DEVICE_ID_AMD_8111_LPC      0x7468
@@ -614 +660 @@
 #define PCI_DEVICE_ID_DELL_RAC4         0x0012
 #define PCI_DEVICE_ID_DELL_PERC5        0x0015
+
+#define PCI_SUBVENDOR_ID_DELL           0x1028
 
 #define PCI_VENDOR_ID_MATROX            0x102B
@@ -866 +914 @@
 #define PCI_DEVICE_ID_TI_X420           0xac8e
 #define PCI_DEVICE_ID_TI_XX20_FM        0xac8f
+#define PCI_DEVICE_ID_TI_J721E          0xb00d
 #define PCI_DEVICE_ID_TI_DRA74x         0xb500
 #define PCI_DEVICE_ID_TI_DRA72x         0xb501
@@ -1061 +1110 @@
 #define PCI_DEVICE_ID_SGI_IOC3          0x0003
 #define PCI_DEVICE_ID_SGI_LITHIUM       0x1002
-#define PCI_DEVICE_ID_SGI_IOC4          0x100a
 
 #define PCI_VENDOR_ID_WINBOND           0x10ad
@@ -1102 +1150 @@
 
 #define PCI_VENDOR_ID_AL                0x10b9
+#define PCI_DEVICE_ID_AL_M1489          0x1489
 #define PCI_DEVICE_ID_AL_M1533          0x1533
-#define PCI_DEVICE_ID_AL_M1535          0x1535
+#define PCI_DEVICE_ID_AL_M1535          0x1535
 #define PCI_DEVICE_ID_AL_M1541          0x1541
 #define PCI_DEVICE_ID_AL_M1563          0x1563
@@ -1130 +1179 @@
 #define PCI_VENDOR_ID_TCONRAD           0x10da
 #define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
+
+#define PCI_VENDOR_ID_ROHM              0x10db
 
 #define PCI_VENDOR_ID_NVIDIA                    0x10de
@@ -1325 +1376 @@
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE       0x0759
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS     0x07D8
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_320M           0x08A0
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS     0x0AA2
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA      0x0D85
@@ -1562 +1614 @@
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA            0x1172
+
 #define PCI_VENDOR_ID_SBE               0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100      0x0301
@@ -1664 +1718 @@
 
 #define PCI_VENDOR_ID_PMC_Sierra        0x11f8
+#define PCI_VENDOR_ID_MICROSEMI         0x11f8
 
 #define PCI_VENDOR_ID_RP                0x11fe
-#define PCI_DEVICE_ID_RP32INTF          0x0001
-#define PCI_DEVICE_ID_RP8INTF           0x0002
-#define PCI_DEVICE_ID_RP16INTF          0x0003
-#define PCI_DEVICE_ID_RP4QUAD           0x0004
-#define PCI_DEVICE_ID_RP8OCTA           0x0005
-#define PCI_DEVICE_ID_RP8J              0x0006
-#define PCI_DEVICE_ID_RP4J              0x0007
-#define PCI_DEVICE_ID_RP8SNI            0x0008
-#define PCI_DEVICE_ID_RP16SNI           0x0009
-#define PCI_DEVICE_ID_RPP4              0x000A
-#define PCI_DEVICE_ID_RPP8              0x000B
-#define PCI_DEVICE_ID_RP4M              0x000D
-#define PCI_DEVICE_ID_RP2_232           0x000E
-#define PCI_DEVICE_ID_RP2_422           0x000F
-#define PCI_DEVICE_ID_URP32INTF         0x0801
-#define PCI_DEVICE_ID_URP8INTF          0x0802
-#define PCI_DEVICE_ID_URP16INTF         0x0803
-#define PCI_DEVICE_ID_URP8OCTA          0x0805
-#define PCI_DEVICE_ID_UPCI_RM3_8PORT    0x080C
-#define PCI_DEVICE_ID_UPCI_RM3_4PORT    0x080D
-#define PCI_DEVICE_ID_CRP16INTF         0x0903
 
 #define PCI_VENDOR_ID_CYCLADES          0x120e
-#define PCI_DEVICE_ID_CYCLOM_Y_Lo       0x0100
-#define PCI_DEVICE_ID_CYCLOM_Y_Hi       0x0101
-#define PCI_DEVICE_ID_CYCLOM_4Y_Lo      0x0102
-#define PCI_DEVICE_ID_CYCLOM_4Y_Hi      0x0103
-#define PCI_DEVICE_ID_CYCLOM_8Y_Lo      0x0104
-#define PCI_DEVICE_ID_CYCLOM_8Y_Hi      0x0105
-#define PCI_DEVICE_ID_CYCLOM_Z_Lo       0x0200
-#define PCI_DEVICE_ID_CYCLOM_Z_Hi       0x0201
 #define PCI_DEVICE_ID_PC300_RX_2        0x0300
 #define PCI_DEVICE_ID_PC300_RX_1        0x0301
@@ -1738 +1764 @@
 
 /* Allied Telesyn */
-#define PCI_VENDOR_ID_AT                0x1259
+#define PCI_VENDOR_ID_AT                0x1259
 #define PCI_SUBDEVICE_ID_AT_2700FX      0x2701
 #define PCI_SUBDEVICE_ID_AT_2701FX      0x2703
+
+#define PCI_VENDOR_ID_ASIX              0x125b
+#define PCI_DEVICE_ID_ASIX_AX99100      0x9100
+#define PCI_DEVICE_ID_ASIX_AX99100_LB   0x9110
 
 #define PCI_VENDOR_ID_ESS               0x125d
@@ -1813 +1843 @@
 #define PCI_VENDOR_ID_NVIDIA_SGS        0x12d2
 #define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCI_VENDOR_ID_PERICOM                   0x12D8
+#define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
+#define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
+#define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
+#define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
 
 #define PCI_SUBVENDOR_ID_CHASE_PCIFAST          0x12E0
@@ -1936 +1972 @@
 #define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM     0xc001
 #define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM 0xc002
+#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM            0xc021
+#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM        0xc022
 
 #define PCI_VENDOR_ID_KAWASAKI          0x136b
@@ -1958 +1996 @@
 
 #define PCI_VENDOR_ID_MOXA              0x1393
-#define PCI_DEVICE_ID_MOXA_RC7000       0x0001
-#define PCI_DEVICE_ID_MOXA_CP102        0x1020
-#define PCI_DEVICE_ID_MOXA_CP102UL      0x1021
-#define PCI_DEVICE_ID_MOXA_CP102U       0x1022
-#define PCI_DEVICE_ID_MOXA_C104         0x1040
-#define PCI_DEVICE_ID_MOXA_CP104U       0x1041
-#define PCI_DEVICE_ID_MOXA_CP104JU      0x1042
-#define PCI_DEVICE_ID_MOXA_CP104EL      0x1043
-#define PCI_DEVICE_ID_MOXA_CT114        0x1140
-#define PCI_DEVICE_ID_MOXA_CP114        0x1141
-#define PCI_DEVICE_ID_MOXA_CP118U       0x1180
-#define PCI_DEVICE_ID_MOXA_CP118EL      0x1181
-#define PCI_DEVICE_ID_MOXA_CP132        0x1320
-#define PCI_DEVICE_ID_MOXA_CP132U       0x1321
-#define PCI_DEVICE_ID_MOXA_CP134U       0x1340
-#define PCI_DEVICE_ID_MOXA_C168         0x1680
-#define PCI_DEVICE_ID_MOXA_CP168U       0x1681
-#define PCI_DEVICE_ID_MOXA_CP168EL      0x1682
 #define PCI_DEVICE_ID_MOXA_CP204J       0x2040
 #define PCI_DEVICE_ID_MOXA_C218         0x2180
@@ -2035 +2055 @@
 
 #define PCI_VENDOR_ID_MICROGATE         0x13c0
-#define PCI_DEVICE_ID_MICROGATE_USC     0x0010
-#define PCI_DEVICE_ID_MICROGATE_SCA     0x0030
 
 #define PCI_VENDOR_ID_3WARE             0x13C1
@@ -2086 +2104 @@
 #define PCI_DEVICE_ID_VT1724            0x1724
 
+#define PCI_VENDOR_ID_MICROSOFT         0x1414
+#define PCI_DEVICE_ID_HYPERV_VIDEO      0x5353
+
 #define PCI_VENDOR_ID_OXSEMI            0x1415
 #define PCI_DEVICE_ID_OXSEMI_12PCI840   0x8403
@@ -2106 +2127 @@
 #define PCI_VENDOR_ID_CHELSIO           0x1425
 
+#define PCI_VENDOR_ID_EDIMAX            0x1432
+
 #define PCI_VENDOR_ID_ADLINK            0x144a
 
@@ -2115 +2138 @@
 
 #define PCI_VENDOR_ID_MYRICOM           0x14c1
+
+#define PCI_VENDOR_ID_MEDIATEK          0x14c3
+#define PCI_DEVICE_ID_MEDIATEK_7629     0x7629
 
 #define PCI_VENDOR_ID_TITAN             0x14D2
@@ -2347 +2373 @@
 
 #define PCI_VENDOR_ID_SYNOPSYS          0x16c3
+#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3         0xabcd
+#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI     0xabce
+#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31        0xabcf
+#define PCI_DEVICE_ID_SYNOPSYS_EDDA     0xedda
+
+#define PCI_VENDOR_ID_USR               0x16ec
 
 #define PCI_VENDOR_ID_VITESSE           0x1725
@@ -2382 +2414 @@
 #define PCI_DEVICE_ID_RDC_D1010         0x1010
 
+#define PCI_VENDOR_ID_GLI               0x17a0
+
 #define PCI_VENDOR_ID_LENOVO            0x17aa
+
+#define PCI_VENDOR_ID_QCOM              0x17cb
+
+#define PCI_VENDOR_ID_CDNS              0x17cd
 
 #define PCI_VENDOR_ID_ARECA             0x17d3
@@ -2434 +2472 @@
 #define PCI_DEVICE_ID_TDI_EHCI          0x0101
 
-#define PCI_VENDOR_ID_FREESCALE         0x1957
+#define PCI_VENDOR_ID_FREESCALE         0x1957  /* duplicate: NXP */
+#define PCI_VENDOR_ID_NXP               0x1957  /* duplicate: FREESCALE */
 #define PCI_DEVICE_ID_MPC8308           0xc006
 #define PCI_DEVICE_ID_MPC8315E          0x00b4
@@ -2525 +2564 @@
 #define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff
 
-#define PCI_VENDOR_ID_HUAWEI            0x19e5
+#define PCI_VENDOR_ID_HUAWEI            0x19e5
+#define PCI_DEVICE_ID_HUAWEI_ZIP_VF     0xa251
+#define PCI_DEVICE_ID_HUAWEI_SEC_VF     0xa256
+#define PCI_DEVICE_ID_HUAWEI_HPRE_VF    0xa259
 
 #define PCI_VENDOR_ID_NETRONOME         0x19ee
-#define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200
-#define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
+#define PCI_DEVICE_ID_NETRONOME_NFP3800 0x3800
 #define PCI_DEVICE_ID_NETRONOME_NFP4000 0x4000
+#define PCI_DEVICE_ID_NETRONOME_NFP5000 0x5000
 #define PCI_DEVICE_ID_NETRONOME_NFP6000 0x6000
+#define PCI_DEVICE_ID_NETRONOME_NFP3800_VF      0x3803
 #define PCI_DEVICE_ID_NETRONOME_NFP6000_VF      0x6003
 
@@ -2544 +2587 @@
 #define PCI_VENDOR_ID_ASMEDIA           0x1b21
 
+#define PCI_VENDOR_ID_REDHAT            0x1b36
+
+#define PCI_VENDOR_ID_SILICOM_DENMARK   0x1c2c
+
+#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS     0x1c36
+
 #define PCI_VENDOR_ID_CIRCUITCO         0x1cc8
 #define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD  0x0001
+
+#define PCI_VENDOR_ID_AMAZON            0x1d0f
+
+#define PCI_VENDOR_ID_ZHAOXIN           0x1d17
+
+#define PCI_VENDOR_ID_HYGON             0x1d94
+
+#define PCI_VENDOR_ID_FUNGIBLE          0x1dad
+
+#define PCI_VENDOR_ID_HXT               0x1dbf
 
 #define PCI_VENDOR_ID_TEKRAM            0x1de1
@@ -2554 +2613 @@
 #define PCI_DEVICE_ID_TEHUTI_3010       0x3010
 #define PCI_DEVICE_ID_TEHUTI_3014       0x3014
+
+#define PCI_VENDOR_ID_SUNIX             0x1fd4
+#define PCI_DEVICE_ID_SUNIX_1999        0x1999
 
 #define PCI_VENDOR_ID_HINT             0x3388
@@ -2594 +2656 @@
 #define PCI_DEVICE_ID_DCI_PCCOM2        0x0004
 
+#define PCI_VENDOR_ID_GLENFLY           0x6766
+
 #define PCI_VENDOR_ID_INTEL             0x8086
 #define PCI_DEVICE_ID_INTEL_EESSC       0x0008
+#define PCI_DEVICE_ID_INTEL_HDA_CML_LP  0x02c8
 #define PCI_DEVICE_ID_INTEL_PXHD_0      0x0320
 #define PCI_DEVICE_ID_INTEL_PXHD_1      0x0321
 #define PCI_DEVICE_ID_INTEL_PXH_0       0x0329
-#define PCI_DEVICE_ID_INTEL_PXH_1       0x032A
-#define PCI_DEVICE_ID_INTEL_PXHV        0x032C
+#define PCI_DEVICE_ID_INTEL_PXH_1       0x032a
+#define PCI_DEVICE_ID_INTEL_PXHV        0x032c
 #define PCI_DEVICE_ID_INTEL_80332_0     0x0330
 #define PCI_DEVICE_ID_INTEL_80332_1     0x0332
 #define PCI_DEVICE_ID_INTEL_80333_0     0x0370
 #define PCI_DEVICE_ID_INTEL_80333_1     0x0372
+#define PCI_DEVICE_ID_INTEL_QAT_DH895XCC        0x0435
+#define PCI_DEVICE_ID_INTEL_QAT_DH895XCC_VF     0x0443
 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 #define PCI_DEVICE_ID_INTEL_82378       0x0484
+#define PCI_DEVICE_ID_INTEL_82425       0x0486
+#define PCI_DEVICE_ID_INTEL_HDA_CML_H   0x06c8
 #define PCI_DEVICE_ID_INTEL_MRST_SD0    0x0807
 #define PCI_DEVICE_ID_INTEL_MRST_SD1    0x0808
+#define PCI_DEVICE_ID_INTEL_HDA_OAKTRAIL        0x080a
 #define PCI_DEVICE_ID_INTEL_MFD_SD      0x0820
 #define PCI_DEVICE_ID_INTEL_MFD_SDIO1   0x0821
@@ -2615 +2685 @@
 #define PCI_DEVICE_ID_INTEL_MFD_EMMC0   0x0823
 #define PCI_DEVICE_ID_INTEL_MFD_EMMC1   0x0824
-#define PCI_DEVICE_ID_INTEL_MRST_SD2    0x084F
-#define PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB     0x095E
+#define PCI_DEVICE_ID_INTEL_MRST_SD2    0x084f
+#define PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB     0x095e
 #define PCI_DEVICE_ID_INTEL_I960        0x0960
 #define PCI_DEVICE_ID_INTEL_I960RM      0x0962
+#define PCI_DEVICE_ID_INTEL_HDA_HSW_0   0x0a0c
+#define PCI_DEVICE_ID_INTEL_DSA_SPR0    0x0b25
+#define PCI_DEVICE_ID_INTEL_HDA_HSW_2   0x0c0c
 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB       0x0c60
+#define PCI_DEVICE_ID_INTEL_IAX_SPR0    0x0cfe
+#define PCI_DEVICE_ID_INTEL_HDA_HSW_3   0x0d0c
+#define PCI_DEVICE_ID_INTEL_HDA_BYT     0x0f04
+#define PCI_DEVICE_ID_INTEL_SST_BYT     0x0f28
 #define PCI_DEVICE_ID_INTEL_8257X_SOL   0x1062
 #define PCI_DEVICE_ID_INTEL_82573E_SOL  0x1085
-#define PCI_DEVICE_ID_INTEL_82573L_SOL  0x108F
+#define PCI_DEVICE_ID_INTEL_82573L_SOL  0x108f
 #define PCI_DEVICE_ID_INTEL_82815_MC    0x1130
 #define PCI_DEVICE_ID_INTEL_82815_CGC   0x1132
+#define PCI_DEVICE_ID_INTEL_SST_TNG     0x119a
 #define PCI_DEVICE_ID_INTEL_82092AA_0   0x1221
-#define PCI_DEVICE_ID_INTEL_7505_0      0x2550
-#define PCI_DEVICE_ID_INTEL_7205_0      0x255d
 #define PCI_DEVICE_ID_INTEL_82437       0x122d
 #define PCI_DEVICE_ID_INTEL_82371FB_0   0x122e
@@ -2653 +2729 @@
 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI     0x1577
 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE  0x1578
+#define PCI_DEVICE_ID_INTEL_HDA_BDW     0x160c
 #define PCI_DEVICE_ID_INTEL_80960_RP    0x1960
+#define PCI_DEVICE_ID_INTEL_QAT_C3XXX   0x19e2
+#define PCI_DEVICE_ID_INTEL_QAT_C3XXX_VF        0x19e3
 #define PCI_DEVICE_ID_INTEL_82840_HB    0x1a21
 #define PCI_DEVICE_ID_INTEL_82845_HB    0x1a30
 #define PCI_DEVICE_ID_INTEL_IOAT        0x1a38
+#define PCI_DEVICE_ID_INTEL_HDA_CPT     0x1c20
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
+#define PCI_DEVICE_ID_INTEL_HDA_PBG     0x1d20
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0      0x1d40
 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1      0x1d41
+#define PCI_DEVICE_ID_INTEL_HDA_PPT     0x1e20
 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI   0x1e31
 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN        0x1e40
 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX        0x1e5f
+#define PCI_DEVICE_ID_INTEL_VMD_201D    0x201d
+#define PCI_DEVICE_ID_INTEL_HDA_BSW     0x2284
+#define PCI_DEVICE_ID_INTEL_SST_BSW     0x22a8
 #define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN    0x2310
 #define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX    0x231f
@@ -2713 +2798 @@
 #define PCI_DEVICE_ID_INTEL_82801EB_12  0x24dc
 #define PCI_DEVICE_ID_INTEL_82801EB_13  0x24dd
-#define PCI_DEVICE_ID_INTEL_ESB_1       0x25a1
-#define PCI_DEVICE_ID_INTEL_ESB_2       0x25a2
-#define PCI_DEVICE_ID_INTEL_ESB_4       0x25a4
-#define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
-#define PCI_DEVICE_ID_INTEL_ESB_9       0x25ab
-#define PCI_DEVICE_ID_INTEL_ESB_10      0x25ac
 #define PCI_DEVICE_ID_INTEL_82820_HB    0x2500
 #define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
@@ -2724 +2803 @@
 #define PCI_DEVICE_ID_INTEL_82860_HB    0x2531
 #define PCI_DEVICE_ID_INTEL_E7501_MCH   0x254c
+#define PCI_DEVICE_ID_INTEL_7505_0      0x2550
+#define PCI_DEVICE_ID_INTEL_7205_0      0x255d
 #define PCI_DEVICE_ID_INTEL_82845G_HB   0x2560
 #define PCI_DEVICE_ID_INTEL_82845G_IG   0x2562
@@ -2733 +2814 @@
 #define PCI_DEVICE_ID_INTEL_82915GM_HB  0x2590
 #define PCI_DEVICE_ID_INTEL_82915GM_IG  0x2592
-#define PCI_DEVICE_ID_INTEL_5000_ERR    0x25F0
-#define PCI_DEVICE_ID_INTEL_5000_FBD0   0x25F5
-#define PCI_DEVICE_ID_INTEL_5000_FBD1   0x25F6
-#define PCI_DEVICE_ID_INTEL_82945G_HB   0x2770
-#define PCI_DEVICE_ID_INTEL_82945G_IG   0x2772
-#define PCI_DEVICE_ID_INTEL_3000_HB     0x2778
-#define PCI_DEVICE_ID_INTEL_82945GM_HB  0x27A0
-#define PCI_DEVICE_ID_INTEL_82945GM_IG  0x27A2
+#define PCI_DEVICE_ID_INTEL_ESB_1       0x25a1
+#define PCI_DEVICE_ID_INTEL_ESB_2       0x25a2
+#define PCI_DEVICE_ID_INTEL_ESB_4       0x25a4
+#define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
+#define PCI_DEVICE_ID_INTEL_ESB_9       0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_10      0x25ac
+#define PCI_DEVICE_ID_INTEL_5000_ERR    0x25f0
+#define PCI_DEVICE_ID_INTEL_5000_FBD0   0x25f5
+#define PCI_DEVICE_ID_INTEL_5000_FBD1   0x25f6
 #define PCI_DEVICE_ID_INTEL_ICH6_0      0x2640
 #define PCI_DEVICE_ID_INTEL_ICH6_1      0x2641
 #define PCI_DEVICE_ID_INTEL_ICH6_2      0x2642
+#define PCI_DEVICE_ID_INTEL_HDA_ICH6    0x2668
 #define PCI_DEVICE_ID_INTEL_ICH6_16     0x266a
 #define PCI_DEVICE_ID_INTEL_ICH6_17     0x266d
@@ -2750 +2833 @@
 #define PCI_DEVICE_ID_INTEL_ESB2_0      0x2670
 #define PCI_DEVICE_ID_INTEL_ESB2_14     0x2698
+#define PCI_DEVICE_ID_INTEL_HDA_ESB2    0x269a
 #define PCI_DEVICE_ID_INTEL_ESB2_17     0x269b
 #define PCI_DEVICE_ID_INTEL_ESB2_18     0x269e
+#define PCI_DEVICE_ID_INTEL_82945G_HB   0x2770
+#define PCI_DEVICE_ID_INTEL_82945G_IG   0x2772
+#define PCI_DEVICE_ID_INTEL_3000_HB     0x2778
+#define PCI_DEVICE_ID_INTEL_82945GM_HB  0x27a0
+#define PCI_DEVICE_ID_INTEL_82945GM_IG  0x27a2
+#define PCI_DEVICE_ID_INTEL_ICH7_30     0x27b0
 #define PCI_DEVICE_ID_INTEL_ICH7_0      0x27b8
 #define PCI_DEVICE_ID_INTEL_ICH7_1      0x27b9
-#define PCI_DEVICE_ID_INTEL_ICH7_30     0x27b0
 #define PCI_DEVICE_ID_INTEL_TGP_LPC     0x27bc
 #define PCI_DEVICE_ID_INTEL_ICH7_31     0x27bd
+#define PCI_DEVICE_ID_INTEL_HDA_ICH7    0x27d8
 #define PCI_DEVICE_ID_INTEL_ICH7_17     0x27da
 #define PCI_DEVICE_ID_INTEL_ICH7_19     0x27dd
@@ -2767 +2857 @@
 #define PCI_DEVICE_ID_INTEL_ICH8_4      0x2815
 #define PCI_DEVICE_ID_INTEL_ICH8_5      0x283e
+#define PCI_DEVICE_ID_INTEL_HDA_ICH8    0x284b
 #define PCI_DEVICE_ID_INTEL_ICH8_6      0x2850
+#define PCI_DEVICE_ID_INTEL_VMD_28C0    0x28c0
 #define PCI_DEVICE_ID_INTEL_ICH9_0      0x2910
-#define PCI_DEVICE_ID_INTEL_ICH9_1      0x2917
 #define PCI_DEVICE_ID_INTEL_ICH9_2      0x2912
 #define PCI_DEVICE_ID_INTEL_ICH9_3      0x2913
 #define PCI_DEVICE_ID_INTEL_ICH9_4      0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_1      0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
 #define PCI_DEVICE_ID_INTEL_ICH9_5      0x2919
 #define PCI_DEVICE_ID_INTEL_ICH9_6      0x2930
-#define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
-#define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
+#define PCI_DEVICE_ID_INTEL_HDA_ICH9_0  0x293e
+#define PCI_DEVICE_ID_INTEL_HDA_ICH9_1  0x293f
 #define PCI_DEVICE_ID_INTEL_I7_MCR      0x2c18
 #define PCI_DEVICE_ID_INTEL_I7_MC_TAD   0x2c19
@@ -2793 +2887 @@
 #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK  0x2c32
 #define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC    0x2c33
+#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
 #define PCI_DEVICE_ID_INTEL_I7_NONCORE  0x2c41
-#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE     0x2c50
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51
@@ -2803 +2897 @@
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR         0x2c98
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD      0x2c99
-#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST     0x2c9C
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST     0x2c9c
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL 0x2ca0
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR 0x2ca1
@@ -2828 +2922 @@
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2
 #define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3
+#define PCI_DEVICE_ID_INTEL_HDA_GML     0x3198
 #define PCI_DEVICE_ID_INTEL_82855PM_HB  0x3340
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG4   0x3429
@@ -2838 +2933 @@
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG2   0x3432
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG3   0x3433
+#define PCI_DEVICE_ID_INTEL_HDA_ICL_LP  0x34c8
 #define PCI_DEVICE_ID_INTEL_82830_HB    0x3575
 #define PCI_DEVICE_ID_INTEL_82830_CGC   0x3577
+#define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580
+#define PCI_DEVICE_ID_INTEL_82855GM_IG  0x3582
 #define PCI_DEVICE_ID_INTEL_82854_HB    0x358c
 #define PCI_DEVICE_ID_INTEL_82854_IG    0x358e
-#define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580
-#define PCI_DEVICE_ID_INTEL_82855GM_IG  0x3582
 #define PCI_DEVICE_ID_INTEL_E7520_MCH   0x3590
 #define PCI_DEVICE_ID_INTEL_E7320_MCH   0x3592
@@ -2853 +2949 @@
 #define PCI_DEVICE_ID_INTEL_MCH_PC1     0x359a
 #define PCI_DEVICE_ID_INTEL_E7525_MCH   0x359e
+#define PCI_DEVICE_ID_INTEL_IOAT_CNB    0x360b
+#define PCI_DEVICE_ID_INTEL_FBD_CNB     0x360c
 #define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c
 #define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f
 #define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610
-#define PCI_DEVICE_ID_INTEL_IOAT_CNB    0x360b
-#define PCI_DEVICE_ID_INTEL_FBD_CNB     0x360c
 #define PCI_DEVICE_ID_INTEL_IOAT_JSF0   0x3710
 #define PCI_DEVICE_ID_INTEL_IOAT_JSF1   0x3711
@@ -2868 +2964 @@
 #define PCI_DEVICE_ID_INTEL_IOAT_JSF8   0x3718
 #define PCI_DEVICE_ID_INTEL_IOAT_JSF9   0x3719
+#define PCI_DEVICE_ID_INTEL_QAT_C62X    0x37c8
+#define PCI_DEVICE_ID_INTEL_QAT_C62X_VF 0x37c9
+#define PCI_DEVICE_ID_INTEL_HDA_ICL_N   0x38c8
 #define PCI_DEVICE_ID_INTEL_ICH10_0     0x3a14
 #define PCI_DEVICE_ID_INTEL_ICH10_1     0x3a16
@@ -2873 +2972 @@
 #define PCI_DEVICE_ID_INTEL_ICH10_3     0x3a1a
 #define PCI_DEVICE_ID_INTEL_ICH10_4     0x3a30
+#define PCI_DEVICE_ID_INTEL_HDA_ICH10_0 0x3a3e
 #define PCI_DEVICE_ID_INTEL_ICH10_5     0x3a60
+#define PCI_DEVICE_ID_INTEL_HDA_ICH10_1 0x3a6e
 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN       0x3b00
 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX       0x3b1f
+#define PCI_DEVICE_ID_INTEL_HDA_5_3400_SERIES_0 0x3b56
+#define PCI_DEVICE_ID_INTEL_HDA_5_3400_SERIES_1 0x3b57
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB0   0x3c20
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB1   0x3c21
@@ -2886 +2989 @@
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB8   0x3c2e
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB9   0x3c2f
-#define PCI_DEVICE_ID_INTEL_UNC_HA      0x3c46
-#define PCI_DEVICE_ID_INTEL_UNC_IMC0    0x3cb0
-#define PCI_DEVICE_ID_INTEL_UNC_IMC1    0x3cb1
-#define PCI_DEVICE_ID_INTEL_UNC_IMC2    0x3cb4
-#define PCI_DEVICE_ID_INTEL_UNC_IMC3    0x3cb5
 #define PCI_DEVICE_ID_INTEL_UNC_QPI0    0x3c41
 #define PCI_DEVICE_ID_INTEL_UNC_QPI1    0x3c42
@@ -2896 +2994 @@
 #define PCI_DEVICE_ID_INTEL_UNC_R3QPI0  0x3c44
 #define PCI_DEVICE_ID_INTEL_UNC_R3QPI1  0x3c45
+#define PCI_DEVICE_ID_INTEL_UNC_HA      0x3c46
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS     0x3c71  /* 15.1 */
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0    0x3c72  /* 16.2 */
@@ -2907 +3006 @@
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2    0x3cac  /* 15.4 */
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3    0x3cad  /* 15.5 */
+#define PCI_DEVICE_ID_INTEL_UNC_IMC0    0x3cb0
+#define PCI_DEVICE_ID_INTEL_UNC_IMC1    0x3cb1
+#define PCI_DEVICE_ID_INTEL_UNC_IMC2    0x3cb4
+#define PCI_DEVICE_ID_INTEL_UNC_IMC3    0x3cb5
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO   0x3cb8  /* 17.0 */
 #define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX       0x3ce0
@@ -2912 +3015 @@
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR          0x3cf5  /* 13.6 */
 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1        0x3cf6  /* 12.7 */
+#define PCI_DEVICE_ID_INTEL_HDA_ICL_H   0x3dc8
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB    0x402f
+#define PCI_DEVICE_ID_INTEL_5400_ERR    0x4030
+#define PCI_DEVICE_ID_INTEL_5400_FBD0   0x4035
+#define PCI_DEVICE_ID_INTEL_5400_FBD1   0x4036
+#define PCI_DEVICE_ID_INTEL_HDA_TGL_H   0x43c8
+#define PCI_DEVICE_ID_INTEL_HDA_DG1     0x490d
+#define PCI_DEVICE_ID_INTEL_HDA_EHL_0   0x4b55
+#define PCI_DEVICE_ID_INTEL_HDA_EHL_3   0x4b58
+#define PCI_DEVICE_ID_INTEL_HDA_JSL_N   0x4dc8
+#define PCI_DEVICE_ID_INTEL_HDA_DG2_0   0x4f90
+#define PCI_DEVICE_ID_INTEL_HDA_DG2_1   0x4f91
+#define PCI_DEVICE_ID_INTEL_HDA_DG2_2   0x4f92
+#define PCI_DEVICE_ID_INTEL_EP80579_0   0x5031
+#define PCI_DEVICE_ID_INTEL_EP80579_1   0x5032
+#define PCI_DEVICE_ID_INTEL_HDA_ADL_P   0x51c8
+#define PCI_DEVICE_ID_INTEL_HDA_ADL_PS  0x51c9
+#define PCI_DEVICE_ID_INTEL_HDA_RPL_P_0 0x51ca
+#define PCI_DEVICE_ID_INTEL_HDA_RPL_P_1 0x51cb
+#define PCI_DEVICE_ID_INTEL_HDA_ADL_M   0x51cc
+#define PCI_DEVICE_ID_INTEL_HDA_ADL_PX  0x51cd
+#define PCI_DEVICE_ID_INTEL_HDA_RPL_M   0x51ce
+#define PCI_DEVICE_ID_INTEL_HDA_RPL_PX  0x51cf
+#define PCI_DEVICE_ID_INTEL_HDA_ADL_N   0x54c8
+#define PCI_DEVICE_ID_INTEL_HDA_APL     0x5a98
 #define PCI_DEVICE_ID_INTEL_5100_16     0x65f0
 #define PCI_DEVICE_ID_INTEL_5100_19     0x65f3
 #define PCI_DEVICE_ID_INTEL_5100_21     0x65f5
 #define PCI_DEVICE_ID_INTEL_5100_22     0x65f6
-#define PCI_DEVICE_ID_INTEL_5400_ERR    0x4030
-#define PCI_DEVICE_ID_INTEL_5400_FBD0   0x4035
-#define PCI_DEVICE_ID_INTEL_5400_FBD1   0x4036
 #define PCI_DEVICE_ID_INTEL_IOAT_SCNB   0x65ff
-#define PCI_DEVICE_ID_INTEL_EP80579_0   0x5031
-#define PCI_DEVICE_ID_INTEL_EP80579_1   0x5032
 #define PCI_DEVICE_ID_INTEL_82371SB_0   0x7000
 #define PCI_DEVICE_ID_INTEL_82371SB_1   0x7010
@@ -2952 +3074 @@
 #define PCI_DEVICE_ID_INTEL_82372FB_1   0x7601
 #define PCI_DEVICE_ID_INTEL_HDA_ARL     0x7728
+#define PCI_DEVICE_ID_INTEL_HDA_RPL_S   0x7a50
+#define PCI_DEVICE_ID_INTEL_HDA_ADL_S   0x7ad0
+#define PCI_DEVICE_ID_INTEL_HDA_MTL     0x7e28
+#define PCI_DEVICE_ID_INTEL_HDA_ARL_S   0x7f50
 #define PCI_DEVICE_ID_INTEL_SCH_LPC     0x8119
 #define PCI_DEVICE_ID_INTEL_SCH_IDE     0x811a
+#define PCI_DEVICE_ID_INTEL_HDA_POULSBO 0x811b
 #define PCI_DEVICE_ID_INTEL_E6XX_CU     0x8183
 #define PCI_DEVICE_ID_INTEL_ITC_LPC     0x8186
@@ -2962 +3089 @@
 #define PCI_DEVICE_ID_INTEL_84460GX     0x84ea
 #define PCI_DEVICE_ID_INTEL_IXP4XX      0x8500
+#define PCI_DEVICE_ID_INTEL_HDA_LPT     0x8c20
+#define PCI_DEVICE_ID_INTEL_HDA_9_SERIES        0x8ca0
+#define PCI_DEVICE_ID_INTEL_HDA_WBG_0   0x8d20
+#define PCI_DEVICE_ID_INTEL_HDA_WBG_1   0x8d21
 #define PCI_DEVICE_ID_INTEL_IXP2800     0x9004
+#define PCI_DEVICE_ID_INTEL_HDA_LKF     0x98c8
+#define PCI_DEVICE_ID_INTEL_VMD_9A0B    0x9a0b
+#define PCI_DEVICE_ID_INTEL_HDA_LPT_LP_0        0x9c20
+#define PCI_DEVICE_ID_INTEL_HDA_LPT_LP_1        0x9c21
+#define PCI_DEVICE_ID_INTEL_HDA_WPT_LP  0x9ca0
+#define PCI_DEVICE_ID_INTEL_HDA_SKL_LP  0x9d70
+#define PCI_DEVICE_ID_INTEL_HDA_KBL_LP  0x9d71
+#define PCI_DEVICE_ID_INTEL_HDA_CNL_LP  0x9dc8
+#define PCI_DEVICE_ID_INTEL_HDA_TGL_LP  0xa0c8
+#define PCI_DEVICE_ID_INTEL_HDA_SKL     0xa170
+#define PCI_DEVICE_ID_INTEL_HDA_KBL     0xa171
+#define PCI_DEVICE_ID_INTEL_HDA_LBG_0   0xa1f0
+#define PCI_DEVICE_ID_INTEL_HDA_LBG_1   0xa270
+#define PCI_DEVICE_ID_INTEL_HDA_KBL_H   0xa2f0
+#define PCI_DEVICE_ID_INTEL_HDA_CNL_H   0xa348
+#define PCI_DEVICE_ID_INTEL_HDA_CML_S   0xa3f0
+#define PCI_DEVICE_ID_INTEL_HDA_LNL_P   0xa828
 #define PCI_DEVICE_ID_INTEL_S21152BB    0xb152
+#define PCI_DEVICE_ID_INTEL_HDA_CML_R   0xf0c8
+#define PCI_DEVICE_ID_INTEL_HDA_RKL_S   0xf1c8
+
+#define PCI_VENDOR_ID_WANGXUN           0x8088
 
 #define PCI_VENDOR_ID_SCALEMP           0x8686
@@ -3045 +3197 @@
 #define PCI_VENDOR_ID_3COM_2            0xa727
 
+#define PCI_VENDOR_ID_SOLIDRUN          0xd063
+
 #define PCI_VENDOR_ID_DIGIUM            0xd161
 #define PCI_DEVICE_ID_DIGIUM_HFC4S      0xb410

GPL/branches/uniaud32-exp/include/linux/pm.h

@@ -295 +295 @@
  * to RAM and hibernation.
  */
+#define DEFINE_SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \
+const struct dev_pm_ops name = { \
+        SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \
+}
+
+
 #define SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \
 const struct dev_pm_ops name = { \
@@ -342 +348 @@
 #define PMSG_THAW       0
 #define PMSG_RESTORE    0
-
+#define pm_sleep_ptr(_ptr) _ptr
 #endif /* _LINUX_PM_H */

GPL/branches/uniaud32-exp/include/linux/regmap.h

@@ -45 +45 @@
         REGCACHE_COMPRESSED,
         REGCACHE_FLAT,
+        REGCACHE_MAPLE,
 };
 
@@ -1120 +1121 @@
 void regcache_cache_bypass(struct regmap *map, bool enable);
 void regcache_mark_dirty(struct regmap *map);
+bool regcache_reg_cached(struct regmap *map, unsigned int reg);
 
 bool regmap_check_range_table(struct regmap *map, unsigned int reg,

GPL/branches/uniaud32-exp/include/linux/uaccess.h

@@ -2 +2 @@
 #define _LINUX_UACCESS_H
 #include <asm/uaccess.h>
+#include <linux/minmax.h>
 
 #endif /* _LINUX_UACCESS_H */

GPL/branches/uniaud32-exp/include/linux/uio.h

@@ -4 +4 @@
 #define _LINUX_UIO_H
 
-enum {
-        ITER_IOVEC = 0,
-        ITER_KVEC = 2,
-        ITER_BVEC = 4,
+#include <linux/types.h>
+
+enum iter_type {
+        /* iter types */
+        ITER_IOVEC,
+        ITER_KVEC,
+        ITER_BVEC,
+        ITER_XARRAY,
+        ITER_DISCARD,
+        ITER_UBUF,
+};
+
+#define ITER_SOURCE     1       // == WRITE
+#define ITER_DEST       0       // == READ
+
+struct kvec {
+        void *iov_base; /* and that should *never* hold a userland pointer */
+        size_t iov_len;
 };
 
@@ -20 +34 @@
 
 struct iov_iter {
-        int type;
-        size_t iov_offset;
-        size_t count;
+        u8 iter_type;
+        bool copy_mc;
+        bool nofault;
+        bool data_source;
+        bool user_backed;
+        union {
+                /*
+                 * This really should be a const, but we cannot do that without
+                 * also modifying any of the zero-filling iter init functions.
+                 * Leave it non-const for now, but it should be treated as such.
+                 */
+                struct iovec __ubuf_iovec;
+                struct {
+                        union {
+                                /* use iter_iov() to get the current vec */
+                                const struct iovec *__iov;
+                                void __user *ubuf;
+                        };
+                        size_t count;
+                };
+        };
         union {
                 const struct iovec *iov;
@@ -33 +65 @@
 static inline bool iter_is_iovec(const struct iov_iter *i)
 {
-        return !(i->type & (ITER_BVEC | ITER_KVEC));
+        return !(i->iter_type & (ITER_BVEC | ITER_KVEC));
 }
 
+static inline const struct iovec *iter_iov(const struct iov_iter *iter)
+{
+        if (iter->iter_type == ITER_UBUF)
+                return (const struct iovec *) &iter->__ubuf_iovec;
+        return iter->__iov;
+}
+int import_ubuf(int type, void __user *buf, size_t len, struct iov_iter *i);
+
 #endif /* _LINUX_UIO_H */

GPL/branches/uniaud32-exp/lib32/regcache.c

@@ -562 +562 @@
 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 
+/**
+ * regcache_reg_cached - Check if a register is cached
+ *
+ * @map: map to check
+ * @reg: register to check
+ *
+ * Reports if a register is cached.
+ */
+bool regcache_reg_cached(struct regmap *map, unsigned int reg)
+{
+        unsigned int val;
+        int ret;
+
+        map->lock(map->lock_arg);
+
+        ret = regcache_read(map, reg, &val);
+
+        map->unlock(map->lock_arg);
+
+        return ret == 0;
+}
+EXPORT_SYMBOL_GPL(regcache_reg_cached);
+
 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
                       unsigned int val)