Changeset 281 for GPL/branches/alsa-resync1/alsa-kernel/pci
- Timestamp:
- Jan 23, 2008, 7:05:10 AM (18 years ago)
- Location:
- GPL/branches/alsa-resync1/alsa-kernel/pci
- Files:
-
- 13 edited
-
als4000.c (modified) (1 diff)
-
cmipci.c (modified) (4 diffs)
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ice1712/aureon.c (modified) (3 diffs)
-
ice1712/delta.c (modified) (3 diffs)
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ice1712/ice1712.c (modified) (5 diffs)
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ice1712/ice1712.h (modified) (1 diff)
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ice1712/ice1724.c (modified) (7 diffs)
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korg1212/korg1212.c (modified) (1 diff)
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rme96.c (modified) (1 diff)
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rme9652/hdsp.c (modified) (104 diffs)
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rme9652/rme9652.c (modified) (2 diffs)
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sonicvibes.c (modified) (2 diffs)
-
ymfpci/ymfpci.c (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
-
GPL/branches/alsa-resync1/alsa-kernel/pci/als4000.c
r277 r281 654 654 /* disable all legacy ISA stuff except for joystick */ 655 655 #ifdef SUPPORT_JOYSTICK 656 if (joystick_port[dev] > 0 && 657 (acard->res_joystick = request_region(joystick_port[dev], 8, "ALS4000 gameport")) != NULL) 656 if (joystick_port[dev] == 1) { 657 /* auto-detect */ 658 long p; 659 for (p = 0x200; p <= 0x218; p += 8) { 660 if ((acard->res_joystick = request_region(p, 8, "ALS4000 gameport")) != NULL) { 661 joystick_port[dev] = p; 662 break; 663 } 664 } 665 } else if (joystick_port[dev] > 0) 666 acard->res_joystick = request_region(joystick_port[dev], 8, "ALS4000 gameport"); 667 if (acard->res_joystick) 658 668 joystick = joystick_port[dev]; 669 else 670 joystick = 0; 659 671 #endif 660 672 snd_als4000_set_addr(gcr, 0, 0, 0, joystick); -
GPL/branches/alsa-resync1/alsa-kernel/pci/cmipci.c
r277 r281 72 72 MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "l"); 73 73 MODULE_PARM_DESC(mpu_port, "MPU-401 port."); 74 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{ -1},{0x330},{0x320},{0x310},{0x300}},dialog:list");74 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x320},{0x310},{0x300}},dialog:list"); 75 75 MODULE_PARM(fm_port, "1-" __MODULE_STRING(SNDRV_CARDS) "l"); 76 76 MODULE_PARM_DESC(fm_port, "FM port."); 77 MODULE_PARM_SYNTAX(fm_port, SNDRV_ENABLED ",allows:{{ -1},{0x388},{0x3c8},{0x3e0},{0x3e8}},dialog:list");77 MODULE_PARM_SYNTAX(fm_port, SNDRV_ENABLED ",allows:{{0},{0x388},{0x3c8},{0x3e0},{0x3e8}},dialog:list"); 78 78 #ifdef DO_SOFT_AC3 79 79 MODULE_PARM(soft_ac3, "1-" __MODULE_STRING(SNDRV_CARDS) "l"); … … 82 82 #endif 83 83 #ifdef SUPPORT_JOYSTICK 84 MODULE_PARM(joystick , "1-" __MODULE_STRING(SNDRV_CARDS) "i");85 MODULE_PARM_DESC(joystick , "Enable joystick.");86 MODULE_PARM_SYNTAX(joystick , SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);84 MODULE_PARM(joystick_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i"); 85 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 86 MODULE_PARM_SYNTAX(joystick_port, SNDRV_ENABLED ",allows:{{0},{1},{0x200},{0x201}},dialog:list"); 87 87 #endif 88 88 … … 355 355 #define CM_EXTENT_MIDI 0x2 356 356 #define CM_EXTENT_SYNTH 0x4 357 358 /* fixed legacy joystick address */359 #define CM_JOYSTICK_ADDR 0x200360 357 361 358 … … 2984 2981 2985 2982 #ifdef SUPPORT_JOYSTICK 2986 if (joystick[dev] && 2987 (cm->res_joystick = request_region(CM_JOYSTICK_ADDR, 8, "CMIPCI gameport")) != NULL) { 2988 cm->gameport.io = CM_JOYSTICK_ADDR; 2983 if (joystick_port[dev] > 0) { 2984 if (joystick_port[dev] == 1) { /* auto-detect */ 2985 static int ports[] = { 0x200, 0x201, 0 }; 2986 int i; 2987 for (i = 0; ports[i]; i++) { 2988 joystick_port[dev] = ports[i]; 2989 cm->res_joystick = request_region(ports[i], 8, "CMIPCI gameport"); 2990 if (cm->res_joystick) 2991 break; 2992 } 2993 } else { 2994 cm->res_joystick = request_region(joystick_port[dev], 8, "CMIPCI gameport"); 2995 } 2996 } 2997 if (cm->res_joystick) { 2998 cm->gameport.io = joystick_port[dev]; 2989 2999 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2990 3000 gameport_register_port(&cm->gameport); 2991 } else 3001 } else { 3002 if (joystick_port[dev] > 0) 3003 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); 2992 3004 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 3005 } 2993 3006 #endif 2994 3007 *rcmipci = cm; -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/aureon.c
r262 r281 186 186 change = 0; 187 187 else 188 wm_put(ice, idx, nvol | 0x1 00);188 wm_put(ice, idx, nvol | 0x180); /* update on zero detect */ 189 189 } 190 190 snd_ice1712_restore_gpio_status(ice); … … 367 367 { 368 368 static unsigned short wm_inits[] = { 369 /* These come first to reduce init pop noise */ 370 0x1b, 0x000, /* ADC Mux */ 371 0x1c, 0x009, /* Out Mux1 */ 372 0x1d, 0x009, /* Out Mux2 */ 373 374 0x18, 0x000, /* All power-up */ 375 369 376 0x16, 0x122, /* I2S, normal polarity, 24bit */ 370 377 0x17, 0x022, /* 256fs, slave mode */ 371 0x18, 0x000, /* All power-up */372 378 0x00, 0, /* DAC1 analog mute */ 373 379 0x01, 0, /* DAC2 analog mute */ … … 394 400 0x19, 0x000, /* -12dB ADC/L */ 395 401 0x1a, 0x000, /* -12dB ADC/R */ 396 0x1b, 0x000, /* ADC Mux */397 0x1c, 0x009, /* Out Mux1 */398 0x1d, 0x009, /* Out Mux2 */399 402 }; 400 403 static unsigned short cs_inits[] = { -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/delta.c
r246 r281 258 258 259 259 /* 260 * change the DFS bit according rate for Delta1010 261 */ 262 static void delta_1010_set_rate_val(ice1712_t *ice, unsigned int rate) 263 { 264 unsigned char tmp, tmp2; 265 266 if (rate == 0) /* no hint - S/PDIF input is master, simply return */ 267 return; 268 269 down(&ice->gpio_mutex); 270 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); 271 tmp2 = tmp & ~ICE1712_DELTA_DFS; 272 if (rate > 48000) 273 tmp2 |= ICE1712_DELTA_DFS; 274 if (tmp != tmp2) 275 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp2); 276 up(&ice->gpio_mutex); 277 } 278 279 /* 260 280 * change the rate of AK4524 on Delta 44/66, AP, 1010LT 261 281 */ … … 272 292 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); 273 293 up(&ice->gpio_mutex); 274 tmp2 = tmp; 275 tmp2 &= ~ICE1712_DELTA_DFS; 294 tmp2 = tmp & ~ICE1712_DELTA_DFS; 276 295 if (rate > 48000) 277 296 tmp2 |= ICE1712_DELTA_DFS; … … 455 474 break; 456 475 case ICE1712_SUBDEVICE_DELTA1010: 476 ice->gpio.set_pro_rate = delta_1010_set_rate_val; 477 break; 457 478 case ICE1712_SUBDEVICE_DELTADIO2496: 479 ice->gpio.set_pro_rate = delta_1010_set_rate_val; 480 /* fall thru */ 458 481 case ICE1712_SUBDEVICE_DELTA66: 459 482 ice->spdif.ops.open = delta_open_spdif; -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ice1712.c
r277 r281 1048 1048 spin_unlock_irqrestore(&ice->reg_lock, flags); 1049 1049 1050 if (ice->gpio.set_pro_rate) 1051 ice->gpio.set_pro_rate(ice, rate); 1050 1052 for (i = 0; i < ice->akm_codecs; i++) { 1051 1053 if (ice->akm[i].ops.set_rate_val) … … 1451 1453 1452 1454 if (ice_has_con_ac97(ice)) { 1455 ac97_bus_t bus, *pbus; 1453 1456 ac97_t ac97; 1457 memset(&bus, 0, sizeof(bus)); 1458 bus.write = snd_ice1712_ac97_write; 1459 bus.read = snd_ice1712_ac97_read; 1460 if ((err = snd_ac97_bus(ice->card, &bus, &pbus)) < 0) 1461 return err; 1454 1462 memset(&ac97, 0, sizeof(ac97)); 1455 ac97.write = snd_ice1712_ac97_write;1456 ac97.read = snd_ice1712_ac97_read;1457 1463 ac97.private_data = ice; 1458 1464 ac97.private_free = snd_ice1712_mixer_free_ac97; 1459 if ((err = snd_ac97_mixer( ice->card, &ac97, &ice->ac97)) < 0)1465 if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0) 1460 1466 printk(KERN_WARNING "ice1712: cannot initialize ac97 for consumer, skipped\n"); 1461 1467 else { … … 1467 1473 1468 1474 if (! (ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) { 1475 ac97_bus_t bus, *pbus; 1469 1476 ac97_t ac97; 1477 memset(&bus, 0, sizeof(bus)); 1478 bus.write = snd_ice1712_pro_ac97_write; 1479 bus.read = snd_ice1712_pro_ac97_read; 1480 if ((err = snd_ac97_bus(ice->card, &bus, &pbus)) < 0) 1481 return err; 1470 1482 memset(&ac97, 0, sizeof(ac97)); 1471 ac97.write = snd_ice1712_pro_ac97_write;1472 ac97.read = snd_ice1712_pro_ac97_read;1473 1483 ac97.private_data = ice; 1474 1484 ac97.private_free = snd_ice1712_mixer_free_ac97; 1475 if ((err = snd_ac97_mixer( ice->card, &ac97, &ice->ac97)) < 0)1485 if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0) 1476 1486 printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n"); 1477 1487 else … … 1534 1544 1535 1545 if (! snd_card_proc_new(ice->card, "ice1712", &entry)) 1536 snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);1546 snd_info_set_text_ops(entry, ice, 1024, snd_ice1712_proc_read); 1537 1547 } 1538 1548 … … 2358 2368 return -ENXIO; 2359 2369 } 2360 pci_set_ dma_mask(pci, 0x0fffffff);2370 pci_set_consistent_dma_mask(pci, 0x0fffffff); 2361 2371 2362 2372 ice = snd_magic_kcalloc(ice1712_t, 0, GFP_KERNEL); -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ice1712.h
r260 r281 354 354 void (*set_data)(ice1712_t *ice, unsigned int data); 355 355 unsigned int (*get_data)(ice1712_t *ice); 356 /* misc operators - move to another place? */ 357 void (*set_pro_rate)(ice1712_t *ice, unsigned int rate); 356 358 } gpio; 357 359 struct semaphore gpio_mutex; -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ice1724.c
r262 r281 44 44 #include "revo.h" 45 45 #include "aureon.h" 46 #include "prodigy.h" 47 46 48 47 49 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); … … 53 55 AMP_AUDIO2000_DEVICE_DESC 54 56 AUREON_DEVICE_DESC 57 PRODIGY_DEVICE_DESC 55 58 "{VIA,VT1724}," 56 59 "{ICEnsemble,Generic ICE1724}," … … 909 912 910 913 if (! (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) { 914 ac97_bus_t bus, *pbus; 911 915 ac97_t ac97; 912 916 /* cold reset */ … … 915 919 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD)); 916 920 921 memset(&bus, 0, sizeof(bus)); 922 bus.write = snd_vt1724_ac97_write; 923 bus.read = snd_vt1724_ac97_read; 924 if ((err = snd_ac97_bus(ice->card, &bus, &pbus)) < 0) 925 return err; 917 926 memset(&ac97, 0, sizeof(ac97)); 918 ac97.write = snd_vt1724_ac97_write;919 ac97.read = snd_vt1724_ac97_read;920 927 ac97.private_data = ice; 921 if ((err = snd_ac97_mixer( ice->card, &ac97, &ice->ac97)) < 0)928 if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0) 922 929 printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n"); 923 930 else … … 976 983 977 984 if (! snd_card_proc_new(ice->card, "ice1724", &entry)) 978 snd_info_set_text_ops(entry, ice, snd_vt1724_proc_read);985 snd_info_set_text_ops(entry, ice, 1024, snd_vt1724_proc_read); 979 986 } 980 987 … … 1577 1584 snd_vt1724_amp_cards, 1578 1585 snd_vt1724_aureon_cards, 1586 snd_vt1724_prodigy_cards, 1579 1587 0, 1580 1588 }; … … 1794 1802 if ((err = pci_enable_device(pci)) < 0) 1795 1803 return err; 1796 pci_set_ dma_mask(pci, 0xffffffff);1804 pci_set_consistent_dma_mask(pci, 0xffffffff); 1797 1805 1798 1806 ice = snd_magic_kcalloc(ice1712_t, 0, GFP_KERNEL); -
GPL/branches/alsa-resync1/alsa-kernel/pci/korg1212/korg1212.c
r262 r281 2094 2094 2095 2095 if (! snd_card_proc_new(korg1212->card, "korg1212", &entry)) 2096 snd_info_set_text_ops(entry, korg1212, snd_korg1212_proc_read);2096 snd_info_set_text_ops(entry, korg1212, 1024, snd_korg1212_proc_read); 2097 2097 } 2098 2098 -
GPL/branches/alsa-resync1/alsa-kernel/pci/rme96.c
r277 r281 1931 1931 1932 1932 if (! snd_card_proc_new(rme96->card, "rme96", &entry)) 1933 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);1933 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read); 1934 1934 } 1935 1935 -
GPL/branches/alsa-resync1/alsa-kernel/pci/rme9652/hdsp.c
r262 r281 71 71 MODULE_CLASSES("{sound}"); 72 72 MODULE_DEVICES("{{RME Hammerfall-DSP}," 73 "{RME HDSP-9652}}"); 73 "{RME HDSP-9652}," 74 "{RME HDSP-9632}}"); 74 75 75 76 #define HDSP_MAX_CHANNELS 26 77 #define HDSP_MAX_DS_CHANNELS 14 78 #define HDSP_MAX_QS_CHANNELS 8 76 79 #define DIGIFACE_SS_CHANNELS 26 77 80 #define DIGIFACE_DS_CHANNELS 14 … … 80 83 #define H9652_SS_CHANNELS 26 81 84 #define H9652_DS_CHANNELS 14 85 /* This does not include possible Analog Extension Boards 86 AEBs are detected at card initialization 87 */ 88 #define H9632_SS_CHANNELS 12 89 #define H9632_DS_CHANNELS 8 90 #define H9632_QS_CHANNELS 4 82 91 83 92 /* Write registers. These are defined as byte-offsets from the iobase value. … … 123 132 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 124 133 125 #define HDSP_IO_EXTENT 5192 134 135 /* This is for H9652 cards 136 Peak values are read downward from the base 137 Rms values are read upward 138 There are rms values for the outputs too 139 26*3 values are read in ss mode 140 14*3 in ds mode, with no gap between values 141 */ 142 #define HDSP_9652_peakBase 7164 143 #define HDSP_9652_rmsBase 4096 144 145 /* c.f. the hdsp_9632_meters_t struct */ 146 #define HDSP_9632_metersBase 4096 147 148 #define HDSP_IO_EXTENT 7168 126 149 127 150 /* control2 register bits */ … … 139 162 #define HDSP_RD_MULTIPLE 0x400 140 163 #define HDSP_9652_ENABLE_MIXER 0x800 164 #define HDSP_TDO 0x10000000 141 165 142 166 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) … … 148 172 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 149 173 #define HDSP_Latency1 (1<<2) /* [ see above ] */ 150 #define HDSP_Latency2 (1<<3) /* ]see above ] */174 #define HDSP_Latency2 (1<<3) /* [ see above ] */ 151 175 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 152 176 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 153 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */154 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz */177 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ 178 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ 155 179 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 156 180 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ … … 162 186 #define HDSP_SPDIFInputSelect1 (1<<15) 163 187 #define HDSP_SyncRef0 (1<<16) 164 #define HDSP_SyncRef1 (1<<17) 188 #define HDSP_SyncRef1 (1<<17) 189 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 190 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ 165 191 #define HDSP_Midi0InterruptEnable (1<<22) 166 192 #define HDSP_Midi1InterruptEnable (1<<23) 167 193 #define HDSP_LineOut (1<<24) 194 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ 195 #define HDSP_ADGain1 (1<<26) 196 #define HDSP_DAGain0 (1<<27) 197 #define HDSP_DAGain1 (1<<28) 198 #define HDSP_PhoneGain0 (1<<29) 199 #define HDSP_PhoneGain1 (1<<30) 200 #define HDSP_QuadSpeed (1<<31) 201 202 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) 203 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask 204 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 205 #define HDSP_ADGainLowGain 0 206 207 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) 208 #define HDSP_DAGainHighGain HDSP_DAGainMask 209 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 210 #define HDSP_DAGainMinus10dBV 0 211 212 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 213 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 214 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 215 #define HDSP_PhoneGainMinus12dB 0 168 216 169 217 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) 170 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed )218 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) 171 219 172 220 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 173 221 #define HDSP_SPDIFInputADAT1 0 174 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect1) 175 #define HDSP_SPDIFInputCDROM (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 222 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) 223 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) 224 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 176 225 177 226 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) 178 #define HDSP_SyncRef_ADAT1 0227 #define HDSP_SyncRef_ADAT1 0 179 228 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) 180 229 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) … … 185 234 /* Sample Clock Sources */ 186 235 187 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 188 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 189 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 190 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 191 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 192 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 193 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 236 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 237 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 238 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 239 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 240 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 241 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 242 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 243 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 244 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 245 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 194 246 195 247 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 196 248 197 249 #define HDSP_SYNC_FROM_WORD 0 198 #define HDSP_SYNC_FROM_ ADAT_SYNC1199 #define HDSP_SYNC_FROM_ SPDIF2200 #define HDSP_SYNC_FROM_ADAT 13250 #define HDSP_SYNC_FROM_SPDIF 1 251 #define HDSP_SYNC_FROM_ADAT1 2 252 #define HDSP_SYNC_FROM_ADAT_SYNC 3 201 253 #define HDSP_SYNC_FROM_ADAT2 4 202 254 #define HDSP_SYNC_FROM_ADAT3 5 … … 220 272 /* Possible sources of S/PDIF input */ 221 273 222 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 223 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 224 #define HDSP_SPDIFIN_INTERN 2 /* internal (CDROM) */ 274 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 275 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 276 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ 277 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ 225 278 226 279 #define HDSP_Frequency32KHz HDSP_Frequency0 227 280 #define HDSP_Frequency44_1KHz HDSP_Frequency1 228 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 229 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 230 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 231 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 281 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 282 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 283 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 284 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 285 /* For H9632 cards */ 286 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) 287 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) 288 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 232 289 233 290 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) … … 240 297 241 298 #define HDSP_audioIRQPending (1<<0) 242 #define HDSP_Lock2 (1<<1) 299 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ 300 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ 243 301 #define HDSP_Lock1 (1<<2) 244 302 #define HDSP_Lock0 (1<<3) … … 258 316 #define HDSP_BufferID (1<<26) 259 317 #define HDSP_TimecodeSync (1<<27) 260 #define HDSP_CIN (1<<28) 261 #define HDSP_midi0IRQPending (1<<30) /* notice the gap at bit 29 */ 318 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ 319 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ 320 #define HDSP_midi0IRQPending (1<<30) 262 321 #define HDSP_midi1IRQPending (1<<31) 263 322 … … 271 330 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 272 331 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 332 333 /* This is for H9632 cards */ 334 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask 335 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 336 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) 273 337 274 338 /* Status2 Register bits */ … … 295 359 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) 296 360 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) 361 /* FIXME : more values for 9632 cards ? */ 297 362 298 363 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) … … 342 407 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 343 408 344 typedef struct _hdsp hdsp_t; 345 typedef struct _hdsp_midi hdsp_midi_t; 409 typedef struct _hdsp hdsp_t; 410 typedef struct _hdsp_midi hdsp_midi_t; 411 typedef struct _hdsp_9632_meters hdsp_9632_meters_t; 412 413 struct _hdsp_9632_meters { 414 u32 input_peak[16]; 415 u32 playback_peak[16]; 416 u32 output_peak[16]; 417 u32 xxx_peak[16]; 418 u32 padding[64]; 419 u32 input_rms_low[16]; 420 u32 playback_rms_low[16]; 421 u32 output_rms_low[16]; 422 u32 xxx_rms_low[16]; 423 u32 input_rms_high[16]; 424 u32 playback_rms_high[16]; 425 u32 output_rms_high[16]; 426 u32 xxx_rms_high[16]; 427 }; 346 428 347 429 struct _hdsp_midi { … … 374 456 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ 375 457 size_t period_bytes; /* guess what this is */ 376 unsigned char ds_channels; 377 unsigned char ss_channels; /* different for multiface/digiface */ 458 unsigned char max_channels; 459 unsigned char qs_in_channels; /* quad speed mode for H9632 */ 460 unsigned char ds_in_channels; 461 unsigned char ss_in_channels; /* different for multiface/digiface */ 462 unsigned char qs_out_channels; 463 unsigned char ds_out_channels; 464 unsigned char ss_out_channels; 378 465 void *capture_buffer_unaligned; /* original buffer addresses */ 379 466 void *playback_buffer_unaligned; /* original buffer addresses */ … … 386 473 int running; 387 474 int passthru; /* non-zero if doing pass-thru */ 388 int last_spdif_sample_rate;/* for information reporting */389 int last_external_sample_rate;390 int last_internal_sample_rate;391 475 int system_sample_rate; 392 476 char *channel_map; … … 401 485 struct pci_dev *pci; 402 486 snd_kcontrol_t *spdif_ctl; 403 snd_kcontrol_t *playback_mixer_ctls[HDSP_MAX_CHANNELS];404 487 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 405 488 }; … … 425 508 /* SPDIF */ 426 509 24, 25, 427 -1, -1, -1, -1, -1, -1, -1, -1 ,510 -1, -1, -1, -1, -1, -1, -1, -1 428 511 }; 429 512 … … 434 517 24, 25, 435 518 /* others don't exist */ 436 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 519 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 520 }; 521 522 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { 523 /* ADAT channels */ 524 0, 1, 2, 3, 4, 5, 6, 7, 525 /* SPDIF */ 526 8, 9, 527 /* Analog */ 528 10, 11, 529 /* AO4S-192 and AI4S-192 extension boards */ 530 12, 13, 14, 15, 531 /* others don't exist */ 532 -1, -1, -1, -1, -1, -1, -1, -1, 533 -1, -1 534 }; 535 536 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { 537 /* ADAT */ 538 1, 3, 5, 7, 539 /* SPDIF */ 540 8, 9, 541 /* Analog */ 542 10, 11, 543 /* AO4S-192 and AI4S-192 extension boards */ 544 12, 13, 14, 15, 545 /* others don't exist */ 546 -1, -1, -1, -1, -1, -1, -1, -1, 547 -1, -1, -1, -1, -1, -1 548 }; 549 550 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { 551 /* ADAT is disabled in this mode */ 552 /* SPDIF */ 553 8, 9, 554 /* Analog */ 555 10, 11, 556 /* AO4S-192 and AI4S-192 extension boards */ 557 12, 13, 14, 15, 558 /* others don't exist */ 559 -1, -1, -1, -1, -1, -1, -1, -1, 560 -1, -1, -1, -1, -1, -1, -1, -1, 561 -1, -1 437 562 }; 438 563 … … 494 619 static inline void snd_hdsp_initialize_channels (hdsp_t *hdsp); 495 620 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout); 496 static int hdsp_update_simple_mixer_controls(hdsp_t *hdsp);497 621 static int hdsp_autosync_ref(hdsp_t *hdsp); 498 622 static int snd_hdsp_set_defaults(hdsp_t *hdsp); 623 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp); 499 624 500 625 static inline int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out) … … 503 628 case 0xa: 504 629 return (64 * out) + (32 + (in)); 630 case 0x96: 631 return (32 * out) + (16 + (in)); 505 632 default: 506 633 return (52 * out) + (26 + (in)); … … 513 640 case 0xa: 514 641 return (64 * out) + in; 642 case 0x96: 643 return (32 * out) + in; 515 644 default: 516 645 return (52 * out) + in; … … 531 660 { 532 661 533 if (hdsp->io_type == H9652 ) return 0;662 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 534 663 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { 535 664 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); … … 567 696 } 568 697 } 698 699 if ((1000 / HZ) < 3000) { 700 set_current_state(TASK_UNINTERRUPTIBLE); 701 schedule_timeout((3000 * HZ + 999) / 1000); 702 } else { 703 mdelay(3000); 704 } 569 705 570 706 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { … … 581 717 snd_printk ("finished firmware loading\n"); 582 718 583 if ((1000 / HZ) < 3000) {584 set_current_state(TASK_UNINTERRUPTIBLE);585 schedule_timeout((3000 * HZ + 999) / 1000);586 } else {587 mdelay(3000);588 }589 719 } 590 720 if (hdsp->state & HDSP_InitializationComplete) { … … 645 775 static inline int hdsp_check_for_firmware (hdsp_t *hdsp) 646 776 { 647 if (hdsp->io_type == H9652 ) return 0;777 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 648 778 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 649 779 snd_printk("firmware not present.\n"); … … 694 824 if (addr >= HDSP_MATRIX_MIXER_SIZE) 695 825 return -1; 696 697 if (hdsp->io_type == H9652 ) {826 827 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { 698 828 699 829 /* from martin björnsen: … … 709 839 */ 710 840 841 if (hdsp->io_type == H9632 && addr >= 512) { 842 return 0; 843 } 844 845 if (hdsp->io_type == H9652 && addr >= 1352) { 846 return 0; 847 } 848 711 849 hdsp->mixer_matrix[addr] = data; 712 850 851 713 852 /* `addr' addresses a 16-bit wide address, but 714 853 the address space accessed via hdsp_write … … 718 857 to access 0 to 2703 ... 719 858 */ 720 721 hdsp_write (hdsp, 4096 + (addr*2), 859 ad = addr/2; 860 861 hdsp_write (hdsp, 4096 + (ad*4), 722 862 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 723 863 hdsp->mixer_matrix[addr&0x7fe]); … … 788 928 case HDSP_spdifFrequency88_2KHz: return 88200; 789 929 case HDSP_spdifFrequency96KHz: return 96000; 930 case HDSP_spdifFrequency128KHz: 931 if (hdsp->io_type == H9632) return 128000; 932 break; 933 case HDSP_spdifFrequency176_4KHz: 934 if (hdsp->io_type == H9632) return 176400; 935 break; 936 case HDSP_spdifFrequency192KHz: 937 if (hdsp->io_type == H9632) return 192000; 938 break; 790 939 default: 791 snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); 792 return 0; 793 } 940 break; 941 } 942 snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); 943 return 0; 794 944 } 795 945 … … 869 1019 int rate_bits; 870 1020 871 /* ASSUMPTION: hdsp->lock is either hel p, or1021 /* ASSUMPTION: hdsp->lock is either held, or 872 1022 there is no need for it (e.g. during module 873 1023 initialization). … … 886 1036 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) { 887 1037 snd_printk("Detected ADAT in double speed mode\n"); 1038 } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) { 1039 snd_printk("Detected ADAT in quad speed mode\n"); 888 1040 } else if (rate != external_freq) { 889 1041 snd_printk("No AutoSync source for requested rate\n"); … … 905 1057 is to flag rate changes in the read/write routines. */ 906 1058 1059 if (rate > 96000 && hdsp->io_type != H9632) { 1060 return -EINVAL; 1061 } 1062 907 1063 switch (rate) { 908 1064 case 32000: … … 925 1081 break; 926 1082 case 64000: 927 if (current_rate <= 48000 ) {1083 if (current_rate <= 48000 || current_rate > 96000) { 928 1084 reject_if_open = 1; 929 1085 } … … 931 1087 break; 932 1088 case 88200: 933 if (current_rate <= 48000 ) {1089 if (current_rate <= 48000 || current_rate > 96000) { 934 1090 reject_if_open = 1; 935 1091 } … … 937 1093 break; 938 1094 case 96000: 939 if (current_rate <= 48000 ) {1095 if (current_rate <= 48000 || current_rate > 96000) { 940 1096 reject_if_open = 1; 941 1097 } 942 1098 rate_bits = HDSP_Frequency96KHz; 1099 break; 1100 case 128000: 1101 if (current_rate < 128000) { 1102 reject_if_open = 1; 1103 } 1104 rate_bits = HDSP_Frequency128KHz; 1105 break; 1106 case 176400: 1107 if (current_rate < 128000) { 1108 reject_if_open = 1; 1109 } 1110 rate_bits = HDSP_Frequency176_4KHz; 1111 break; 1112 case 192000: 1113 if (current_rate < 128000) { 1114 reject_if_open = 1; 1115 } 1116 rate_bits = HDSP_Frequency192KHz; 943 1117 break; 944 1118 default: … … 947 1121 948 1122 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { 949 snd_printk ("cannot change between single- and double-speed mode (capture PID = %d, playback PID = %d)\n",1123 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n", 950 1124 hdsp->capture_pid, 951 1125 hdsp->playback_pid); … … 957 1131 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 958 1132 959 if (rate > 48000) { 960 hdsp->channel_map = channel_map_ds; 1133 if (rate >= 128000) { 1134 hdsp->channel_map = channel_map_H9632_qs; 1135 } else if (rate > 48000) { 1136 if (hdsp->io_type == H9632) { 1137 hdsp->channel_map = channel_map_H9632_ds; 1138 } else { 1139 hdsp->channel_map = channel_map_ds; 1140 } 961 1141 } else { 962 1142 switch (hdsp->io_type) { … … 968 1148 hdsp->channel_map = channel_map_df_ss; 969 1149 break; 1150 case H9632: 1151 hdsp->channel_map = channel_map_H9632_ss; 1152 break; 970 1153 default: 971 1154 /* should never happen */ … … 975 1158 976 1159 hdsp->system_sample_rate = rate; 977 978 if (reject_if_open) {979 hdsp_update_simple_mixer_controls (hdsp);980 }981 1160 982 1161 return 0; … … 995 1174 996 1175 if (enable) { 997 for (i = 0; i < 26; i++) {1176 for (i = 0; i < hdsp->max_channels; i++) { 998 1177 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN); 999 1178 } 1000 1179 } else { 1001 for (i = 0; i < 26; i++) {1180 for (i = 0; i < hdsp->max_channels; i++) { 1002 1181 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN); 1003 1182 } … … 1007 1186 int mapped_channel; 1008 1187 1009 snd_assert(channel < HDSP_MAX_CHANNELS, return);1188 snd_assert(channel < hdsp->max_channels, return); 1010 1189 1011 1190 mapped_channel = hdsp->channel_map[channel]; … … 1465 1644 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1466 1645 { 1467 static char *texts[3] = {"ADAT1", "Coaxial", "Internal"}; 1646 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; 1647 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1468 1648 1469 1649 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1470 1650 uinfo->count = 1; 1471 uinfo->value.enumerated.items = 3;1472 if (uinfo->value.enumerated.item > 2)1473 uinfo->value.enumerated.item = 2;1651 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); 1652 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) 1653 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); 1474 1654 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1475 1655 return 0; … … 1493 1673 if (!snd_hdsp_use_is_exclusive(hdsp)) 1494 1674 return -EBUSY; 1495 val = ucontrol->value.enumerated.item[0] % 3;1675 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); 1496 1676 spin_lock_irqsave(&hdsp->lock, flags); 1497 1677 change = val != hdsp_spdif_in(hdsp); … … 1706 1886 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1707 1887 { 1708 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None"}; 1888 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1889 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1890 1709 1891 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1710 1892 uinfo->count = 1; 1711 uinfo->value.enumerated.items = 7;1893 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; 1712 1894 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1713 1895 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; … … 1738 1920 case 96000: 1739 1921 ucontrol->value.enumerated.item[0] = 5; 1922 break; 1923 case 128000: 1924 ucontrol->value.enumerated.item[0] = 7; 1925 break; 1926 case 176400: 1927 ucontrol->value.enumerated.item[0] = 8; 1928 break; 1929 case 192000: 1930 ucontrol->value.enumerated.item[0] = 9; 1740 1931 break; 1741 1932 default: … … 1780 1971 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1781 1972 { 1782 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None"}; 1973 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1974 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1783 1975 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1784 1976 uinfo->count = 1; 1785 uinfo->value.enumerated.items = 7 ;1977 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; 1786 1978 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1787 1979 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; … … 1813 2005 ucontrol->value.enumerated.item[0] = 5; 1814 2006 break; 2007 case 128000: 2008 ucontrol->value.enumerated.item[0] = 7; 2009 break; 2010 case 176400: 2011 ucontrol->value.enumerated.item[0] = 8; 2012 break; 2013 case 192000: 2014 ucontrol->value.enumerated.item[0] = 9; 2015 break; 1815 2016 default: 1816 2017 ucontrol->value.enumerated.item[0] = 6; … … 1884 2085 case 96000: 1885 2086 return 6; 2087 case 128000: 2088 return 7; 2089 case 176400: 2090 return 8; 2091 case 192000: 2092 return 9; 1886 2093 default: 1887 2094 return 3; … … 1898 2105 case HDSP_CLOCK_SOURCE_AUTOSYNC: 1899 2106 if (hdsp_external_sample_rate(hdsp) != 0) { 1900 hdsp->control_register &= ~HDSP_ClockModeMaster; 1901 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1902 return 0; 2107 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { 2108 hdsp->control_register &= ~HDSP_ClockModeMaster; 2109 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2110 return 0; 2111 } 1903 2112 } 1904 2113 return -1; … … 1921 2130 rate = 96000; 1922 2131 break; 2132 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 2133 rate = 128000; 2134 break; 2135 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 2136 rate = 176400; 2137 break; 2138 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 2139 rate = 192000; 2140 break; 1923 2141 default: 1924 2142 rate = 48000; … … 1932 2150 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1933 2151 { 1934 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz" }; 2152 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; 2153 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1935 2154 1936 2155 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1937 2156 uinfo->count = 1; 1938 uinfo->value.enumerated.items = 7; 2157 if (hdsp->io_type == H9632) 2158 uinfo->value.enumerated.items = 10; 2159 else 2160 uinfo->value.enumerated.items = 7; 1939 2161 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1940 2162 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; … … 1962 2184 val = ucontrol->value.enumerated.item[0]; 1963 2185 if (val < 0) val = 0; 1964 if (val > 6) val = 6; 2186 if (hdsp->io_type == H9632) { 2187 if (val > 9) val = 9; 2188 } else { 2189 if (val > 6) val = 6; 2190 } 1965 2191 spin_lock_irqsave(&hdsp->lock, flags); 1966 2192 if (val != hdsp_clock_source(hdsp)) { … … 1969 2195 change = 0; 1970 2196 } 2197 spin_unlock_irqrestore(&hdsp->lock, flags); 2198 return change; 2199 } 2200 2201 #define HDSP_DA_GAIN(xname, xindex) \ 2202 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2203 .name = xname, \ 2204 .index = xindex, \ 2205 .info = snd_hdsp_info_da_gain, \ 2206 .get = snd_hdsp_get_da_gain, \ 2207 .put = snd_hdsp_put_da_gain \ 2208 } 2209 2210 static int hdsp_da_gain(hdsp_t *hdsp) 2211 { 2212 switch (hdsp->control_register & HDSP_DAGainMask) { 2213 case HDSP_DAGainHighGain: 2214 return 0; 2215 case HDSP_DAGainPlus4dBu: 2216 return 1; 2217 case HDSP_DAGainMinus10dBV: 2218 return 2; 2219 default: 2220 return 1; 2221 } 2222 } 2223 2224 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode) 2225 { 2226 hdsp->control_register &= ~HDSP_DAGainMask; 2227 switch (mode) { 2228 case 0: 2229 hdsp->control_register |= HDSP_DAGainHighGain; 2230 break; 2231 case 1: 2232 hdsp->control_register |= HDSP_DAGainPlus4dBu; 2233 break; 2234 case 2: 2235 hdsp->control_register |= HDSP_DAGainMinus10dBV; 2236 break; 2237 default: 2238 return -1; 2239 2240 } 2241 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2242 return 0; 2243 } 2244 2245 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2246 { 2247 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; 2248 2249 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2250 uinfo->count = 1; 2251 uinfo->value.enumerated.items = 3; 2252 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2253 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2254 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2255 return 0; 2256 } 2257 2258 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2259 { 2260 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2261 2262 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); 2263 return 0; 2264 } 2265 2266 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2267 { 2268 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2269 unsigned long flags; 2270 int change; 2271 int val; 2272 2273 if (!snd_hdsp_use_is_exclusive(hdsp)) 2274 return -EBUSY; 2275 val = ucontrol->value.enumerated.item[0]; 2276 if (val < 0) val = 0; 2277 if (val > 2) val = 2; 2278 spin_lock_irqsave(&hdsp->lock, flags); 2279 if (val != hdsp_da_gain(hdsp)) { 2280 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; 2281 } else { 2282 change = 0; 2283 } 2284 spin_unlock_irqrestore(&hdsp->lock, flags); 2285 return change; 2286 } 2287 2288 #define HDSP_AD_GAIN(xname, xindex) \ 2289 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2290 .name = xname, \ 2291 .index = xindex, \ 2292 .info = snd_hdsp_info_ad_gain, \ 2293 .get = snd_hdsp_get_ad_gain, \ 2294 .put = snd_hdsp_put_ad_gain \ 2295 } 2296 2297 static int hdsp_ad_gain(hdsp_t *hdsp) 2298 { 2299 switch (hdsp->control_register & HDSP_ADGainMask) { 2300 case HDSP_ADGainMinus10dBV: 2301 return 0; 2302 case HDSP_ADGainPlus4dBu: 2303 return 1; 2304 case HDSP_ADGainLowGain: 2305 return 2; 2306 default: 2307 return 1; 2308 } 2309 } 2310 2311 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode) 2312 { 2313 hdsp->control_register &= ~HDSP_ADGainMask; 2314 switch (mode) { 2315 case 0: 2316 hdsp->control_register |= HDSP_ADGainMinus10dBV; 2317 break; 2318 case 1: 2319 hdsp->control_register |= HDSP_ADGainPlus4dBu; 2320 break; 2321 case 2: 2322 hdsp->control_register |= HDSP_ADGainLowGain; 2323 break; 2324 default: 2325 return -1; 2326 2327 } 2328 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2329 return 0; 2330 } 2331 2332 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2333 { 2334 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; 2335 2336 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2337 uinfo->count = 1; 2338 uinfo->value.enumerated.items = 3; 2339 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2340 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2341 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2342 return 0; 2343 } 2344 2345 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2346 { 2347 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2348 2349 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); 2350 return 0; 2351 } 2352 2353 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2354 { 2355 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2356 unsigned long flags; 2357 int change; 2358 int val; 2359 2360 if (!snd_hdsp_use_is_exclusive(hdsp)) 2361 return -EBUSY; 2362 val = ucontrol->value.enumerated.item[0]; 2363 if (val < 0) val = 0; 2364 if (val > 2) val = 2; 2365 spin_lock_irqsave(&hdsp->lock, flags); 2366 if (val != hdsp_ad_gain(hdsp)) { 2367 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; 2368 } else { 2369 change = 0; 2370 } 2371 spin_unlock_irqrestore(&hdsp->lock, flags); 2372 return change; 2373 } 2374 2375 #define HDSP_PHONE_GAIN(xname, xindex) \ 2376 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2377 .name = xname, \ 2378 .index = xindex, \ 2379 .info = snd_hdsp_info_phone_gain, \ 2380 .get = snd_hdsp_get_phone_gain, \ 2381 .put = snd_hdsp_put_phone_gain \ 2382 } 2383 2384 static int hdsp_phone_gain(hdsp_t *hdsp) 2385 { 2386 switch (hdsp->control_register & HDSP_PhoneGainMask) { 2387 case HDSP_PhoneGain0dB: 2388 return 0; 2389 case HDSP_PhoneGainMinus6dB: 2390 return 1; 2391 case HDSP_PhoneGainMinus12dB: 2392 return 2; 2393 default: 2394 return 0; 2395 } 2396 } 2397 2398 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode) 2399 { 2400 hdsp->control_register &= ~HDSP_PhoneGainMask; 2401 switch (mode) { 2402 case 0: 2403 hdsp->control_register |= HDSP_PhoneGain0dB; 2404 break; 2405 case 1: 2406 hdsp->control_register |= HDSP_PhoneGainMinus6dB; 2407 break; 2408 case 2: 2409 hdsp->control_register |= HDSP_PhoneGainMinus12dB; 2410 break; 2411 default: 2412 return -1; 2413 2414 } 2415 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2416 return 0; 2417 } 2418 2419 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2420 { 2421 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; 2422 2423 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2424 uinfo->count = 1; 2425 uinfo->value.enumerated.items = 3; 2426 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2427 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2428 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2429 return 0; 2430 } 2431 2432 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2433 { 2434 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2435 2436 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); 2437 return 0; 2438 } 2439 2440 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2441 { 2442 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2443 unsigned long flags; 2444 int change; 2445 int val; 2446 2447 if (!snd_hdsp_use_is_exclusive(hdsp)) 2448 return -EBUSY; 2449 val = ucontrol->value.enumerated.item[0]; 2450 if (val < 0) val = 0; 2451 if (val > 2) val = 2; 2452 spin_lock_irqsave(&hdsp->lock, flags); 2453 if (val != hdsp_phone_gain(hdsp)) { 2454 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; 2455 } else { 2456 change = 0; 2457 } 2458 spin_unlock_irqrestore(&hdsp->lock, flags); 2459 return change; 2460 } 2461 2462 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ 2463 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2464 .name = xname, \ 2465 .index = xindex, \ 2466 .info = snd_hdsp_info_xlr_breakout_cable, \ 2467 .get = snd_hdsp_get_xlr_breakout_cable, \ 2468 .put = snd_hdsp_put_xlr_breakout_cable \ 2469 } 2470 2471 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp) 2472 { 2473 if (hdsp->control_register & HDSP_XLRBreakoutCable) { 2474 return 1; 2475 } 2476 return 0; 2477 } 2478 2479 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode) 2480 { 2481 if (mode) { 2482 hdsp->control_register |= HDSP_XLRBreakoutCable; 2483 } else { 2484 hdsp->control_register &= ~HDSP_XLRBreakoutCable; 2485 } 2486 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2487 return 0; 2488 } 2489 2490 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2491 { 2492 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2493 uinfo->count = 1; 2494 uinfo->value.integer.min = 0; 2495 uinfo->value.integer.max = 1; 2496 return 0; 2497 } 2498 2499 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2500 { 2501 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2502 2503 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); 2504 return 0; 2505 } 2506 2507 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2508 { 2509 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2510 unsigned long flags; 2511 int change; 2512 int val; 2513 2514 if (!snd_hdsp_use_is_exclusive(hdsp)) 2515 return -EBUSY; 2516 val = ucontrol->value.integer.value[0] & 1; 2517 spin_lock_irqsave(&hdsp->lock, flags); 2518 change = (int)val != hdsp_xlr_breakout_cable(hdsp); 2519 hdsp_set_xlr_breakout_cable(hdsp, val); 2520 spin_unlock_irqrestore(&hdsp->lock, flags); 2521 return change; 2522 } 2523 2524 /* (De)activates old RME Analog Extension Board 2525 These are connected to the internal ADAT connector 2526 Switching this on desactivates external ADAT 2527 */ 2528 #define HDSP_AEB(xname, xindex) \ 2529 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2530 .name = xname, \ 2531 .index = xindex, \ 2532 .info = snd_hdsp_info_aeb, \ 2533 .get = snd_hdsp_get_aeb, \ 2534 .put = snd_hdsp_put_aeb \ 2535 } 2536 2537 static int hdsp_aeb(hdsp_t *hdsp) 2538 { 2539 if (hdsp->control_register & HDSP_AnalogExtensionBoard) { 2540 return 1; 2541 } 2542 return 0; 2543 } 2544 2545 static int hdsp_set_aeb(hdsp_t *hdsp, int mode) 2546 { 2547 if (mode) { 2548 hdsp->control_register |= HDSP_AnalogExtensionBoard; 2549 } else { 2550 hdsp->control_register &= ~HDSP_AnalogExtensionBoard; 2551 } 2552 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2553 return 0; 2554 } 2555 2556 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2557 { 2558 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2559 uinfo->count = 1; 2560 uinfo->value.integer.min = 0; 2561 uinfo->value.integer.max = 1; 2562 return 0; 2563 } 2564 2565 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2566 { 2567 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2568 2569 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); 2570 return 0; 2571 } 2572 2573 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2574 { 2575 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2576 unsigned long flags; 2577 int change; 2578 int val; 2579 2580 if (!snd_hdsp_use_is_exclusive(hdsp)) 2581 return -EBUSY; 2582 val = ucontrol->value.integer.value[0] & 1; 2583 spin_lock_irqsave(&hdsp->lock, flags); 2584 change = (int)val != hdsp_aeb(hdsp); 2585 hdsp_set_aeb(hdsp, val); 1971 2586 spin_unlock_irqrestore(&hdsp->lock, flags); 1972 2587 return change; … … 2038 2653 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2039 2654 { 2040 static char *texts[] = {"Word", " ADAT Sync", "IEC958", "ADAT1", "ADAT2", "ADAT3" };2655 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; 2041 2656 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2042 2657 … … 2051 2666 case Multiface: 2052 2667 uinfo->value.enumerated.items = 4; 2668 break; 2669 case H9632: 2670 uinfo->value.enumerated.items = 3; 2671 break; 2053 2672 default: 2054 2673 uinfo->value.enumerated.items = 0; … … 2087 2706 case Multiface: 2088 2707 max = 4; 2708 break; 2709 case H9632: 2710 max = 3; 2089 2711 break; 2090 2712 default: … … 2298 2920 source = ucontrol->value.integer.value[0]; 2299 2921 destination = ucontrol->value.integer.value[1]; 2300 2301 if (source > 25) {2302 addr = hdsp_playback_to_output_key(hdsp,source- 26,destination);2922 2923 if (source >= hdsp->max_channels) { 2924 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); 2303 2925 } else { 2304 2926 addr = hdsp_input_to_output_key(hdsp,source, destination); … … 2327 2949 destination = ucontrol->value.integer.value[1]; 2328 2950 2329 if (source > 25) {2330 addr = hdsp_playback_to_output_key(hdsp,source- 26, destination);2951 if (source >= hdsp->max_channels) { 2952 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); 2331 2953 } else { 2332 2954 addr = hdsp_input_to_output_key(hdsp,source, destination); … … 2334 2956 2335 2957 gain = ucontrol->value.integer.value[2]; 2336 2337 spin_lock_irqsave(&hdsp->lock, flags);2338 change = gain != hdsp_read_gain(hdsp, addr);2339 if (change)2340 hdsp_write_gain(hdsp, addr, gain);2341 spin_unlock_irqrestore(&hdsp->lock, flags);2342 return change;2343 }2344 2345 /* The simple mixer control(s) provide gain control for the2346 basic 1:1 mappings of playback streams to output2347 streams.2348 */2349 2350 #define HDSP_PLAYBACK_MIXER \2351 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2352 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \2353 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \2354 .info = snd_hdsp_info_playback_mixer, \2355 .get = snd_hdsp_get_playback_mixer, \2356 .put = snd_hdsp_put_playback_mixer \2357 }2358 2359 static int snd_hdsp_info_playback_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)2360 {2361 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;2362 uinfo->count = 1;2363 uinfo->value.integer.min = 0;2364 uinfo->value.integer.max = 65536;2365 uinfo->value.integer.step = 1;2366 return 0;2367 }2368 2369 static int snd_hdsp_get_playback_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)2370 {2371 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);2372 unsigned long flags;2373 int addr;2374 int channel;2375 int mapped_channel;2376 2377 channel = ucontrol->id.index - 1;2378 2379 snd_assert(channel >= 0 || channel < HDSP_MAX_CHANNELS, return -EINVAL);2380 2381 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {2382 return -EINVAL;2383 }2384 2385 addr = hdsp_playback_to_output_key(hdsp,mapped_channel, mapped_channel);2386 2387 spin_lock_irqsave(&hdsp->lock, flags);2388 ucontrol->value.integer.value[0] = hdsp_read_gain (hdsp, addr);2389 spin_unlock_irqrestore(&hdsp->lock, flags);2390 return 0;2391 }2392 2393 static int snd_hdsp_put_playback_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)2394 {2395 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);2396 unsigned long flags;2397 int change;2398 int addr;2399 int channel;2400 int mapped_channel;2401 int gain;2402 2403 if (!snd_hdsp_use_is_exclusive(hdsp))2404 return -EBUSY;2405 2406 channel = ucontrol->id.index - 1;2407 2408 snd_assert(channel >= 0 || channel < HDSP_MAX_CHANNELS, return -EINVAL);2409 2410 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {2411 return -EINVAL;2412 }2413 2414 addr = hdsp_playback_to_output_key(hdsp,mapped_channel, mapped_channel);2415 gain = ucontrol->value.integer.value[0];2416 2417 2958 2418 2959 spin_lock_irqsave(&hdsp->lock, flags); … … 2568 3109 break; 2569 3110 case Multiface: 3111 case H9632: 2570 3112 if (offset >= 1) 2571 3113 return -EINVAL; … … 2578 3120 return 0; 2579 3121 } 3122 3123 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = { 3124 HDSP_DA_GAIN("DA Gain", 0), 3125 HDSP_AD_GAIN("AD Gain", 0), 3126 HDSP_PHONE_GAIN("Phones Gain", 0), 3127 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0) 3128 }; 2580 3129 2581 3130 static snd_kcontrol_new_t snd_hdsp_controls[] = { … … 2639 3188 #define HDSP_CONTROLS (sizeof(snd_hdsp_controls)/sizeof(snd_kcontrol_new_t)) 2640 3189 2641 static snd_kcontrol_new_t snd_hdsp_playback_mixer = HDSP_PLAYBACK_MIXER; 3190 #define HDSP_9632_CONTROLS (sizeof(snd_hdsp_9632_controls)/sizeof(snd_kcontrol_new_t)) 3191 3192 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); 2642 3193 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 2643 3194 2644 2645 static int hdsp_update_simple_mixer_controls(hdsp_t *hdsp)2646 {2647 int i;2648 2649 for (i = hdsp->ds_channels; i < hdsp->ss_channels; ++i) {2650 if (hdsp->system_sample_rate > 48000) {2651 hdsp->playback_mixer_ctls[i]->vd[0].access = SNDRV_CTL_ELEM_ACCESS_INACTIVE |2652 SNDRV_CTL_ELEM_ACCESS_READ |2653 SNDRV_CTL_ELEM_ACCESS_VOLATILE;2654 } else {2655 hdsp->playback_mixer_ctls[i]->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE |2656 SNDRV_CTL_ELEM_ACCESS_VOLATILE;2657 }2658 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |2659 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->playback_mixer_ctls[i]->id);2660 }2661 2662 return 0;2663 }2664 2665 2666 3195 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp) 2667 3196 { 2668 unsigned int idx , limit;3197 unsigned int idx; 2669 3198 int err; 2670 3199 snd_kcontrol_t *kctl; … … 2678 3207 } 2679 3208 2680 snd_hdsp_playback_mixer.name = "Chn";3209 /* ADAT SyncCheck status */ 2681 3210 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 2682 2683 switch (hdsp->io_type) {2684 case Digiface:2685 limit = DIGIFACE_SS_CHANNELS;2686 break;2687 case H9652:2688 limit = H9652_SS_CHANNELS;2689 break;2690 case Multiface:2691 limit = MULTIFACE_SS_CHANNELS;2692 break;2693 default:2694 return -EIO;2695 }2696 2697 /* The index values are one greater than the channel ID so that alsamixer2698 will display them correctly. We want to use the index for fast lookup2699 of the relevant channel, but if we use it at all, most ALSA software2700 does the wrong thing with it ...2701 */2702 2703 for (idx = 0; idx < limit; ++idx) {2704 snd_hdsp_playback_mixer.index = idx+1;2705 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_playback_mixer, hdsp)))) {2706 return err;2707 }2708 hdsp->playback_mixer_ctls[idx] = kctl;2709 }2710 2711 /* ADAT SyncCheck status */2712 3211 snd_hdsp_adat_sync_check.index = 1; 2713 3212 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) { … … 2722 3221 } 2723 3222 } 3223 3224 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ 3225 if (hdsp->io_type == H9632) { 3226 for (idx = 0; idx < HDSP_9632_CONTROLS; idx++) { 3227 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) { 3228 return err; 3229 } 3230 } 3231 } 3232 3233 /* AEB control for H96xx card */ 3234 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 3235 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) { 3236 return err; 3237 } 3238 } 2724 3239 2725 3240 return 0; … … 2814 3329 clock_source = "Internal 96 kHz"; 2815 3330 break; 3331 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 3332 clock_source = "Internal 128 kHz"; 3333 break; 3334 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 3335 clock_source = "Internal 176.4 kHz"; 3336 break; 3337 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 3338 clock_source = "Internal 192 kHz"; 3339 break; 2816 3340 default: 2817 3341 clock_source = "Error"; … … 2886 3410 snd_iprintf(buffer, "\n"); 2887 3411 2888 switch ( (hdsp->control_register & HDSP_SPDIFInputMask) >> 14) {3412 switch (hdsp_spdif_in(hdsp)) { 2889 3413 case HDSP_SPDIFIN_OPTICAL: 2890 snd_iprintf(buffer, "IEC958 input: ADAT1\n");3414 snd_iprintf(buffer, "IEC958 input: Optical\n"); 2891 3415 break; 2892 3416 case HDSP_SPDIFIN_COAXIAL: 2893 3417 snd_iprintf(buffer, "IEC958 input: Coaxial\n"); 2894 3418 break; 2895 case HDSP_SPDIFIN_INTERN :3419 case HDSP_SPDIFIN_INTERNAL: 2896 3420 snd_iprintf(buffer, "IEC958 input: Internal\n"); 3421 break; 3422 case HDSP_SPDIFIN_AES: 3423 snd_iprintf(buffer, "IEC958 input: AES\n"); 2897 3424 break; 2898 3425 default: … … 2982 3509 2983 3510 snd_iprintf(buffer, "\n"); 2984 2985 #if 0 2986 for (x = 0; x < 26; x++) { 2987 unsigned int val = hdsp_read (hdsp, HDSP_inputPeakLevel + (4 * x)); 2988 snd_iprintf (buffer, "%d: input peak = %d overs = %d\n", x, val&0xffffff00, val&0xf); 2989 } 2990 #endif 3511 3512 /* Informations about H9632 specific controls */ 3513 if (hdsp->io_type == H9632) { 3514 char *tmp; 3515 3516 switch (hdsp_ad_gain(hdsp)) { 3517 case 0: 3518 tmp = "-10 dBV"; 3519 break; 3520 case 1: 3521 tmp = "+4 dBu"; 3522 break; 3523 default: 3524 tmp = "Lo Gain"; 3525 break; 3526 } 3527 snd_iprintf(buffer, "AD Gain : %s\n", tmp); 3528 3529 switch (hdsp_da_gain(hdsp)) { 3530 case 0: 3531 tmp = "Hi Gain"; 3532 break; 3533 case 1: 3534 tmp = "+4 dBu"; 3535 break; 3536 default: 3537 tmp = "-10 dBV"; 3538 break; 3539 } 3540 snd_iprintf(buffer, "DA Gain : %s\n", tmp); 3541 3542 switch (hdsp_phone_gain(hdsp)) { 3543 case 0: 3544 tmp = "0 dB"; 3545 break; 3546 case 1: 3547 tmp = "-6 dB"; 3548 break; 3549 default: 3550 tmp = "-12 dB"; 3551 break; 3552 } 3553 snd_iprintf(buffer, "Phones Gain : %s\n", tmp); 3554 3555 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); 3556 3557 if (hdsp->control_register & HDSP_AnalogExtensionBoard) { 3558 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); 3559 } else { 3560 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); 3561 } 3562 snd_iprintf(buffer, "\n"); 3563 } 3564 2991 3565 } 2992 3566 … … 2996 3570 2997 3571 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) 2998 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);3572 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read); 2999 3573 } 3000 3574 … … 3080 3654 hdsp_encode_latency(7) | 3081 3655 HDSP_LineOut; 3656 3082 3657 3083 3658 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3659 3660 #ifdef SNDRV_BIG_ENDIAN 3661 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 3662 #else 3663 hdsp->control2_register = 0; 3664 #endif 3665 if (hdsp->io_type == H9652) { 3666 snd_hdsp_9652_enable_mixer (hdsp); 3667 } else { 3668 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 3669 } 3670 3084 3671 hdsp_reset_hw_pointer(hdsp); 3085 3672 hdsp_compute_period_size(hdsp); … … 3091 3678 } 3092 3679 3093 for (i = 0; i < ( hdsp->io_type == H9652 ? 1352 : HDSP_MATRIX_MIXER_SIZE); i++) {3680 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { 3094 3681 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) { 3095 3682 return -EIO; … … 3098 3685 3099 3686 if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) { 3687 3688 int lineouts_base; 3100 3689 3101 3690 snd_printk ("sending all inputs and playback streams to line outs.\n"); … … 3104 3693 odd numbered channels to right, even to left. 3105 3694 */ 3695 if (hdsp->io_type == H9632) { 3696 /* this is the phones/analog output */ 3697 lineouts_base = 10; 3698 } else { 3699 lineouts_base = 26; 3700 } 3106 3701 3107 for (i = 0; i < HDSP_MAX_CHANNELS; i++) {3702 for (i = 0; i < hdsp->max_channels; i++) { 3108 3703 if (i & 1) { 3109 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, 26), UNITY_GAIN) ||3110 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, 26), UNITY_GAIN)) {3704 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) || 3705 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) { 3111 3706 return -EIO; 3112 3707 } 3113 3708 } else { 3114 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, 27), UNITY_GAIN) || 3115 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, 27), UNITY_GAIN)) { 3709 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) || 3710 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) { 3711 3116 3712 return -EIO; 3117 3713 } … … 3121 3717 3122 3718 hdsp->passthru = 0; 3719 3720 /* H9632 specific defaults */ 3721 if (hdsp->io_type == H9632) { 3722 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); 3723 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3724 } 3123 3725 3124 3726 /* set a default rate so that the channel map is set up. … … 3210 3812 int mapped_channel; 3211 3813 3212 snd_assert(channel >= 0 || channel < HDSP_MAX_CHANNELS, return NULL);3814 snd_assert(channel >= 0 || channel < hdsp->max_channels, return NULL); 3213 3815 3214 3816 if ((mapped_channel = hdsp->channel_map[channel]) < 0) { … … 3382 3984 int mapped_channel; 3383 3985 3384 snd_assert(info->channel < HDSP_MAX_CHANNELS, return -EINVAL);3986 snd_assert(info->channel < hdsp->max_channels, return -EINVAL); 3385 3987 3386 3988 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) { … … 3571 4173 }; 3572 4174 3573 static unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };3574 3575 #define PERIOD_SIZES sizeof(period_sizes) / sizeof(period_sizes[0])3576 3577 static snd_pcm_hw_constraint_list_t h w_constraints_period_sizes = {3578 .count = PERIOD_SIZES,3579 .list = period_sizes,4175 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; 4176 4177 #define HDSP_PERIOD_SIZES sizeof(hdsp_period_sizes) / sizeof(hdsp_period_sizes[0]) 4178 4179 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = { 4180 .count = HDSP_PERIOD_SIZES, 4181 .list = hdsp_period_sizes, 3580 4182 .mask = 0 3581 4183 }; 3582 4184 3583 static int snd_hdsp_hw_rule_channels(snd_pcm_hw_params_t *params, 4185 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; 4186 4187 #define HDSP_9632_SAMPLE_RATES sizeof(hdsp_9632_sample_rates) / sizeof(hdsp_9632_sample_rates[0]) 4188 4189 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = { 4190 .count = HDSP_9632_SAMPLE_RATES, 4191 .list = hdsp_9632_sample_rates, 4192 .mask = 0 4193 }; 4194 4195 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params, 3584 4196 snd_pcm_hw_rule_t *rule) 3585 4197 { 3586 4198 hdsp_t *hdsp = rule->private; 3587 4199 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 3588 unsigned int list[2] = { hdsp->ds_channels, hdsp->ss_channels }; 4200 if (hdsp->io_type == H9632) { 4201 unsigned int list[3]; 4202 list[0] = hdsp->qs_in_channels; 4203 list[1] = hdsp->ds_in_channels; 4204 list[2] = hdsp->ss_in_channels; 4205 return snd_interval_list(c, 3, list, 0); 4206 } else { 4207 unsigned int list[2]; 4208 list[0] = hdsp->ds_in_channels; 4209 list[1] = hdsp->ss_in_channels; 4210 return snd_interval_list(c, 2, list, 0); 4211 } 4212 } 4213 4214 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params, 4215 snd_pcm_hw_rule_t *rule) 4216 { 4217 unsigned int list[3]; 4218 hdsp_t *hdsp = rule->private; 4219 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4220 if (hdsp->io_type == H9632) { 4221 list[0] = hdsp->qs_out_channels; 4222 list[1] = hdsp->ds_out_channels; 4223 list[2] = hdsp->ss_out_channels; 4224 return snd_interval_list(c, 3, list, 0); 4225 } else { 4226 list[0] = hdsp->ds_out_channels; 4227 list[1] = hdsp->ss_out_channels; 4228 } 3589 4229 return snd_interval_list(c, 2, list, 0); 3590 4230 } 3591 4231 3592 static int snd_hdsp_hw_rule_ channels_rate(snd_pcm_hw_params_t *params,4232 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params, 3593 4233 snd_pcm_hw_rule_t *rule) 3594 4234 { … … 3596 4236 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 3597 4237 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 3598 if (r->min > 48000) {4238 if (r->min > 96000 && hdsp->io_type == H9632) { 3599 4239 snd_interval_t t = { 3600 .min = hdsp->ds_channels, 3601 .max = hdsp->ds_channels, 4240 .min = hdsp->qs_in_channels, 4241 .max = hdsp->qs_in_channels, 4242 .integer = 1, 4243 }; 4244 return snd_interval_refine(c, &t); 4245 } else if (r->min > 48000 && r->max <= 96000) { 4246 snd_interval_t t = { 4247 .min = hdsp->ds_in_channels, 4248 .max = hdsp->ds_in_channels, 3602 4249 .integer = 1, 3603 4250 }; … … 3605 4252 } else if (r->max < 64000) { 3606 4253 snd_interval_t t = { 3607 .min = hdsp->ss_ channels,3608 .max = hdsp->ss_ channels,4254 .min = hdsp->ss_in_channels, 4255 .max = hdsp->ss_in_channels, 3609 4256 .integer = 1, 3610 4257 }; … … 3614 4261 } 3615 4262 3616 static int snd_hdsp_hw_rule_ rate_channels(snd_pcm_hw_params_t *params,4263 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params, 3617 4264 snd_pcm_hw_rule_t *rule) 3618 4265 { … … 3620 4267 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 3621 4268 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 3622 if (c->min >= hdsp->ss_channels) { 4269 if (r->min > 96000 && hdsp->io_type == H9632) { 4270 snd_interval_t t = { 4271 .min = hdsp->qs_out_channels, 4272 .max = hdsp->qs_out_channels, 4273 .integer = 1, 4274 }; 4275 return snd_interval_refine(c, &t); 4276 } else if (r->min > 48000 && r->max <= 96000) { 4277 snd_interval_t t = { 4278 .min = hdsp->ds_out_channels, 4279 .max = hdsp->ds_out_channels, 4280 .integer = 1, 4281 }; 4282 return snd_interval_refine(c, &t); 4283 } else if (r->max < 64000) { 4284 snd_interval_t t = { 4285 .min = hdsp->ss_out_channels, 4286 .max = hdsp->ss_out_channels, 4287 .integer = 1, 4288 }; 4289 return snd_interval_refine(c, &t); 4290 } 4291 return 0; 4292 } 4293 4294 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params, 4295 snd_pcm_hw_rule_t *rule) 4296 { 4297 hdsp_t *hdsp = rule->private; 4298 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4299 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4300 if (c->min >= hdsp->ss_out_channels) { 3623 4301 snd_interval_t t = { 3624 4302 .min = 32000, … … 3627 4305 }; 3628 4306 return snd_interval_refine(r, &t); 3629 } else if (c->max <= hdsp->ds_channels) { 4307 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { 4308 snd_interval_t t = { 4309 .min = 128000, 4310 .max = 192000, 4311 .integer = 1, 4312 }; 4313 return snd_interval_refine(r, &t); 4314 } else if (c->max <= hdsp->ds_out_channels) { 4315 snd_interval_t t = { 4316 .min = 64000, 4317 .max = 96000, 4318 .integer = 1, 4319 }; 4320 return snd_interval_refine(r, &t); 4321 } 4322 return 0; 4323 } 4324 4325 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params, 4326 snd_pcm_hw_rule_t *rule) 4327 { 4328 hdsp_t *hdsp = rule->private; 4329 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4330 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4331 if (c->min >= hdsp->ss_in_channels) { 4332 snd_interval_t t = { 4333 .min = 32000, 4334 .max = 48000, 4335 .integer = 1, 4336 }; 4337 return snd_interval_refine(r, &t); 4338 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { 4339 snd_interval_t t = { 4340 .min = 128000, 4341 .max = 192000, 4342 .integer = 1, 4343 }; 4344 return snd_interval_refine(r, &t); 4345 } else if (c->max <= hdsp->ds_in_channels) { 3630 4346 snd_interval_t t = { 3631 4347 .min = 64000, … … 3678 4394 3679 4395 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 3680 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes); 4396 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4397 if (hdsp->io_type == H9632) { 4398 runtime->hw.channels_min = hdsp->qs_out_channels; 4399 runtime->hw.channels_max = hdsp->ss_out_channels; 4400 runtime->hw.rate_max = 192000; 4401 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4402 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4403 } 4404 3681 4405 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 3682 snd_hdsp_hw_rule_ channels, hdsp,4406 snd_hdsp_hw_rule_out_channels, hdsp, 3683 4407 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 3684 4408 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 3685 snd_hdsp_hw_rule_ channels_rate, hdsp,4409 snd_hdsp_hw_rule_out_channels_rate, hdsp, 3686 4410 SNDRV_PCM_HW_PARAM_RATE, -1); 3687 4411 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 3688 snd_hdsp_hw_rule_rate_ channels, hdsp,4412 snd_hdsp_hw_rule_rate_out_channels, hdsp, 3689 4413 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 3690 4414 … … 3755 4479 3756 4480 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 3757 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes); 4481 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4482 if (hdsp->io_type == H9632) { 4483 runtime->hw.channels_min = hdsp->qs_in_channels; 4484 runtime->hw.channels_max = hdsp->ss_in_channels; 4485 runtime->hw.rate_max = 192000; 4486 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4487 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4488 } 3758 4489 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 3759 snd_hdsp_hw_rule_ channels, hdsp,4490 snd_hdsp_hw_rule_in_channels, hdsp, 3760 4491 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 3761 4492 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 3762 snd_hdsp_hw_rule_ channels_rate, hdsp,4493 snd_hdsp_hw_rule_in_channels_rate, hdsp, 3763 4494 SNDRV_PCM_HW_PARAM_RATE, -1); 3764 4495 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 3765 snd_hdsp_hw_rule_rate_ channels, hdsp,4496 snd_hdsp_hw_rule_rate_in_channels, hdsp, 3766 4497 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 3767 4498 return 0; … … 3784 4515 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file) 3785 4516 { 3786 /* we have nothing to initialize but the call is required */3787 return 0;4517 /* we have nothing to initialize but the call is required */ 4518 return 0; 3788 4519 } 3789 4520 … … 3792 4523 { 3793 4524 hdsp_t *hdsp = (hdsp_t *)hw->private_data; 3794 4525 3795 4526 switch (cmd) { 3796 4527 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { 3797 4528 hdsp_peak_rms_t *peak_rms; 3798 4529 int i; 4530 3799 4531 if (hdsp->io_type == H9652) { 3800 snd_printk("hardware metering isn't supported yet for hdsp9652 cards\n"); 3801 return -EINVAL; 4532 unsigned long rms_low, rms_high; 4533 int doublespeed = 0; 4534 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4535 doublespeed = 1; 4536 peak_rms = (hdsp_peak_rms_t *)arg; 4537 for (i = 0; i < 26; ++i) { 4538 if (!(doublespeed && (i & 4))) { 4539 if (copy_to_user_fromio((void *)peak_rms->input_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-i*4, 4) != 0) 4540 return -EFAULT; 4541 if (copy_to_user_fromio((void *)peak_rms->playback_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-(doublespeed ? 14 : 26)*4-i*4, 4) != 0) 4542 return -EFAULT; 4543 if (copy_to_user_fromio((void *)peak_rms->output_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-2*(doublespeed ? 14 : 26)*4-i*4, 4) != 0) 4544 return -EFAULT; 4545 rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8) & 0xFFFFFF00; 4546 rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8+4) & 0xFFFFFF00; 4547 rms_high += (rms_low >> 24); 4548 rms_low <<= 8; 4549 if (copy_to_user((void *)peak_rms->input_rms+i*8, &rms_low, 4) != 0) 4550 return -EFAULT; 4551 if (copy_to_user((void *)peak_rms->input_rms+i*8+4, &rms_high, 4) != 0) 4552 return -EFAULT; 4553 rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00; 4554 rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00; 4555 rms_high += (rms_low >> 24); 4556 rms_low <<= 8; 4557 if (copy_to_user((void *)peak_rms->playback_rms+i*8, &rms_low, 4) != 0) 4558 return -EFAULT; 4559 if (copy_to_user((void *)peak_rms->playback_rms+i*8+4, &rms_high, 4) != 0) 4560 return -EFAULT; 4561 rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00; 4562 rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00; 4563 rms_high += (rms_low >> 24); 4564 rms_low <<= 8; 4565 if (copy_to_user((void *)peak_rms->output_rms+i*8, &rms_low, 4) != 0) 4566 return -EFAULT; 4567 if (copy_to_user((void *)peak_rms->output_rms+i*8+4, &rms_high, 4) != 0) 4568 return -EFAULT; 4569 } 4570 } 4571 return 0; 4572 } 4573 if (hdsp->io_type == H9632) { 4574 int j; 4575 hdsp_9632_meters_t *m; 4576 int doublespeed = 0; 4577 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4578 doublespeed = 1; 4579 m = (hdsp_9632_meters_t *)(hdsp->iobase+HDSP_9632_metersBase); 4580 peak_rms = (hdsp_peak_rms_t *)arg; 4581 for (i = 0, j = 0; i < 16; ++i, ++j) { 4582 if (copy_to_user((void *)peak_rms->input_peaks+i*4, &(m->input_peak[j]), 4) != 0) 4583 return -EFAULT; 4584 if (copy_to_user((void *)peak_rms->playback_peaks+i*4, &(m->playback_peak[j]), 4) != 0) 4585 return -EFAULT; 4586 if (copy_to_user((void *)peak_rms->output_peaks+i*4, &(m->output_peak[j]), 4) != 0) 4587 return -EFAULT; 4588 if (copy_to_user((void *)peak_rms->input_rms+i*8, &(m->input_rms_low[j]), 4) != 0) 4589 return -EFAULT; 4590 if (copy_to_user((void *)peak_rms->playback_rms+i*8, &(m->playback_rms_low[j]), 4) != 0) 4591 return -EFAULT; 4592 if (copy_to_user((void *)peak_rms->output_rms+i*8, &(m->output_rms_low[j]), 4) != 0) 4593 return -EFAULT; 4594 if (copy_to_user((void *)peak_rms->input_rms+i*8+4, &(m->input_rms_high[j]), 4) != 0) 4595 return -EFAULT; 4596 if (copy_to_user((void *)peak_rms->playback_rms+i*8+4, &(m->playback_rms_high[j]), 4) != 0) 4597 return -EFAULT; 4598 if (copy_to_user((void *)peak_rms->output_rms+i*8+4, &(m->output_rms_high[j]), 4) != 0) 4599 return -EFAULT; 4600 if (doublespeed && i == 3) i += 4; 4601 } 4602 return 0; 3802 4603 } 3803 4604 if (!(hdsp->state & HDSP_FirmwareLoaded)) { … … 3806 4607 } 3807 4608 peak_rms = (hdsp_peak_rms_t *)arg; 3808 if (copy_to_user_fromio((void *)peak_rms->playback_peaks, hdsp->iobase+HDSP_playbackPeakLevel, 26*4) != 0) { 3809 return -EFAULT; 3810 } 3811 if (copy_to_user_fromio((void *)peak_rms->input_peaks, hdsp->iobase+HDSP_inputPeakLevel, 26*4) != 0) { 3812 return -EFAULT; 3813 } 3814 if (copy_to_user_fromio((void *)peak_rms->output_peaks, hdsp->iobase+HDSP_outputPeakLevel, 28*4) != 0) { 3815 return -EFAULT; 3816 } 3817 if (copy_to_user_fromio((void *)peak_rms->playback_rms, hdsp->iobase+HDSP_playbackRmsLevel, 26*8) != 0) { 3818 return -EFAULT; 3819 } 3820 if (copy_to_user_fromio((void *)peak_rms->input_rms, hdsp->iobase+HDSP_inputRmsLevel, 26*8) != 0) { 3821 return -EFAULT; 4609 for (i = 0; i < 26; ++i) { 4610 if (copy_to_user((void *)peak_rms->playback_peaks+i*4, (void *)hdsp->iobase+HDSP_playbackPeakLevel+i*4, 4) != 0) 4611 return -EFAULT; 4612 if (copy_to_user((void *)peak_rms->input_peaks+i*4, (void *)hdsp->iobase+HDSP_inputPeakLevel+i*4, 4) != 0) 4613 return -EFAULT; 4614 } 4615 for (i = 0; i < 26; ++i) { 4616 if (copy_to_user((void *)peak_rms->playback_rms+i*8+4, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8, 4) != 0) 4617 return -EFAULT; 4618 if (copy_to_user((void *)peak_rms->playback_rms+i*8, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8+4, 4) != 0) 4619 return -EFAULT; 4620 if (copy_to_user((void *)peak_rms->input_rms+i*8+4, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8, 4) != 0) 4621 return -EFAULT; 4622 if (copy_to_user((void *)peak_rms->input_rms+i*8, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8+4, 4) != 0) 4623 return -EFAULT; 4624 } 4625 for (i = 0; i < 28; ++i) { 4626 if (copy_to_user((void *)peak_rms->output_peaks+i*4, (void *)hdsp->iobase+HDSP_outputPeakLevel+i*4, 4) != 0) 4627 return -EFAULT; 3822 4628 } 3823 4629 break; … … 3827 4633 unsigned long flags; 3828 4634 int i; 3829 4635 3830 4636 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 3831 4637 snd_printk("Firmware needs to be uploaded to the card.\n"); … … 3835 4641 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 3836 4642 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 3837 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4643 if (hdsp->io_type != H9632) { 4644 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4645 } 3838 4646 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 3839 for (i = 0; i < ((hdsp->io_type != Multiface ) ? 3 : 1); ++i) {4647 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) { 3840 4648 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 3841 4649 } … … 3853 4661 info.line_out = (unsigned char)hdsp_line_out(hdsp); 3854 4662 info.passthru = (unsigned char)hdsp->passthru; 4663 if (hdsp->io_type == H9632) { 4664 info.da_gain = (unsigned char)hdsp_da_gain(hdsp); 4665 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); 4666 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); 4667 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); 4668 4669 } 4670 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 4671 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); 4672 } 3855 4673 spin_unlock_irqrestore(&hdsp->lock, flags); 3856 4674 if (copy_to_user((void *)arg, &info, sizeof(info))) … … 3858 4676 break; 3859 4677 } 4678 case SNDRV_HDSP_IOCTL_GET_9632_AEB: { 4679 hdsp_9632_aeb_t h9632_aeb; 4680 4681 if (hdsp->io_type != H9632) return -EINVAL; 4682 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; 4683 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; 4684 if (copy_to_user((void *)arg, &h9632_aeb, sizeof(h9632_aeb))) 4685 return -EFAULT; 4686 break; 4687 } 3860 4688 case SNDRV_HDSP_IOCTL_GET_VERSION: { 3861 4689 hdsp_version_t hdsp_version; 3862 4690 int err; 3863 3864 if (hdsp->io_type == H9652 ) return -EINVAL;4691 4692 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 3865 4693 if (hdsp->io_type == Undefined) { 3866 4694 if ((err = hdsp_get_iobox_version(hdsp)) < 0) { … … 3879 4707 unsigned long *firmware_data; 3880 4708 int err; 3881 3882 if (hdsp->io_type == H9652 ) return -EINVAL;4709 4710 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 3883 4711 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 3884 4712 if (hdsp->io_type == Undefined) return -EINVAL; … … 3886 4714 snd_printk("initializing firmware upload\n"); 3887 4715 firmware = (hdsp_firmware_t *)arg; 4716 3888 4717 if (get_user(firmware_data, &firmware->firmware_data)) { 3889 4718 return -EFAULT; 3890 4719 } 3891 4720 3892 4721 if (hdsp_check_for_iobox (hdsp)) { 3893 4722 return -EIO; … … 3903 4732 return err; 3904 4733 } 3905 3906 4734 3907 4735 if (!(hdsp->state & HDSP_InitializationComplete)) { … … 3918 4746 } 3919 4747 case SNDRV_HDSP_IOCTL_GET_MIXER: { 3920 hdsp_mixer_t *mixer;3921 4748 hdsp_mixer_t *mixer; 4749 3922 4750 mixer = (hdsp_mixer_t *)arg; 3923 4751 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) … … 4015 4843 } 4016 4844 4017 for (i = 0; i < HDSP_MAX_CHANNELS; ++i) {4845 for (i = 0; i < hdsp->max_channels; ++i) { 4018 4846 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 4019 4847 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); … … 4025 4853 static inline void snd_hdsp_initialize_channels(hdsp_t *hdsp) 4026 4854 { 4855 int status, aebi_channels, aebo_channels; 4856 4027 4857 switch (hdsp->io_type) { 4028 4858 case Digiface: 4029 4859 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 4030 hdsp->ss_ channels = DIGIFACE_SS_CHANNELS;4031 hdsp->ds_ channels = DIGIFACE_DS_CHANNELS;4860 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; 4861 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; 4032 4862 break; 4033 4863 4034 4864 case H9652: 4035 4865 hdsp->card_name = "RME Hammerfall HDSP 9652"; 4036 hdsp->ss_channels = H9652_SS_CHANNELS; 4037 hdsp->ds_channels = H9652_DS_CHANNELS; 4866 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; 4867 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; 4868 break; 4869 4870 case H9632: 4871 status = hdsp_read(hdsp, HDSP_statusRegister); 4872 /* HDSP_AEBx bits are low when AEB are connected */ 4873 aebi_channels = (status & HDSP_AEBI) ? 0 : 4; 4874 aebo_channels = (status & HDSP_AEBO) ? 0 : 4; 4875 hdsp->card_name = "RME Hammerfall HDSP 9632"; 4876 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; 4877 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; 4878 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; 4879 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; 4880 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; 4881 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; 4038 4882 break; 4039 4883 4040 4884 case Multiface: 4041 4885 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 4042 hdsp->ss_channels = MULTIFACE_SS_CHANNELS; 4043 hdsp->ds_channels = MULTIFACE_DS_CHANNELS; 4044 4886 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; 4887 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; 4888 break; 4889 4045 4890 default: 4046 4891 /* should never get here */ … … 4060 4905 4061 4906 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { 4907 snd_printk("Error creating pcm interface\n"); 4062 4908 return err; 4063 4909 } 4064 4910 4911 4065 4912 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { 4913 snd_printk("Error creating first midi interface\n"); 4066 4914 return err; 4067 4915 } 4068 4916 4917 4069 4918 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { 4919 snd_printk("Error creating second midi interface\n"); 4070 4920 return err; 4071 4921 } 4072 4922 4073 4923 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { 4924 snd_printk("Error creating ctl interface\n"); 4074 4925 return err; 4075 4926 } … … 4077 4928 snd_hdsp_proc_init(hdsp); 4078 4929 4079 hdsp->last_spdif_sample_rate = -1;4080 4930 hdsp->system_sample_rate = -1; 4081 hdsp->last_external_sample_rate = -1;4082 hdsp->last_internal_sample_rate = -1;4083 4931 hdsp->playback_pid = -1; 4084 4932 hdsp->capture_pid = -1; … … 4087 4935 4088 4936 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { 4937 snd_printk("Error setting default values\n"); 4089 4938 return err; 4090 4939 } 4091 4092 hdsp_update_simple_mixer_controls(hdsp);4093 4940 4094 4941 if (!(hdsp->state & HDSP_InitializationComplete)) { … … 4112 4959 struct pci_dev *pci = hdsp->pci; 4113 4960 int err; 4114 int i;4115 4961 int is_9652 = 0; 4962 int is_9632 = 0; 4116 4963 4117 4964 hdsp->irq = -1; … … 4127 4974 hdsp->iobase = 0; 4128 4975 hdsp->res_port = 0; 4976 hdsp->control_register = 0; 4977 hdsp->control2_register = 0; 4129 4978 hdsp->io_type = Undefined; 4130 for (i = 0; i < HDSP_MAX_CHANNELS; ++i) 4131 hdsp->playback_mixer_ctls[i] = 0; 4979 hdsp->max_channels = 26; 4132 4980 4133 4981 hdsp->card = card; … … 4154 5002 is_9652 = 1; 4155 5003 break; 4156 5004 case 0x96: 5005 hdsp->card_name = "RME HDSP 9632"; 5006 hdsp->max_channels = 16; 5007 is_9632 = 1; 5008 break; 4157 5009 default: 4158 5010 return -ENODEV; … … 4189 5041 } 4190 5042 4191 if (!is_9652 && hdsp_check_for_iobox (hdsp)) {5043 if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) { 4192 5044 /* no iobox connected, we defer initialization */ 4193 5045 snd_printk("card initialization pending : waiting for firmware\n"); … … 4220 5072 if (is_9652) { 4221 5073 hdsp->io_type = H9652; 4222 snd_hdsp_9652_enable_mixer (hdsp); 5074 } 5075 5076 if (is_9632) { 5077 hdsp->io_type = H9632; 4223 5078 } 4224 5079 -
GPL/branches/alsa-resync1/alsa-kernel/pci/rme9652/rme9652.c
r262 r281 1618 1618 RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0), 1619 1619 RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1), 1620 RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2),1621 1620 RME9652_TC_VALID("Timecode Valid", 0), 1622 1621 RME9652_PASSTHRU("Passthru", 0) … … 1835 1834 1836 1835 if (! snd_card_proc_new(rme9652->card, "rme9652", &entry)) 1837 snd_info_set_text_ops(entry, rme9652, snd_rme9652_proc_read);1836 snd_info_set_text_ops(entry, rme9652, 1024, snd_rme9652_proc_read); 1838 1837 } 1839 1838 -
GPL/branches/alsa-resync1/alsa-kernel/pci/sonicvibes.c
r262 r281 1182 1182 1183 1183 if (! snd_card_proc_new(sonic->card, "sonicvibes", &entry)) 1184 snd_info_set_text_ops(entry, sonic, snd_sonicvibes_proc_read);1184 snd_info_set_text_ops(entry, sonic, 1024, snd_sonicvibes_proc_read); 1185 1185 } 1186 1186 … … 1258 1258 return -ENXIO; 1259 1259 } 1260 pci_set_ dma_mask(pci, 0x00ffffff);1260 pci_set_consistent_dma_mask(pci, 0x00ffffff); 1261 1261 1262 1262 sonic = snd_magic_kcalloc(sonicvibes_t, 0, GFP_KERNEL); -
GPL/branches/alsa-resync1/alsa-kernel/pci/ymfpci/ymfpci.c
r277 r281 135 135 136 136 if (pci_id->device >= 0x0010) { /* YMF 744/754 */ 137 if (fm_port[dev] <= 0) { 137 if (fm_port[dev] == 1) { 138 /* auto-detect */ 138 139 fm_port[dev] = pci_resource_start(pci, 1); 139 140 } … … 143 144 pci_write_config_word(pci, PCIR_DSXG_FMBASE, fm_port[dev]); 144 145 } 145 if (mpu_port[dev] <= 0) { 146 if (mpu_port[dev] == 1) { 147 /* auto-detect */ 146 148 mpu_port[dev] = pci_resource_start(pci, 1) + 0x20; 147 149 } … … 152 154 } 153 155 #ifdef SUPPORT_JOYSTICK 154 if (joystick_port[dev] < 0) { 156 if (joystick_port[dev] == 1) { 157 /* auto-detect */ 155 158 joystick_port[dev] = pci_resource_start(pci, 2); 156 159 } 157 if (joystick_port[dev] > =0 &&160 if (joystick_port[dev] > 0 && 158 161 (joystick_res = request_region(joystick_port[dev], 1, "YMFPCI gameport")) != NULL) { 159 162 legacy_ctrl |= YMFPCI_LEGACY_JPEN; … … 167 170 case 0x3a0: legacy_ctrl2 |= 2; break; 168 171 case 0x3a8: legacy_ctrl2 |= 3; break; 169 default: fm_port[dev] = -1; break;172 default: fm_port[dev] = 0; break; 170 173 } 171 174 if (fm_port[dev] > 0 && … … 174 177 } else { 175 178 legacy_ctrl2 &= ~YMFPCI_LEGACY2_FMIO; 176 fm_port[dev] = -1;179 fm_port[dev] = 0; 177 180 } 178 181 switch (mpu_port[dev]) { … … 181 184 case 0x332: legacy_ctrl2 |= 2 << 4; break; 182 185 case 0x334: legacy_ctrl2 |= 3 << 4; break; 183 default: mpu_port[dev] = -1; break;186 default: mpu_port[dev] = 0; break; 184 187 } 185 188 if (mpu_port[dev] > 0 && … … 188 191 } else { 189 192 legacy_ctrl2 &= ~YMFPCI_LEGACY2_MPUIO; 190 mpu_port[dev] = -1; 191 } 192 #ifdef SUPPORT_JOYSTICK 193 mpu_port[dev] = 0; 194 } 195 #ifdef SUPPORT_JOYSTICK 196 if (joystick_port[dev] == 1) { 197 /* auto-detect */ 198 long p; 199 for (p = 0x201; p <= 0x205; p++) { 200 if (p == 0x203) continue; 201 if ((joystick_res = request_region(p, 1, "YMFPCI gameport")) != NULL) 202 break; 203 } 204 if (joystick_res) 205 joystick_port[dev] = p; 206 } 193 207 switch (joystick_port[dev]) { 194 208 case 0x201: legacy_ctrl2 |= 0 << 6; break; … … 196 210 case 0x204: legacy_ctrl2 |= 2 << 6; break; 197 211 case 0x205: legacy_ctrl2 |= 3 << 6; break; 198 default: joystick_port[dev] = -1; break; 199 } 200 if (joystick_port[dev] > 0 && 201 (joystick_res = request_region(joystick_port[dev], 1, "YMFPCI gameport")) != NULL) { 212 default: joystick_port[dev] = 0; break; 213 } 214 if (! joystick_res && joystick_port[dev] > 0) 215 joystick_res = request_region(joystick_port[dev], 1, "YMFPCI gameport"); 216 if (joystick_res) { 202 217 legacy_ctrl |= YMFPCI_LEGACY_JPEN; 203 218 } else { 204 219 legacy_ctrl2 &= ~YMFPCI_LEGACY2_JSIO; 205 joystick_port[dev] = -1;220 joystick_port[dev] = 0; 206 221 } 207 222 #endif
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