Changeset 246 for GPL/branches/alsa-resync1/alsa-kernel/pci
- Timestamp:
- Aug 22, 2007, 5:33:25 AM (18 years ago)
- Location:
- GPL/branches/alsa-resync1/alsa-kernel/pci
- Files:
-
- 14 edited
- 1 moved
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ice1712/ak4xxx.c (moved) (moved from GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ak4524.c ) (4 diffs)
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ice1712/delta.c (modified) (16 diffs)
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ice1712/ews.c (modified) (17 diffs)
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ice1712/ice1712.c (modified) (20 diffs)
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ice1712/ice1712.h (modified) (5 diffs)
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ice1712/ice1724.c (modified) (19 diffs)
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ice1712/makefile.os2 (modified) (1 diff)
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ice1712/revo.c (modified) (6 diffs)
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korg1212/korg1212.c (modified) (31 diffs)
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rme96.c (modified) (3 diffs)
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rme9652/hdsp.c (modified) (109 diffs)
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rme9652/rme9652.c (modified) (7 diffs)
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sonicvibes.c (modified) (2 diffs)
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trident/trident_main.c (modified) (3 diffs)
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ymfpci/ymfpci_main.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ak4xxx.c
r244 r246 30 30 #include "ice1712.h" 31 31 32 static void snd_ice1712_akm4xxx_lock(akm4xxx_t *ak, int chip) 33 { 34 ice1712_t *ice = ak->private_data[0]; 35 36 snd_ice1712_save_gpio_status(ice); 37 } 38 39 static void snd_ice1712_akm4xxx_unlock(akm4xxx_t *ak, int chip) 40 { 41 ice1712_t *ice = ak->private_data[0]; 42 43 snd_ice1712_restore_gpio_status(ice); 44 } 32 45 33 46 /* 34 47 * write AK4xxx register 35 48 */ 36 void snd_ice1712_akm4xxx_write(akm4xxx_t *ak, int chip,37 unsigned char addr, unsigned char data)49 static void snd_ice1712_akm4xxx_write(akm4xxx_t *ak, int chip, 50 unsigned char addr, unsigned char data) 38 51 { 39 52 unsigned int tmp; 40 53 int idx; 41 54 unsigned int addrdata; 42 ice1712_t *ice = ak->chip; 55 struct snd_ak4xxx_private *priv = (void *)ak->private_value[0]; 56 ice1712_t *ice = ak->private_data[0]; 43 57 44 58 snd_assert(chip >= 0 && chip < 4, return); 45 59 46 if (ak->ops.start) {47 if (ak->ops.start(ak, chip) < 0)48 return;49 } else50 snd_ice1712_save_gpio_status(ice);51 52 60 tmp = snd_ice1712_gpio_read(ice); 53 tmp |= ak->add_flags;54 tmp &= ~ ak->mask_flags;55 if ( ak->cs_mask == ak->cs_addr) {56 if ( ak->cif) {57 tmp |= ak->cs_mask; /* start without chip select */61 tmp |= priv->add_flags; 62 tmp &= ~priv->mask_flags; 63 if (priv->cs_mask == priv->cs_addr) { 64 if (priv->cif) { 65 tmp |= priv->cs_mask; /* start without chip select */ 58 66 } else { 59 tmp &= ~ ak->cs_mask; /* chip select low */67 tmp &= ~priv->cs_mask; /* chip select low */ 60 68 snd_ice1712_gpio_write(ice, tmp); 61 69 udelay(1); … … 63 71 } else { 64 72 /* doesn't handle cf=1 yet */ 65 tmp &= ~ ak->cs_mask;66 tmp |= ak->cs_addr;73 tmp &= ~priv->cs_mask; 74 tmp |= priv->cs_addr; 67 75 snd_ice1712_gpio_write(ice, tmp); 68 76 udelay(1); … … 70 78 71 79 /* build I2C address + data byte */ 72 addrdata = ( ak->caddr << 6) | 0x20 | (addr & 0x1f);80 addrdata = (priv->caddr << 6) | 0x20 | (addr & 0x1f); 73 81 addrdata = (addrdata << 8) | data; 74 82 for (idx = 15; idx >= 0; idx--) { 75 83 /* drop clock */ 76 tmp &= ~ ak->clk_mask;84 tmp &= ~priv->clk_mask; 77 85 snd_ice1712_gpio_write(ice, tmp); 78 86 udelay(1); 79 87 /* set data */ 80 88 if (addrdata & (1 << idx)) 81 tmp |= ak->data_mask;89 tmp |= priv->data_mask; 82 90 else 83 tmp &= ~ ak->data_mask;91 tmp &= ~priv->data_mask; 84 92 snd_ice1712_gpio_write(ice, tmp); 85 93 udelay(1); 86 94 /* raise clock */ 87 tmp |= ak->clk_mask;95 tmp |= priv->clk_mask; 88 96 snd_ice1712_gpio_write(ice, tmp); 89 97 udelay(1); … … 101 109 } 102 110 103 if ( ak->cs_mask == ak->cs_addr) {104 if ( ak->cif) {111 if (priv->cs_mask == priv->cs_addr) { 112 if (priv->cif) { 105 113 /* assert a cs pulse to trigger */ 106 tmp &= ~ ak->cs_mask;114 tmp &= ~priv->cs_mask; 107 115 snd_ice1712_gpio_write(ice, tmp); 108 116 udelay(1); 109 117 } 110 tmp |= ak->cs_mask; /* chip select high to trigger */118 tmp |= priv->cs_mask; /* chip select high to trigger */ 111 119 } else { 112 tmp &= ~ ak->cs_mask;113 tmp |= ak->cs_none; /* deselect address */120 tmp &= ~priv->cs_mask; 121 tmp |= priv->cs_none; /* deselect address */ 114 122 } 115 123 snd_ice1712_gpio_write(ice, tmp); 116 124 udelay(1); 117 118 if (ak->ops.stop)119 ak->ops.stop(ak);120 else121 snd_ice1712_restore_gpio_status(ice);122 125 } 123 124 /*125 * reset the AKM codecs126 * @state: 1 = reset codec, 0 = restore the registers127 *128 * assert the reset operation and restores the register values to the chips.129 */130 void snd_ice1712_akm4xxx_reset(akm4xxx_t *ak, int state)131 {132 unsigned int chip;133 unsigned char reg;134 135 switch (ak->type) {136 case SND_AK4524:137 case SND_AK4528:138 for (chip = 0; chip < ak->num_dacs/2; chip++) {139 snd_ice1712_akm4xxx_write(ak, chip, 0x01, state ? 0x00 : 0x03);140 if (state)141 continue;142 /* DAC volumes */143 for (reg = 0x04; reg < (ak->type == SND_AK4528 ? 0x06 : 0x08); reg++)144 snd_ice1712_akm4xxx_write(ak, chip, reg, ak->images[chip][reg]);145 if (ak->type == SND_AK4528)146 continue;147 /* IPGA */148 for (reg = 0x04; reg < 0x06; reg++)149 snd_ice1712_akm4xxx_write(ak, chip, reg, ak->ipga_gain[chip][reg-4]);150 }151 break;152 case SND_AK4529:153 /* FIXME: needed for ak4529? */154 break;155 case SND_AK4355:156 snd_ice1712_akm4xxx_write(ak, 0, 0x01, state ? 0x02 : 0x01);157 if (state)158 return;159 for (reg = 0x00; reg < 0x0a; reg++)160 if (reg != 0x01)161 snd_ice1712_akm4xxx_write(ak, 0, reg, ak->images[0][reg]);162 break;163 case SND_AK4381:164 for (chip = 0; chip < ak->num_dacs/2; chip++) {165 snd_ice1712_akm4xxx_write(ak, chip, 0x00, state ? 0x0c : 0x0f);166 if (state)167 continue;168 for (reg = 0x01; reg < 0x05; reg++)169 snd_ice1712_akm4xxx_write(ak, chip, reg, ak->images[chip][reg]);170 }171 break;172 }173 }174 175 /*176 * initialize all the ak4xxx chips177 */178 static void __devinit snd_ice1712_akm4xxx_init_chip(akm4xxx_t *ak)179 {180 static unsigned char inits_ak4524[] = {181 0x00, 0x07, /* 0: all power up */182 0x01, 0x00, /* 1: ADC/DAC reset */183 0x02, 0x60, /* 2: 24bit I2S */184 0x03, 0x19, /* 3: deemphasis off */185 0x01, 0x03, /* 1: ADC/DAC enable */186 0x04, 0x00, /* 4: ADC left muted */187 0x05, 0x00, /* 5: ADC right muted */188 0x04, 0x80, /* 4: ADC IPGA gain 0dB */189 0x05, 0x80, /* 5: ADC IPGA gain 0dB */190 0x06, 0x00, /* 6: DAC left muted */191 0x07, 0x00, /* 7: DAC right muted */192 0xff, 0xff193 };194 static unsigned char inits_ak4528[] = {195 0x00, 0x07, /* 0: all power up */196 0x01, 0x00, /* 1: ADC/DAC reset */197 0x02, 0x60, /* 2: 24bit I2S */198 0x03, 0x0d, /* 3: deemphasis off, turn LR highpass filters on */199 0x01, 0x03, /* 1: ADC/DAC enable */200 0x04, 0x00, /* 4: ADC left muted */201 0x05, 0x00, /* 5: ADC right muted */202 0xff, 0xff203 };204 static unsigned char inits_ak4529[] = {205 0x09, 0x01, /* 9: ATS=0, RSTN=1 */206 0x0a, 0x3f, /* A: all power up, no zero/overflow detection */207 0x00, 0x0c, /* 0: TDM=0, 24bit I2S, SMUTE=0 */208 0x01, 0x00, /* 1: ACKS=0, ADC, loop off */209 0x02, 0xff, /* 2: LOUT1 muted */210 0x03, 0xff, /* 3: ROUT1 muted */211 0x04, 0xff, /* 4: LOUT2 muted */212 0x05, 0xff, /* 5: ROUT2 muted */213 0x06, 0xff, /* 6: LOUT3 muted */214 0x07, 0xff, /* 7: ROUT3 muted */215 0x0b, 0xff, /* B: LOUT4 muted */216 0x0c, 0xff, /* C: ROUT4 muted */217 0x08, 0x55, /* 8: deemphasis all off */218 0xff, 0xff219 };220 static unsigned char inits_ak4355[] = {221 0x01, 0x02, /* 1: reset and soft-mute */222 0x00, 0x06, /* 0: mode3(i2s), disable auto-clock detect, disable DZF, sharp roll-off, RSTN#=0 */223 // 0x02, 0x0e, /* 2: DA's power up, normal speed, RSTN#=0 */224 0x02, 0x2e,225 0x03, 0x01, /* 3: de-emphasis off */226 0x04, 0x00, /* 4: LOUT1 volume muted */227 0x05, 0x00, /* 5: ROUT1 volume muted */228 0x06, 0x00, /* 6: LOUT2 volume muted */229 0x07, 0x00, /* 7: ROUT2 volume muted */230 0x08, 0x00, /* 8: LOUT3 volume muted */231 0x09, 0x00, /* 9: ROUT3 volume muted */232 0x0a, 0x00, /* a: DATT speed=0, ignore DZF */233 0x01, 0x01, /* 1: un-reset, unmute */234 0xff, 0xff235 };236 static unsigned char inits_ak4381[] = {237 0x00, 0x0c, /* 0: mode3(i2s), disable auto-clock detect */238 // 0x01, 0x02, /* 1: de-emphasis off, normal speed, sharp roll-off, DZF off */239 0x01, 0x12,240 0x02, 0x00, /* 2: DZF disabled */241 0x03, 0x00, /* 3: LATT 0 */242 0x04, 0x00, /* 4: RATT 0 */243 0x00, 0x0f, /* 0: power-up, un-reset */244 0xff, 0xff245 };246 247 int chip, num_chips;248 unsigned char *ptr, reg, data, *inits;249 250 switch (ak->type) {251 case SND_AK4524:252 inits = inits_ak4524;253 num_chips = ak->num_dacs / 2;254 break;255 case SND_AK4528:256 inits = inits_ak4528;257 num_chips = ak->num_dacs / 2;258 break;259 case SND_AK4529:260 inits = inits_ak4529;261 num_chips = 1;262 break;263 case SND_AK4355:264 inits = inits_ak4355;265 num_chips = 1;266 break;267 case SND_AK4381:268 inits = inits_ak4381;269 num_chips = ak->num_dacs / 2;270 break;271 default:272 snd_BUG();273 return;274 }275 276 for (chip = 0; chip < num_chips; chip++) {277 ptr = inits;278 while (*ptr != 0xff) {279 reg = *ptr++;280 data = *ptr++;281 snd_ice1712_akm4xxx_write(ak, chip, reg, data);282 }283 }284 }285 286 126 287 127 /* 288 128 * initialize the akm4xxx_t record with the template 289 129 */ 290 void snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *temp, ice1712_t *ice) 130 int __devinit snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *temp, 131 const struct snd_ak4xxx_private *_priv, ice1712_t *ice) 291 132 { 133 struct snd_ak4xxx_private *priv; 134 135 priv = kmalloc(sizeof(*priv), GFP_KERNEL); 136 if (priv == NULL) 137 return -ENOMEM; 292 138 *ak = *temp; 293 ak->chip = ice; 294 snd_ice1712_akm4xxx_init_chip(ak); 295 } 296 297 298 #define AK_GET_CHIP(val) (((val) >> 8) & 0xff) 299 #define AK_GET_ADDR(val) ((val) & 0xff) 300 #define AK_GET_SHIFT(val) (((val) >> 16) & 0x7f) 301 #define AK_GET_INVERT(val) (((val) >> 23) & 1) 302 #define AK_GET_MASK(val) (((val) >> 24) & 0xff) 303 #define AK_COMPOSE(chip,addr,shift,mask) (((chip) << 8) | (addr) | ((shift) << 16) | ((mask) << 24)) 304 #define AK_INVERT (1<<23) 305 306 static int snd_ice1712_akm4xxx_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 307 { 308 unsigned int mask = AK_GET_MASK(kcontrol->private_value); 309 310 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 311 uinfo->count = 1; 312 uinfo->value.integer.min = 0; 313 uinfo->value.integer.max = mask; 139 ak->card = ice->card; 140 *priv = *_priv; 141 ak->private_value[0] = (unsigned long)priv; 142 ak->private_data[0] = ice; 143 if (ak->ops.lock == NULL) 144 ak->ops.lock = snd_ice1712_akm4xxx_lock; 145 if (ak->ops.unlock == NULL) 146 ak->ops.unlock = snd_ice1712_akm4xxx_unlock; 147 if (ak->ops.write == NULL) 148 ak->ops.write = snd_ice1712_akm4xxx_write; 149 snd_akm4xxx_init(ak); 314 150 return 0; 315 151 } 316 152 317 static int snd_ice1712_akm4xxx_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)153 void __devexit snd_ice1712_akm4xxx_free(ice1712_t *ice) 318 154 { 319 akm4xxx_t *ak = _snd_kcontrol_chip(kcontrol); 320 int chip = AK_GET_CHIP(kcontrol->private_value); 321 int addr = AK_GET_ADDR(kcontrol->private_value); 322 int invert = AK_GET_INVERT(kcontrol->private_value); 323 unsigned int mask = AK_GET_MASK(kcontrol->private_value); 324 unsigned char val = ak->images[chip][addr]; 325 326 ucontrol->value.integer.value[0] = invert ? mask - val : val; 327 return 0; 328 } 329 330 static int snd_ice1712_akm4xxx_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 331 { 332 akm4xxx_t *ak = _snd_kcontrol_chip(kcontrol); 333 int chip = AK_GET_CHIP(kcontrol->private_value); 334 int addr = AK_GET_ADDR(kcontrol->private_value); 335 int invert = AK_GET_INVERT(kcontrol->private_value); 336 unsigned int mask = AK_GET_MASK(kcontrol->private_value); 337 unsigned char nval = ucontrol->value.integer.value[0] % (mask+1); 338 int change; 339 340 if (invert) 341 nval = mask - nval; 342 change = ak->images[chip][addr] != nval; 343 if (change) 344 snd_ice1712_akm4xxx_write(ak, chip, addr, nval); 345 return change; 346 } 347 348 static int snd_ice1712_akm4xxx_ipga_gain_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 349 { 350 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 351 uinfo->count = 1; 352 uinfo->value.integer.min = 0; 353 uinfo->value.integer.max = 36; 354 return 0; 355 } 356 357 static int snd_ice1712_akm4xxx_ipga_gain_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 358 { 359 akm4xxx_t *ak = _snd_kcontrol_chip(kcontrol); 360 int chip = AK_GET_CHIP(kcontrol->private_value); 361 int addr = AK_GET_ADDR(kcontrol->private_value); 362 ucontrol->value.integer.value[0] = ak->ipga_gain[chip][addr-4] & 0x7f; 363 return 0; 364 } 365 366 static int snd_ice1712_akm4xxx_ipga_gain_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 367 { 368 akm4xxx_t *ak = _snd_kcontrol_chip(kcontrol); 369 int chip = AK_GET_CHIP(kcontrol->private_value); 370 int addr = AK_GET_ADDR(kcontrol->private_value); 371 unsigned char nval = (ucontrol->value.integer.value[0] % 37) | 0x80; 372 int change = ak->ipga_gain[chip][addr] != nval; 373 if (change) 374 snd_ice1712_akm4xxx_write(ak, chip, addr, nval); 375 return change; 376 } 377 378 static int snd_ice1712_akm4xxx_deemphasis_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 379 { 380 static char *texts[4] = { 381 "44.1kHz", "Off", "48kHz", "32kHz", 382 }; 383 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 384 uinfo->count = 1; 385 uinfo->value.enumerated.items = 4; 386 if (uinfo->value.enumerated.item >= 4) 387 uinfo->value.enumerated.item = 3; 388 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 389 return 0; 390 } 391 392 static int snd_ice1712_akm4xxx_deemphasis_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol) 393 { 394 akm4xxx_t *ak = _snd_kcontrol_chip(kcontrol); 395 int chip = AK_GET_CHIP(kcontrol->private_value); 396 int addr = AK_GET_ADDR(kcontrol->private_value); 397 int shift = AK_GET_SHIFT(kcontrol->private_value); 398 ucontrol->value.enumerated.item[0] = (ak->images[chip][addr] >> shift) & 3; 399 return 0; 400 } 401 402 static int snd_ice1712_akm4xxx_deemphasis_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 403 { 404 akm4xxx_t *ak = _snd_kcontrol_chip(kcontrol); 405 int chip = AK_GET_CHIP(kcontrol->private_value); 406 int addr = AK_GET_ADDR(kcontrol->private_value); 407 int shift = AK_GET_SHIFT(kcontrol->private_value); 408 unsigned char nval = ucontrol->value.enumerated.item[0] & 3; 409 int change; 410 411 nval = (nval << shift) | (ak->images[chip][addr] & ~(3 << shift)); 412 change = ak->images[chip][addr] != nval; 413 if (change) 414 snd_ice1712_akm4xxx_write(ak, chip, addr, nval); 415 return change; 155 unsigned int akidx; 156 if (ice->akm == NULL) 157 return; 158 for (akidx = 0; akidx < ice->akm_codecs; akidx++) { 159 akm4xxx_t *ak = &ice->akm[akidx]; 160 if (ak->private_value[0]) 161 kfree((void *)ak->private_value[0]); 162 } 163 kfree(ice->akm); 416 164 } 417 165 418 166 /* 419 * build AK4 524controls167 * build AK4xxx controls 420 168 */ 421 422 169 int __devinit snd_ice1712_akm4xxx_build_controls(ice1712_t *ice) 423 170 { 424 unsigned int idx;171 unsigned int akidx; 425 172 int err; 426 unsigned int akidx;427 173 428 174 for (akidx = 0; akidx < ice->akm_codecs; akidx++) { 429 175 akm4xxx_t *ak = &ice->akm[akidx]; 430 for (idx = 0; idx < ak->num_dacs; ++idx) { 431 snd_kcontrol_t ctl; 432 memset(&ctl, 0, sizeof(ctl)); 433 strcpy(ctl.id.name, "DAC Volume"); 434 ctl.id.index = idx + ak->idx_offset * 2; 435 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 436 ctl.info = snd_ice1712_akm4xxx_volume_info; 437 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 438 ctl.get = snd_ice1712_akm4xxx_volume_get; 439 ctl.put = snd_ice1712_akm4xxx_volume_put; 440 switch (ak->type) { 441 case SND_AK4524: 442 ctl.private_value = AK_COMPOSE(idx/2, (idx%2) + 6, 0, 127); /* register 6 & 7 */ 443 break; 444 case SND_AK4528: 445 ctl.private_value = AK_COMPOSE(idx/2, (idx%2) + 4, 0, 127); /* register 4 & 5 */ 446 break; 447 case SND_AK4529: { 448 int val = idx < 6 ? idx + 2 : (idx - 6) + 0xb; /* registers 2-7 and b,c */ 449 ctl.private_value = AK_COMPOSE(0, val, 0, 255) | AK_INVERT; 450 break; 451 } 452 case SND_AK4355: 453 ctl.private_value = AK_COMPOSE(0, idx + 4, 0, 255); /* register 4-9, chip #0 only */ 454 break; 455 case SND_AK4381: 456 ctl.private_value = AK_COMPOSE(idx/2, (idx%2) + 3, 0, 255); /* register 3 & 4 */ 457 break; 458 default: 459 return -EINVAL; 460 } 461 ctl.private_data = ak; 462 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0) 463 return err; 464 } 465 for (idx = 0; idx < ak->num_adcs && ak->type == SND_AK4524; ++idx) { 466 snd_kcontrol_t ctl; 467 memset(&ctl, 0, sizeof(ctl)); 468 strcpy(ctl.id.name, "ADC Volume"); 469 ctl.id.index = idx; 470 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 471 ctl.info = snd_ice1712_akm4xxx_volume_info; 472 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 473 ctl.get = snd_ice1712_akm4xxx_volume_get; 474 ctl.put = snd_ice1712_akm4xxx_volume_put; 475 ctl.private_value = AK_COMPOSE(idx/2, (idx%2) + 4, 0, 127); /* register 4 & 5 */ 476 ctl.private_data = ak; 477 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0) 478 return err; 479 memset(&ctl, 0, sizeof(ctl)); 480 strcpy(ctl.id.name, "IPGA Analog Capture Volume"); 481 ctl.id.index = idx; 482 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 483 ctl.info = snd_ice1712_akm4xxx_ipga_gain_info; 484 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 485 ctl.get = snd_ice1712_akm4xxx_ipga_gain_get; 486 ctl.put = snd_ice1712_akm4xxx_ipga_gain_put; 487 ctl.private_value = AK_COMPOSE(idx/2, (idx%2) + 4, 0, 0); /* register 4 & 5 */ 488 ctl.private_data = ak; 489 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0) 490 return err; 491 } 492 for (idx = 0; idx < ak->num_dacs/2; idx++) { 493 snd_kcontrol_t ctl; 494 memset(&ctl, 0, sizeof(ctl)); 495 strcpy(ctl.id.name, "Deemphasis"); 496 ctl.id.index = idx + ak->idx_offset; 497 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 498 ctl.info = snd_ice1712_akm4xxx_deemphasis_info; 499 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 500 ctl.get = snd_ice1712_akm4xxx_deemphasis_get; 501 ctl.put = snd_ice1712_akm4xxx_deemphasis_put; 502 switch (ak->type) { 503 case SND_AK4524: 504 case SND_AK4528: 505 ctl.private_value = AK_COMPOSE(idx, 3, 0, 0); /* register 3 */ 506 break; 507 case SND_AK4529: { 508 int shift = idx == 3 ? 6 : (2 - idx) * 2; 509 ctl.private_value = AK_COMPOSE(0, 8, shift, 0); /* register 8 with shift */ 510 break; 511 } 512 case SND_AK4355: 513 ctl.private_value = AK_COMPOSE(idx, 3, 0, 0); 514 break; 515 case SND_AK4381: 516 ctl.private_value = AK_COMPOSE(idx, 1, 1, 0); 517 break; 518 } 519 ctl.private_data = ak; 520 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0) 521 return err; 522 } 176 err = snd_akm4xxx_build_controls(ak); 177 if (err < 0) 178 return err; 523 179 } 524 180 return 0; 525 181 } 526 527 -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/delta.c
r224 r246 233 233 * AK4524 on Delta 44 and 66 to choose the chip mask 234 234 */ 235 static int delta_ak4524_start(akm4xxx_t *ak, int chip) 236 { 237 snd_ice1712_save_gpio_status(ak->chip); 238 ak->cs_mask = 239 ak->cs_addr = chip == 0 ? ICE1712_DELTA_CODEC_CHIP_A : 240 ICE1712_DELTA_CODEC_CHIP_B; 241 return 0; 235 static void delta_ak4524_lock(akm4xxx_t *ak, int chip) 236 { 237 struct snd_ak4xxx_private *priv = (void *)ak->private_value[0]; 238 ice1712_t *ice = ak->private_data[0]; 239 240 snd_ice1712_save_gpio_status(ice); 241 priv->cs_mask = 242 priv->cs_addr = chip == 0 ? ICE1712_DELTA_CODEC_CHIP_A : 243 ICE1712_DELTA_CODEC_CHIP_B; 242 244 } 243 245 … … 245 247 * AK4524 on Delta1010LT to choose the chip address 246 248 */ 247 static int delta1010lt_ak4524_start(akm4xxx_t *ak, int chip) 248 { 249 snd_ice1712_save_gpio_status(ak->chip); 250 ak->cs_mask = ICE1712_DELTA_1010LT_CS; 251 ak->cs_addr = chip << 4; 252 return 0; 249 static void delta1010lt_ak4524_lock(akm4xxx_t *ak, int chip) 250 { 251 struct snd_ak4xxx_private *priv = (void *)ak->private_value[0]; 252 ice1712_t *ice = ak->private_data[0]; 253 254 snd_ice1712_save_gpio_status(ice); 255 priv->cs_mask = ICE1712_DELTA_1010LT_CS; 256 priv->cs_addr = chip << 4; 253 257 } 254 258 … … 259 263 { 260 264 unsigned char tmp, tmp2; 261 ice1712_t *ice = ak-> chip;265 ice1712_t *ice = ak->private_data[0]; 262 266 263 267 if (rate == 0) /* no hint - S/PDIF input is master, simply return */ … … 276 280 277 281 /* do it again */ 278 snd_ ice1712_akm4xxx_reset(ak, 1);282 snd_akm4xxx_reset(ak, 1); 279 283 down(&ice->gpio_mutex); 280 284 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ~ICE1712_DELTA_DFS; … … 283 287 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); 284 288 up(&ice->gpio_mutex); 285 snd_ ice1712_akm4xxx_reset(ak, 0);289 snd_akm4xxx_reset(ak, 0); 286 290 } 287 291 … … 331 335 .num_adcs = 2, 332 336 .num_dacs = 2, 337 .ops = { 338 .set_rate_val = delta_ak4524_set_rate_val 339 } 340 }; 341 342 static struct snd_ak4xxx_private akm_audiophile_priv __devinitdata = { 333 343 .caddr = 2, 334 344 .cif = 0, … … 340 350 .add_flags = ICE1712_DELTA_AP_CS_DIGITAL, 341 351 .mask_flags = 0, 342 .ops = {343 .set_rate_val = delta_ak4524_set_rate_val344 }345 352 }; 346 353 … … 349 356 .num_adcs = 2, 350 357 .num_dacs = 8, 358 .ops = { 359 .set_rate_val = delta_ak4524_set_rate_val 360 } 361 }; 362 363 static struct snd_ak4xxx_private akm_delta410_priv __devinitdata = { 351 364 .caddr = 0, 352 365 .cif = 0, … … 358 371 .add_flags = ICE1712_DELTA_AP_CS_DIGITAL, 359 372 .mask_flags = 0, 360 .ops = {361 .set_rate_val = delta_ak4524_set_rate_val362 }363 373 }; 364 374 … … 367 377 .num_adcs = 8, 368 378 .num_dacs = 8, 379 .ops = { 380 .lock = delta1010lt_ak4524_lock, 381 .set_rate_val = delta_ak4524_set_rate_val 382 } 383 }; 384 385 static struct snd_ak4xxx_private akm_delta1010lt_priv __devinitdata = { 369 386 .caddr = 2, 370 387 .cif = 0, /* the default level of the CIF pin from AK4524 */ … … 376 393 .add_flags = 0, 377 394 .mask_flags = 0, 378 .ops = {379 .start = delta1010lt_ak4524_start,380 .set_rate_val = delta_ak4524_set_rate_val381 }382 395 }; 383 396 … … 386 399 .num_adcs = 4, 387 400 .num_dacs = 4, 401 .ops = { 402 .lock = delta_ak4524_lock, 403 .set_rate_val = delta_ak4524_set_rate_val 404 } 405 }; 406 407 static struct snd_ak4xxx_private akm_delta44_priv __devinitdata = { 388 408 .caddr = 2, 389 409 .cif = 0, /* the default level of the CIF pin from AK4524 */ … … 395 415 .add_flags = 0, 396 416 .mask_flags = 0, 397 .ops = {398 .start = delta_ak4524_start,399 .set_rate_val = delta_ak4524_set_rate_val400 }401 417 }; 402 418 … … 467 483 switch (ice->eeprom.subvendor) { 468 484 case ICE1712_SUBDEVICE_AUDIOPHILE: 469 snd_ice1712_akm4xxx_init(ak, &akm_audiophile, ice);485 err = snd_ice1712_akm4xxx_init(ak, &akm_audiophile, &akm_audiophile_priv, ice); 470 486 break; 471 487 case ICE1712_SUBDEVICE_DELTA410: 472 snd_ice1712_akm4xxx_init(ak, &akm_delta410, ice);488 err = snd_ice1712_akm4xxx_init(ak, &akm_delta410, &akm_delta410_priv, ice); 473 489 break; 474 490 case ICE1712_SUBDEVICE_DELTA1010LT: 475 snd_ice1712_akm4xxx_init(ak, &akm_delta1010lt, ice);491 err = snd_ice1712_akm4xxx_init(ak, &akm_delta1010lt, &akm_delta1010lt_priv, ice); 476 492 break; 477 493 case ICE1712_SUBDEVICE_DELTA66: 478 494 case ICE1712_SUBDEVICE_DELTA44: 479 snd_ice1712_akm4xxx_init(ak, &akm_delta44, ice);495 err = snd_ice1712_akm4xxx_init(ak, &akm_delta44, &akm_delta44_priv, ice); 480 496 break; 481 497 default: … … 484 500 } 485 501 486 return 0;502 return err; 487 503 } 488 504 … … 535 551 case ICE1712_SUBDEVICE_DELTADIO2496: 536 552 case ICE1712_SUBDEVICE_DELTA66: 537 case ICE1712_SUBDEVICE_AUDIOPHILE:538 case ICE1712_SUBDEVICE_DELTA410:539 case ICE1712_SUBDEVICE_DELTA1010LT:540 553 err = snd_ice1712_spdif_build_controls(ice); 541 554 if (err < 0) -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ews.c
r224 r246 156 156 157 157 /* start callback for EWS88MT, needs to select a certain chip mask */ 158 static int ews88mt_ak4524_start(akm4xxx_t *ak, int chip)159 { 160 ice1712_t *ice = ak-> chip;158 static void ews88mt_ak4524_lock(akm4xxx_t *ak, int chip) 159 { 160 ice1712_t *ice = ak->private_data[0]; 161 161 unsigned char tmp; 162 162 /* assert AK4524 CS */ 163 163 if (snd_ice1712_ews88mt_chip_select(ice, ~(1 << chip) & 0x0f) < 0) 164 return -EINVAL;164 snd_printk(KERN_ERR "fatal error (ews88mt chip select)\n"); 165 165 snd_ice1712_save_gpio_status(ice); 166 166 tmp = ICE1712_EWS88_SERIAL_DATA | … … 170 170 ice->gpio.direction | tmp); 171 171 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~tmp); 172 return 0;173 172 } 174 173 175 174 /* stop callback for EWS88MT, needs to deselect chip mask */ 176 static void ews88mt_ak4524_ stop(akm4xxx_t *ak)177 { 178 ice1712_t *ice = ak-> chip;175 static void ews88mt_ak4524_unlock(akm4xxx_t *ak, int chip) 176 { 177 ice1712_t *ice = ak->private_data[0]; 179 178 snd_ice1712_restore_gpio_status(ice); 180 179 udelay(1); … … 183 182 184 183 /* start callback for EWX24/96 */ 185 static int ewx2496_ak4524_start(akm4xxx_t *ak, int chip)186 { 187 ice1712_t *ice = ak-> chip;184 static void ewx2496_ak4524_lock(akm4xxx_t *ak, int chip) 185 { 186 ice1712_t *ice = ak->private_data[0]; 188 187 unsigned char tmp; 189 188 snd_ice1712_save_gpio_status(ice); … … 195 194 ice->gpio.direction | tmp); 196 195 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~tmp); 197 return 0;198 196 } 199 197 200 198 /* start callback for DMX 6fire */ 201 static int dmx6fire_ak4524_start(akm4xxx_t *ak, int chip) 202 { 203 ice1712_t *ice = ak->chip; 199 static void dmx6fire_ak4524_lock(akm4xxx_t *ak, int chip) 200 { 201 struct snd_ak4xxx_private *priv = (void *)ak->private_value[0]; 202 ice1712_t *ice = ak->private_data[0]; 204 203 unsigned char tmp; 205 204 snd_ice1712_save_gpio_status(ice); 206 tmp = ak->cs_mask = ak->cs_addr = (1 << chip) & ICE1712_6FIRE_AK4524_CS_MASK;205 tmp = priv->cs_mask = priv->cs_addr = (1 << chip) & ICE1712_6FIRE_AK4524_CS_MASK; 207 206 tmp |= ICE1712_6FIRE_SERIAL_DATA | 208 207 ICE1712_6FIRE_SERIAL_CLOCK | … … 211 210 ice->gpio.direction | tmp); 212 211 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~tmp); 213 return 0; 214 } 215 212 } 216 213 217 214 /* … … 329 326 .num_dacs = 8, 330 327 .type = SND_AK4524, 328 .ops = { 329 .lock = ews88mt_ak4524_lock, 330 .unlock = ews88mt_ak4524_unlock 331 } 332 }; 333 334 static struct snd_ak4xxx_private akm_ews88mt_priv __devinitdata = { 331 335 .caddr = 2, 332 336 .cif = 1, /* CIF high */ … … 338 342 .add_flags = ICE1712_EWS88_RW, /* set rw bit high */ 339 343 .mask_flags = 0, 340 .ops = {341 .start = ews88mt_ak4524_start,342 .stop = ews88mt_ak4524_stop343 }344 344 }; 345 345 … … 348 348 .num_dacs = 2, 349 349 .type = SND_AK4524, 350 .ops = { 351 .lock = ewx2496_ak4524_lock 352 } 353 }; 354 355 static struct snd_ak4xxx_private akm_ewx2496_priv __devinitdata = { 350 356 .caddr = 2, 351 357 .cif = 1, /* CIF high */ … … 357 363 .add_flags = ICE1712_EWS88_RW, /* set rw bit high */ 358 364 .mask_flags = 0, 359 .ops = {360 .start = ewx2496_ak4524_start361 }362 365 }; 363 366 … … 366 369 .num_dacs = 6, 367 370 .type = SND_AK4524, 371 .ops = { 372 .lock = dmx6fire_ak4524_lock 373 } 374 }; 375 376 static struct snd_ak4xxx_private akm_6fire_priv __devinitdata = { 368 377 .caddr = 2, 369 378 .cif = 1, /* CIF high */ … … 375 384 .add_flags = ICE1712_6FIRE_RW, /* set rw bit high */ 376 385 .mask_flags = 0, 377 .ops = { 378 .start = dmx6fire_ak4524_start 379 } 380 }; 381 386 }; 382 387 383 388 /* … … 480 485 case ICE1712_SUBDEVICE_EWS88MT: 481 486 case ICE1712_SUBDEVICE_EWS88MT_NEW: 482 snd_ice1712_akm4xxx_init(ak, &akm_ews88mt, ice);487 err = snd_ice1712_akm4xxx_init(ak, &akm_ews88mt, &akm_ews88mt_priv, ice); 483 488 break; 484 489 case ICE1712_SUBDEVICE_EWX2496: 485 snd_ice1712_akm4xxx_init(ak, &akm_ewx2496, ice);490 err = snd_ice1712_akm4xxx_init(ak, &akm_ewx2496, &akm_ewx2496_priv, ice); 486 491 break; 487 492 case ICE1712_SUBDEVICE_DMX6FIRE: 488 snd_ice1712_akm4xxx_init(ak, &akm_6fire, ice); 489 break; 490 } 491 492 return 0; 493 err = snd_ice1712_akm4xxx_init(ak, &akm_6fire, &akm_6fire_priv, ice); 494 break; 495 default: 496 err = 0; 497 } 498 499 return err; 493 500 } 494 501 … … 603 610 { 604 611 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 605 int channel = kcontrol->id.index;612 int channel = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 606 613 unsigned char data; 607 614 … … 622 629 { 623 630 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 624 int channel = kcontrol->id.index;631 int channel = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 625 632 unsigned char data, ndata; 626 633 … … 646 653 .get = snd_ice1712_ews88mt_input_sense_get, 647 654 .put = snd_ice1712_ews88mt_input_sense_put, 655 .count = 8, 648 656 }; 649 657 … … 895 903 unsigned int idx; 896 904 int err; 897 snd_kcontrol_t *kctl;898 905 899 /* all terratec cards have spdif */ 900 err = snd_ice1712_spdif_build_controls(ice); 901 if (err < 0) 902 return err; 906 /* all terratec cards have spdif, but cs8427 module builds it's own controls */ 907 if (ice->cs8427 == NULL) { 908 err = snd_ice1712_spdif_build_controls(ice); 909 if (err < 0) 910 return err; 911 } 903 912 904 913 /* ak4524 controls */ … … 925 934 case ICE1712_SUBDEVICE_EWS88MT: 926 935 case ICE1712_SUBDEVICE_EWS88MT_NEW: 927 for (idx = 0; idx < 8; idx++) { 928 kctl = snd_ctl_new1(&snd_ice1712_ews88mt_input_sense, ice); 929 kctl->id.index = idx; 930 err = snd_ctl_add(ice->card, kctl); 931 if (err < 0) 932 return err; 933 } 936 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88mt_input_sense, ice)); 937 if (err < 0) 938 return err; 934 939 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88mt_output_sense, ice)); 935 940 if (err < 0) -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ice1712.c
r231 r246 119 119 120 120 /* 121 * AK4xxx stuff 122 */ 123 124 #include "ak4xxx.c" 125 126 /* 121 127 * Basic I/O 122 128 */ … … 399 405 */ 400 406 401 static voidsnd_ice1712_interrupt(int irq, void *dev_id, struct pt_regs *regs)402 { 403 ice1712_t *ice = snd_magic_cast(ice1712_t, dev_id, return );407 static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id, struct pt_regs *regs) 408 { 409 ice1712_t *ice = snd_magic_cast(ice1712_t, dev_id, return IRQ_NONE); 404 410 unsigned char status; 411 int handled = 0; 405 412 406 413 while (1) { … … 408 415 if (status == 0) 409 416 break; 417 handled = 1; 410 418 if (status & ICE1712_IRQ_MPU1) { 411 419 if (ice->rmidi[0]) … … 463 471 } 464 472 } 473 return IRQ_RETVAL(handled); 465 474 } 466 475 … … 963 972 unsigned int what = 0; 964 973 unsigned int old; 965 snd_pcm_substream_t *s = substream; 966 967 do { 974 struct list_head *pos; 975 snd_pcm_substream_t *s; 976 977 snd_pcm_group_for_each(pos, substream) { 978 s = snd_pcm_group_substream_entry(pos); 968 979 if (s == ice->playback_pro_substream) { 969 980 what |= ICE1712_PLAYBACK_START; … … 973 984 snd_pcm_trigger_done(s, substream); 974 985 } 975 s = s->link_next; 976 } while (s != substream); 986 } 977 987 spin_lock(&ice->reg_lock); 978 988 old = inl(ICEMT(ice, PLAYBACK_CONTROL)); … … 1297 1307 { 1298 1308 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1299 int index = kcontrol->private_value;1309 int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value; 1300 1310 1301 1311 spin_lock_irq(&ice->reg_lock); … … 1309 1319 { 1310 1320 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1311 int index = kcontrol->private_value;1321 int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value; 1312 1322 unsigned int nval, change; 1313 1323 … … 1335 1345 { 1336 1346 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1337 int index = kcontrol->private_value;1347 int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value; 1338 1348 1339 1349 spin_lock_irq(&ice->reg_lock); … … 1347 1357 { 1348 1358 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1349 int index = kcontrol->private_value;1359 int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value; 1350 1360 unsigned int nval, change; 1351 1361 … … 1362 1372 1363 1373 1374 static snd_kcontrol_new_t snd_ice1712_multi_ctrls[] __devinitdata = { 1375 { 1376 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1377 .name = "Multi Playback Switch", 1378 .info = snd_ice1712_pro_mixer_switch_info, 1379 .get = snd_ice1712_pro_mixer_switch_get, 1380 .put = snd_ice1712_pro_mixer_switch_put, 1381 .private_value = 0, 1382 .count = 10, 1383 }, 1384 { 1385 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1386 .name = "Multi Playback Volume", 1387 .info = snd_ice1712_pro_mixer_volume_info, 1388 .get = snd_ice1712_pro_mixer_volume_get, 1389 .put = snd_ice1712_pro_mixer_volume_put, 1390 .private_value = 0, 1391 .count = 10, 1392 }, 1393 { 1394 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1395 .name = "Multi Capture Switch", 1396 .info = snd_ice1712_pro_mixer_switch_info, 1397 .get = snd_ice1712_pro_mixer_switch_get, 1398 .put = snd_ice1712_pro_mixer_switch_put, 1399 .private_value = 10, 1400 .count = 10, 1401 }, 1402 { 1403 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1404 .name = "Multi Capture Volume", 1405 .info = snd_ice1712_pro_mixer_volume_info, 1406 .get = snd_ice1712_pro_mixer_volume_get, 1407 .put = snd_ice1712_pro_mixer_volume_put, 1408 .private_value = 10, 1409 .count = 10, 1410 }, 1411 }; 1412 1364 1413 static int __devinit snd_ice1712_build_pro_mixer(ice1712_t *ice) 1365 1414 { 1366 1415 snd_card_t * card = ice->card; 1367 snd_kcontrol_t ctl; 1368 int idx, err; 1369 1370 /* PCM playback */ 1371 for (idx = 0; idx < 10; idx++) { 1372 memset(&ctl, 0, sizeof(ctl)); 1373 strcpy(ctl.id.name, "Multi Playback Switch"); 1374 ctl.id.index = idx; 1375 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1376 ctl.info = snd_ice1712_pro_mixer_switch_info; 1377 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 1378 ctl.get = snd_ice1712_pro_mixer_switch_get; 1379 ctl.put = snd_ice1712_pro_mixer_switch_put; 1380 ctl.private_value = idx; 1381 ctl.private_data = ice; 1382 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0) 1383 return err; 1384 memset(&ctl, 0, sizeof(ctl)); 1385 strcpy(ctl.id.name, "Multi Playback Volume"); 1386 ctl.id.index = idx; 1387 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1388 ctl.info = snd_ice1712_pro_mixer_volume_info; 1389 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 1390 ctl.get = snd_ice1712_pro_mixer_volume_get; 1391 ctl.put = snd_ice1712_pro_mixer_volume_put; 1392 ctl.private_value = idx; 1393 ctl.private_data = ice; 1394 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0) 1395 return err; 1396 } 1397 1398 /* PCM capture */ 1399 for (idx = 0; idx < 10; idx++) { 1400 memset(&ctl, 0, sizeof(ctl)); 1401 strcpy(ctl.id.name, "Multi Capture Switch"); 1402 ctl.id.index = idx; 1403 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1404 ctl.info = snd_ice1712_pro_mixer_switch_info; 1405 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 1406 ctl.get = snd_ice1712_pro_mixer_switch_get; 1407 ctl.put = snd_ice1712_pro_mixer_switch_put; 1408 ctl.private_value = idx + 10; 1409 ctl.private_data = ice; 1410 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0) 1411 return err; 1412 memset(&ctl, 0, sizeof(ctl)); 1413 strcpy(ctl.id.name, "Multi Capture Volume"); 1414 ctl.id.index = idx; 1415 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1416 ctl.info = snd_ice1712_pro_mixer_volume_info; 1417 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE; 1418 ctl.get = snd_ice1712_pro_mixer_volume_get; 1419 ctl.put = snd_ice1712_pro_mixer_volume_put; 1420 ctl.private_value = idx + 10; 1421 ctl.private_data = ice; 1422 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0) 1416 unsigned int idx; 1417 int err; 1418 1419 /* multi-channel mixer */ 1420 for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_ctrls); idx++) { 1421 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_ctrls[idx], ice)); 1422 if (err < 0) 1423 1423 return err; 1424 1424 } … … 1909 1909 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1910 1910 uinfo->count = 1; 1911 uinfo->value.enumerated.items = kcontrol->id.index< 2 ? 12 : 11;1911 uinfo->value.enumerated.items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11; 1912 1912 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1913 1913 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; … … 1919 1919 { 1920 1920 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1921 int idx = kcontrol->id.index;1921 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1922 1922 unsigned int val, cval; 1923 1923 … … 1945 1945 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1946 1946 int change, shift; 1947 int idx = kcontrol->id.index;1947 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1948 1948 unsigned int val, old_val, nval; 1949 1949 … … 1993 1993 { 1994 1994 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1995 int idx = kcontrol->id.index;1995 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1996 1996 unsigned int val, cval; 1997 1997 val = inw(ICEMT(ice, ROUTE_SPDOUT)); … … 2013 2013 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 2014 2014 int change, shift; 2015 int idx = kcontrol->id.index;2015 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 2016 2016 unsigned int val, old_val, nval; 2017 2017 … … 2061 2061 .get = snd_ice1712_pro_route_spdif_get, 2062 2062 .put = snd_ice1712_pro_route_spdif_put, 2063 .count = 2, 2063 2064 }; 2064 2065 … … 2247 2248 static int __devinit snd_ice1712_build_controls(ice1712_t *ice) 2248 2249 { 2249 unsigned int idx;2250 snd_kcontrol_t *kctl;2251 2250 int err; 2252 2251 … … 2265 2264 return err; 2266 2265 2267 for (idx = 0; idx < ice->num_total_dacs; idx++) { 2268 kctl = snd_ctl_new1(&snd_ice1712_mixer_pro_analog_route, ice); 2269 if (kctl == NULL) 2270 return -ENOMEM; 2271 kctl->id.index = idx; 2272 err = snd_ctl_add(ice->card, kctl); 2266 if (ice->num_total_dacs > 0) { 2267 snd_kcontrol_new_t tmp = snd_ice1712_mixer_pro_analog_route; 2268 tmp.count = ice->num_total_dacs; 2269 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice)); 2273 2270 if (err < 0) 2274 2271 return err; 2275 2272 } 2276 2273 2277 for (idx = 0; idx < 2; idx++) { 2278 kctl = snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice); 2279 if (kctl == NULL) 2280 return -ENOMEM; 2281 kctl->id.index = idx; 2282 err = snd_ctl_add(ice->card, kctl); 2283 if (err < 0) 2284 return err; 2285 } 2274 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice)); 2275 if (err < 0) 2276 return err; 2286 2277 2287 2278 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice)); … … 2324 2315 kfree_nocheck(ice->res_profi_port); 2325 2316 } 2326 if (ice->akm) 2327 kfree(ice->akm); 2317 snd_ice1712_akm4xxx_free(ice); 2328 2318 snd_magic_kfree(ice); 2329 2319 return 0; -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ice1712.h
r224 r246 27 27 #include <sound/rawmidi.h> 28 28 #include <sound/i2c.h> 29 #include <sound/ak4xxx-adda.h> 29 30 #include <sound/pcm.h> 30 31 … … 215 216 216 217 typedef struct _snd_ice1712 ice1712_t; 217 typedef struct snd_ak4xxx akm4xxx_t;218 218 219 219 typedef struct { … … 255 255 256 256 257 struct snd_ak4xxx { 258 unsigned int num_adcs; /* AK4524 or AK4528 ADCs */ 259 unsigned int num_dacs; /* AK4524 or AK4528 DACs */ 260 unsigned char images[4][16]; /* saved register image */ 261 unsigned char ipga_gain[4][2]; /* saved register image for IPGA (AK4528) */ 262 ice1712_t *chip; 263 /* template should fill the following fields */ 264 unsigned int idx_offset; /* control index offset */ 265 enum { 266 SND_AK4524, SND_AK4528, SND_AK4529, SND_AK4355, SND_AK4381 267 } type; 257 struct snd_ak4xxx_private { 268 258 unsigned int cif: 1; /* CIF mode */ 269 259 unsigned char caddr; /* C0 and C1 bits */ … … 276 266 unsigned int mask_flags; /* total mask bits */ 277 267 struct snd_akm4xxx_ops { 278 int (*start)(akm4xxx_t *ak, int chip);279 void (*stop)(akm4xxx_t *ak);280 268 void (*set_rate_val)(akm4xxx_t *ak, unsigned int rate); 281 269 } ops; … … 440 428 int snd_ice1712_spdif_build_controls(ice1712_t *ice); 441 429 442 void snd_ice1712_akm4xxx_write(akm4xxx_t *ice, int chip, unsigned char addr, unsigned char data); 443 void snd_ice1712_akm4xxx_reset(akm4xxx_t *ice, int state); 444 void snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *template, ice1712_t *ice); 430 int snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *template, const struct snd_ak4xxx_private *priv, ice1712_t *ice); 431 void snd_ice1712_akm4xxx_free(ice1712_t *ice); 445 432 int snd_ice1712_akm4xxx_build_controls(ice1712_t *ice); 446 433 -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/ice1724.c
r231 r246 89 89 90 90 /* 91 * AK4xxx stuff 92 */ 93 94 #include "ak4xxx.c" 95 96 /* 91 97 * Basic I/O 92 98 */ … … 195 201 */ 196 202 197 static voidsnd_vt1724_interrupt(int irq, void *dev_id, struct pt_regs *regs)198 { 199 ice1712_t *ice = snd_magic_cast(ice1712_t, dev_id, return );203 static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id, struct pt_regs *regs) 204 { 205 ice1712_t *ice = snd_magic_cast(ice1712_t, dev_id, return IRQ_NONE); 200 206 unsigned char status; 207 int handled = 0; 201 208 202 209 while (1) { … … 204 211 if (status == 0) 205 212 break; 206 213 214 handled = 1; 207 215 /* these should probably be separated at some point, 208 216 but as we don't currently have MPU support on the board I will leave it */ … … 243 251 } 244 252 } 253 return IRQ_RETVAL(handled); 245 254 } 246 255 … … 282 291 unsigned int what; 283 292 unsigned int old; 293 struct list_head *pos; 284 294 snd_pcm_substream_t *s; 285 295 … … 288 298 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 289 299 what = 0; 290 s = substream;291 do {300 snd_pcm_group_for_each(pos, substream) { 301 s = snd_pcm_group_substream_entry(pos); 292 302 if (s == ice->playback_pro_substream) 293 303 what |= VT1724_PDMA0_PAUSE; … … 298 308 else if (s == ice->capture_con_substream) 299 309 what |= VT1724_RDMA1_PAUSE; 300 s = s->link_next; 301 } while (s != substream); 310 } 302 311 spin_lock(&ice->reg_lock); 303 312 old = inl(ICEMT1724(ice, DMA_PAUSE)); … … 314 323 what = 0; 315 324 s = substream; 316 do { 325 snd_pcm_group_for_each(pos, substream) { 326 s = snd_pcm_group_substream_entry(pos); 317 327 if (s == ice->playback_pro_substream) { 318 328 what |= VT1724_PDMA0_START; … … 328 338 snd_pcm_trigger_done(s, substream); 329 339 } 330 s = s->link_next; 331 } while (s != substream); 340 } 332 341 spin_lock(&ice->reg_lock); 333 342 old = inl(ICEMT1724(ice, DMA_CONTROL)); … … 1295 1304 } 1296 1305 1297 static snd_kcontrol_new_t snd_vt1724_pro_internal_clock = __devinitdata{1306 static snd_kcontrol_new_t snd_vt1724_pro_internal_clock __devinitdata = { 1298 1307 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1299 1308 .name = "Multi Track Internal Clock", … … 1450 1459 { 1451 1460 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1452 int idx = kcontrol->id.index;1461 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1453 1462 ucontrol->value.enumerated.item[0] = get_route_val(ice, analog_route_shift(idx)); 1454 1463 return 0; … … 1458 1467 { 1459 1468 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1460 int idx = kcontrol->id.index;1469 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1461 1470 return put_route_val(ice, ucontrol->value.enumerated.item[0], 1462 1471 analog_route_shift(idx)); … … 1466 1475 { 1467 1476 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1468 int idx = kcontrol->id.index;1477 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1469 1478 ucontrol->value.enumerated.item[0] = get_route_val(ice, digital_route_shift(idx)); 1470 1479 return 0; … … 1474 1483 { 1475 1484 ice1712_t *ice = snd_kcontrol_chip(kcontrol); 1476 int idx = kcontrol->id.index;1485 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 1477 1486 return put_route_val(ice, ucontrol->value.enumerated.item[0], 1478 1487 digital_route_shift(idx)); … … 1493 1502 .get = snd_vt1724_pro_route_spdif_get, 1494 1503 .put = snd_vt1724_pro_route_spdif_put, 1504 .count = 2, 1495 1505 }; 1496 1506 … … 1603 1613 { 1604 1614 int err; 1605 unsigned int idx;1606 1615 snd_kcontrol_t *kctl; 1607 1616 1608 1617 snd_assert(ice->pcm != NULL, return -EIO); 1609 1618 1610 for (idx = 0; idx < 2; idx++) { 1611 kctl = snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice); 1612 if (kctl == NULL) 1613 return -ENOMEM; 1614 kctl->id.index = idx; 1615 err = snd_ctl_add(ice->card, kctl); 1616 if (err < 0) 1617 return err; 1618 } 1619 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice)); 1620 if (err < 0) 1621 return err; 1619 1622 1620 1623 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice)); … … 1647 1650 static int __devinit snd_vt1724_build_controls(ice1712_t *ice) 1648 1651 { 1649 unsigned int idx;1650 snd_kcontrol_t *kctl;1651 1652 int err; 1652 1653 … … 1665 1666 return err; 1666 1667 1667 for (idx = 0; idx < ice->num_total_dacs; idx++) { 1668 kctl = snd_ctl_new1(&snd_vt1724_mixer_pro_analog_route, ice); 1669 if (kctl == NULL) 1670 return -ENOMEM; 1671 kctl->id.index = idx; 1672 err = snd_ctl_add(ice->card, kctl); 1668 if (ice->num_total_dacs > 0) { 1669 snd_kcontrol_new_t tmp = snd_vt1724_mixer_pro_analog_route; 1670 tmp.count = ice->num_total_dacs; 1671 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice)); 1673 1672 if (err < 0) 1674 1673 return err; … … 1703 1702 kfree_nocheck(ice->res_profi_port); 1704 1703 } 1705 if (ice->akm) 1706 kfree(ice->akm); 1704 snd_ice1712_akm4xxx_free(ice); 1707 1705 snd_magic_kfree(ice); 1708 1706 return 0; -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/makefile.os2
r224 r246 13 13 # 14 14 #=================================================================== 15 FILE1 = ak4 524.obj delta.obj ews.obj hoontech.obj ice1712.obj15 FILE1 = ak4xxx.obj delta.obj ews.obj hoontech.obj ice1712.obj 16 16 FILE2 = ice1724.obj revo.obj 17 17 FILE3 = -
GPL/branches/alsa-resync1/alsa-kernel/pci/ice1712/revo.c
r224 r246 66 66 67 67 /* reset DFS */ 68 snd_ ice1712_akm4xxx_reset(ak, 1);68 snd_akm4xxx_reset(ak, 1); 69 69 tmp = ak->images[0][reg]; 70 70 tmp &= ~(0x03 << shift); 71 71 tmp |= dfs << shift; 72 snd_ ice1712_akm4xxx_write(ak, 0, reg, tmp);73 snd_ ice1712_akm4xxx_reset(ak, 0);72 snd_akm4xxx_write(ak, 0, reg, tmp); 73 snd_akm4xxx_reset(ak, 0); 74 74 } 75 75 … … 81 81 .type = SND_AK4381, 82 82 .num_dacs = 2, 83 .ops = { 84 .set_rate_val = revo_set_rate_val 85 } 86 }; 87 88 static struct snd_ak4xxx_private akm_revo_front_priv __devinitdata = { 83 89 .caddr = 1, 84 90 .cif = 0, … … 90 96 .add_flags = VT1724_REVO_CCLK, /* high at init */ 91 97 .mask_flags = 0, 92 .ops = {93 .set_rate_val = revo_set_rate_val94 }95 98 }; 96 99 … … 99 102 .idx_offset = 1, 100 103 .num_dacs = 6, 104 .ops = { 105 .set_rate_val = revo_set_rate_val 106 } 107 }; 108 109 static struct snd_ak4xxx_private akm_revo_surround_priv __devinitdata = { 101 110 .caddr = 3, 102 111 .cif = 0, … … 108 117 .add_flags = VT1724_REVO_CCLK, /* high at init */ 109 118 .mask_flags = 0, 110 .ops = {111 .set_rate_val = revo_set_rate_val112 }113 119 }; 114 120 … … 134 140 switch (ice->eeprom.subvendor) { 135 141 case VT1724_SUBDEVICE_REVOLUTION71: 136 snd_ice1712_akm4xxx_init(ak, &akm_revo_front, ice);137 snd_ice1712_akm4xxx_init(ak + 1, &akm_revo_surround, ice);142 snd_ice1712_akm4xxx_init(ak, &akm_revo_front, &akm_revo_front_priv, ice); 143 snd_ice1712_akm4xxx_init(ak + 1, &akm_revo_surround, &akm_revo_surround_priv, ice); 138 144 /* unmute all codecs */ 139 145 snd_ice1712_gpio_write_bits(ice, VT1724_REVO_MUTE, VT1724_REVO_MUTE); -
GPL/branches/alsa-resync1/alsa-kernel/pci/korg1212/korg1212.c
r224 r246 150 150 #define MAILBOX2_OFFSET 0x48 // location of mailbox 2 relative to base address 151 151 #define MAILBOX3_OFFSET 0x4c // location of mailbox 3 relative to base address 152 #define OUT_DOORBELL_OFFSET 0x60 // location of PCI to local doorbell "153 #define IN_DOORBELL_OFFSET 0x64 // location of local to PCI doorbell "154 #define STATUS_REG_OFFSET 0x68 // location of interrupt control/status register "152 #define OUT_DOORBELL_OFFSET 0x60 // location of PCI to local doorbell 153 #define IN_DOORBELL_OFFSET 0x64 // location of local to PCI doorbell 154 #define STATUS_REG_OFFSET 0x68 // location of interrupt control/status register 155 155 #define PCI_CONTROL_OFFSET 0x6c // location of the EEPROM, PCI, User I/O, init control 156 156 // register … … 330 330 331 331 spinlock_t lock; 332 struct semaphore open_mutex; 333 334 struct timer_list timer; /* timer callback for checking ack of stop request */ 335 int stop_pending_cnt; /* counter for stop pending check */ 332 336 333 337 wait_queue_head_t wait; … … 603 607 } 604 608 605 static void snd_korg1212_WaitForCardStopAck(korg1212_t *korg1212) 606 { 607 u32 endtime = jiffies + 2 * HZ; 608 609 #if K1212_DEBUG_LEVEL > 0 610 K1212_DEBUG_PRINTK("K1212_DEBUG: WaitForCardStopAck.in [%s] %lu %lu\n", stateName[korg1212->cardState], jiffies, korg1212->inIRQ); 611 #endif 612 613 if (korg1212->inIRQ) 614 return; 615 616 do { 609 /* spinlock already held */ 610 static void snd_korg1212_SendStop(korg1212_t *korg1212) 611 { 612 if (! korg1212->stop_pending_cnt) { 613 writel(0xffffffff, &korg1212->sharedBufferPtr->cardCommand); 614 /* program the timer */ 615 korg1212->stop_pending_cnt = HZ; 616 korg1212->timer.expires = jiffies + 1; 617 add_timer(&korg1212->timer); 618 } 619 } 620 621 static void snd_korg1212_SendStopAndWait(korg1212_t *korg1212) 622 { 623 unsigned long flags; 624 spin_lock_irqsave(&korg1212->lock, flags); 625 snd_korg1212_SendStop(korg1212); 626 spin_unlock_irqrestore(&korg1212->lock, flags); 627 sleep_on_timeout(&korg1212->wait, (HZ * 3) / 2); 628 } 629 630 /* timer callback for checking the ack of stop request */ 631 static void snd_korg1212_timer_func(unsigned long data) 632 { 633 korg1212_t *korg1212 = snd_magic_cast(korg1212_t, (void*)data, return); 634 635 spin_lock(&korg1212->lock); 617 636 if (readl(&korg1212->sharedBufferPtr->cardCommand) == 0) { 618 #if K1212_DEBUG_LEVEL > 0 619 K1212_DEBUG_PRINTK("K1212_DEBUG: WaitForCardStopAck.out [%s] %lu %lu\n", stateName[korg1212->cardState], jiffies, korg1212->inIRQ); 620 #endif 621 return; 637 /* ack'ed */ 638 korg1212->stop_pending_cnt = 0; 639 wake_up(&korg1212->wait); 640 #if K1212_DEBUG_LEVEL > 1 641 K1212_DEBUG_PRINTK("K1212_DEBUG: Stop ack'ed [%s]\n", stateName[korg1212->cardState]); 642 #endif 643 } else { 644 if (--korg1212->stop_pending_cnt > 0) { 645 /* reprogram timer */ 646 korg1212->timer.expires = jiffies + 1; 647 add_timer(&korg1212->timer); 648 } else { 649 snd_printd("korg1212_timer_func timeout\n"); 650 writel(0, &korg1212->sharedBufferPtr->cardCommand); 651 wake_up(&korg1212->wait); 652 #if K1212_DEBUG_LEVEL > 0 653 K1212_DEBUG_PRINTK("K1212_DEBUG: Stop timeout [%s]\n", stateName[korg1212->cardState]); 654 #endif 622 655 } 623 if (!korg1212->inIRQ) 624 schedule(); 625 } while (time_before(jiffies, endtime)); 626 627 #if K1212_DEBUG_LEVEL > 0 628 K1212_DEBUG_PRINTK("K1212_DEBUG: WaitForCardStopAck.out TO [%s] %lu %lu\n", stateName[korg1212->cardState], jiffies, korg1212->inIRQ); 629 #endif 630 writel(0, &korg1212->sharedBufferPtr->cardCommand); 656 } 657 spin_unlock(&korg1212->lock); 631 658 } 632 659 633 660 static void snd_korg1212_TurnOnIdleMonitor(korg1212_t *korg1212) 634 661 { 662 unsigned long flags; 663 635 664 udelay(INTERCOMMAND_DELAY); 665 spin_lock_irqsave(&korg1212->lock, flags); 636 666 korg1212->idleMonitorOn = 1; 637 667 rc = snd_korg1212_Send1212Command(korg1212, K1212_DB_SelectPlayMode, 638 668 K1212_MODE_MonitorOn, 0, 0, 0); 669 spin_unlock_irqrestore(&korg1212->lock, flags); 639 670 } 640 671 … … 642 673 { 643 674 if (korg1212->idleMonitorOn) { 644 writel(0xffffffff, &korg1212->sharedBufferPtr->cardCommand); 645 snd_korg1212_WaitForCardStopAck(korg1212); 675 snd_korg1212_SendStopAndWait(korg1212); 646 676 korg1212->idleMonitorOn = 0; 647 677 } 648 678 } 649 679 650 static void snd_korg1212_setCardState(korg1212_t * korg1212, CardState csState) 651 { 652 switch (csState) { 653 case K1212_STATE_READY: 654 snd_korg1212_TurnOnIdleMonitor(korg1212); 655 break; 656 657 case K1212_STATE_OPEN: 658 snd_korg1212_TurnOffIdleMonitor(korg1212); 659 break; 660 661 default: 662 break; 663 } 664 680 static inline void snd_korg1212_setCardState(korg1212_t * korg1212, CardState csState) 681 { 665 682 korg1212->cardState = csState; 666 683 } … … 671 688 K1212_DEBUG_PRINTK("K1212_DEBUG: OpenCard [%s] %d\n", stateName[korg1212->cardState], korg1212->opencnt); 672 689 #endif 673 if (korg1212->opencnt++ == 0) 690 down(&korg1212->open_mutex); 691 if (korg1212->opencnt++ == 0) { 692 snd_korg1212_TurnOffIdleMonitor(korg1212); 674 693 snd_korg1212_setCardState(korg1212, K1212_STATE_OPEN); 694 } 695 696 up(&korg1212->open_mutex); 675 697 return 1; 676 698 } … … 682 704 #endif 683 705 684 if (--(korg1212->opencnt)) 706 down(&korg1212->open_mutex); 707 if (--(korg1212->opencnt)) { 708 up(&korg1212->open_mutex); 685 709 return 0; 710 } 686 711 687 712 if (korg1212->cardState == K1212_STATE_SETUP) { … … 692 717 #endif 693 718 694 if (rc != K1212_CMDRET_Success) 719 if (rc != K1212_CMDRET_Success) { 720 up(&korg1212->open_mutex); 695 721 return 0; 722 } 696 723 } else if (korg1212->cardState > K1212_STATE_SETUP) { 697 writel(0xffffffff, &korg1212->sharedBufferPtr->cardCommand);698 snd_korg1212_WaitForCardStopAck(korg1212);699 } 700 701 if (korg1212->cardState > K1212_STATE_READY) 724 snd_korg1212_SendStopAndWait(korg1212); 725 } 726 727 if (korg1212->cardState > K1212_STATE_READY) { 728 snd_korg1212_TurnOnIdleMonitor(korg1212); 702 729 snd_korg1212_setCardState(korg1212, K1212_STATE_READY); 703 730 } 731 732 up(&korg1212->open_mutex); 704 733 return 0; 705 734 } 706 735 736 /* spinlock already held */ 707 737 static int snd_korg1212_SetupForPlay(korg1212_t * korg1212) 708 738 { … … 727 757 } 728 758 759 /* spinlock already held */ 729 760 static int snd_korg1212_TriggerPlay(korg1212_t * korg1212) 730 761 { … … 749 780 } 750 781 782 /* spinlock already held */ 751 783 static int snd_korg1212_StopPlay(korg1212_t * korg1212) 752 784 { … … 760 792 korg1212->setcnt = 0; 761 793 762 if (korg1212->cardState != K1212_STATE_ERRORSTOP) { 763 writel(0xffffffff, &korg1212->sharedBufferPtr->cardCommand); 764 snd_korg1212_WaitForCardStopAck(korg1212); 765 } 794 if (korg1212->cardState != K1212_STATE_ERRORSTOP) 795 snd_korg1212_SendStop(korg1212); 796 766 797 snd_korg1212_setCardState(korg1212, K1212_STATE_OPEN); 767 798 return 0; … … 790 821 return 0; 791 822 } else { 792 writel(0xffffffff, &korg1212->sharedBufferPtr->cardCommand); 793 snd_korg1212_WaitForCardStopAck(korg1212); 823 snd_korg1212_SendStopAndWait(korg1212); 794 824 snd_korg1212_setCardState(korg1212, K1212_STATE_OPEN); 795 825 } … … 885 915 // the card's eeprom control register. 886 916 u16 count; 917 unsigned long flags; 887 918 888 919 #if K1212_DEBUG_LEVEL > 0 … … 901 932 // ---------------------------------------------------------------------------- 902 933 if (korg1212->cardState == K1212_STATE_MONITOR || korg1212->idleMonitorOn) { 903 writel(0xffffffff, &korg1212->sharedBufferPtr->cardCommand);904 934 monModeSet = 1; 905 snd_korg1212_WaitForCardStopAck(korg1212);935 snd_korg1212_SendStopAndWait(korg1212); 906 936 } else 907 937 monModeSet = 0; 938 939 spin_lock_irqsave(&korg1212->lock, flags); 908 940 909 941 // ---------------------------------------------------------------------------- … … 1017 1049 } 1018 1050 1051 spin_unlock_irqrestore(&korg1212->lock, flags); 1052 1019 1053 return 1; 1020 1054 } … … 1090 1124 #endif 1091 1125 1126 snd_korg1212_TurnOnIdleMonitor(korg1212); 1092 1127 snd_korg1212_setCardState(korg1212, K1212_STATE_READY); 1093 1128 … … 1096 1131 #endif 1097 1132 1098 wake_up_interruptible(&korg1212->wait);1099 } 1100 1101 static voidsnd_korg1212_interrupt(int irq, void *dev_id, struct pt_regs *regs)1133 snd_korg1212_setCardState(korg1212, K1212_STATE_DSP_COMPLETE); 1134 } 1135 1136 static irqreturn_t snd_korg1212_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1102 1137 { 1103 1138 u32 doorbellValue; 1104 korg1212_t *korg1212 = snd_magic_cast(korg1212_t, dev_id, return );1139 korg1212_t *korg1212 = snd_magic_cast(korg1212_t, dev_id, return IRQ_NONE); 1105 1140 1106 1141 if(irq != korg1212->irq) 1107 return ;1142 return IRQ_NONE; 1108 1143 1109 1144 doorbellValue = readl(korg1212->inDoorbellPtr); 1110 1145 1111 1146 if (!doorbellValue) 1112 return; 1147 return IRQ_HANDLED; 1148 1149 spin_lock(&korg1212->lock); 1113 1150 1114 1151 writel(doorbellValue, korg1212->inDoorbellPtr); … … 1124 1161 K1212_DEBUG_PRINTK("K1212_DEBUG: IRQ DNLD count - %ld, %x, [%s].\n", korg1212->irqcount, doorbellValue, stateName[korg1212->cardState]); 1125 1162 #endif 1126 if (korg1212->cardState == K1212_STATE_DSP_IN_PROCESS) { 1127 snd_korg1212_setCardState(korg1212, K1212_STATE_DSP_COMPLETE); 1128 snd_korg1212_OnDSPDownloadComplete(korg1212); 1129 } 1163 if (korg1212->cardState == K1212_STATE_DSP_IN_PROCESS) 1164 wake_up(&korg1212->wait); 1130 1165 break; 1131 1166 … … 1167 1202 1168 1203 if (korg1212->capture_substream) { 1204 spin_unlock(&korg1212->lock); 1169 1205 snd_pcm_period_elapsed(korg1212->capture_substream); 1206 spin_lock(&korg1212->lock); 1170 1207 } 1171 1208 1172 1209 if (korg1212->playback_substream) { 1210 spin_unlock(&korg1212->lock); 1173 1211 snd_pcm_period_elapsed(korg1212->playback_substream); 1212 spin_lock(&korg1212->lock); 1174 1213 } 1175 1214 } … … 1178 1217 1179 1218 korg1212->inIRQ--; 1219 1220 spin_unlock(&korg1212->lock); 1221 return IRQ_HANDLED; 1180 1222 } 1181 1223 … … 1206 1248 #endif 1207 1249 1208 interruptible_sleep_on_timeout(&korg1212->wait, HZ * 4); 1250 if (! sleep_on_timeout(&korg1212->wait, HZ * 4)) 1251 return -EBUSY; /* timeout */ 1252 1253 snd_korg1212_OnDSPDownloadComplete(korg1212); 1209 1254 1210 1255 return 0; … … 1364 1409 snd_pcm_set_sync(substream); // ??? 1365 1410 1366 spin_lock_irqsave(&korg1212->lock, flags);1367 1368 1411 snd_korg1212_OpenCard(korg1212); 1369 1412 1413 runtime->hw = snd_korg1212_playback_info; 1370 1414 runtime->dma_area = (char *) korg1212->playDataBufsPtr; 1371 1415 runtime->dma_bytes = K1212_BUF_SIZE; 1416 1417 spin_lock_irqsave(&korg1212->lock, flags); 1372 1418 1373 1419 korg1212->playback_substream = substream; … … 1394 1440 snd_pcm_set_sync(substream); // ??? 1395 1441 1396 spin_lock_irqsave(&korg1212->lock, flags);1397 1398 1442 snd_korg1212_OpenCard(korg1212); 1399 1443 … … 1402 1446 runtime->dma_bytes = K1212_BUF_SIZE; 1403 1447 1448 spin_lock_irqsave(&korg1212->lock, flags); 1449 1404 1450 korg1212->capture_substream = substream; 1405 1451 korg1212->periodsize = K1212_PERIODS; … … 1428 1474 korg1212->periodsize = 0; 1429 1475 1430 snd_korg1212_CloseCard(korg1212);1431 1432 1476 spin_unlock_irqrestore(&korg1212->lock, flags); 1477 1478 snd_korg1212_CloseCard(korg1212); 1433 1479 return 0; 1434 1480 } … … 1448 1494 korg1212->periodsize = 0; 1449 1495 1450 snd_korg1212_CloseCard(korg1212);1451 1452 1496 spin_unlock_irqrestore(&korg1212->lock, flags); 1497 1498 snd_korg1212_CloseCard(korg1212); 1453 1499 return 0; 1454 1500 } … … 1508 1554 { 1509 1555 korg1212_t *korg1212 = _snd_pcm_substream_chip(substream); 1510 unsigned long flags;1511 1556 int rc; 1512 1557 … … 1515 1560 #endif 1516 1561 1517 spin_lock_irqsave(&korg1212->lock, flags); 1562 spin_lock(&korg1212->lock); 1563 1564 /* FIXME: we should wait for ack! */ 1565 if (korg1212->stop_pending_cnt > 0) { 1566 #if K1212_DEBUG_LEVEL > 0 1567 K1212_DEBUG_PRINTK("K1212_DEBUG: snd_korg1212_prepare - Stop is pending... [%s]\n", stateName[korg1212->cardState]); 1568 #endif 1569 spin_unlock(&korg1212->lock); 1570 return -EAGAIN; 1571 /* 1572 writel(0, &korg1212->sharedBufferPtr->cardCommand); 1573 del_timer(&korg1212->timer); 1574 korg1212->stop_pending_cnt = 0; 1575 */ 1576 } 1518 1577 1519 1578 rc = snd_korg1212_SetupForPlay(korg1212); 1579 1520 1580 korg1212->currentBuffer = 0; 1521 1581 1522 spin_unlock _irqrestore(&korg1212->lock, flags);1582 spin_unlock(&korg1212->lock); 1523 1583 1524 1584 return rc ? -EINVAL : 0; … … 1535 1595 #endif 1536 1596 1597 spin_lock(&korg1212->lock); 1537 1598 switch (cmd) { 1538 1599 case SNDRV_PCM_TRIGGER_START: … … 1566 1627 break; 1567 1628 } 1629 spin_unlock(&korg1212->lock); 1568 1630 return rc ? -EINVAL : 0; 1569 1631 } … … 1894 1956 } 1895 1957 1958 spin_unlock_irqrestore(&korg1212->lock, flags); 1959 1896 1960 if (change) 1897 1961 snd_korg1212_WriteADCSensitivity(korg1212); 1898 1899 spin_unlock_irqrestore(&korg1212->lock, flags);1900 1962 1901 1963 return change; … … 2151 2213 init_waitqueue_head(&korg1212->wait); 2152 2214 spin_lock_init(&korg1212->lock); 2215 init_MUTEX(&korg1212->open_mutex); 2216 init_timer(&korg1212->timer); 2217 korg1212->timer.function = snd_korg1212_timer_func; 2218 korg1212->timer.data = (unsigned long)korg1212; 2153 2219 2154 2220 korg1212->irq = -1; -
GPL/branches/alsa-resync1/alsa-kernel/pci/rme96.c
r224 r246 1154 1154 } 1155 1155 1156 static void1156 static irqreturn_t 1157 1157 snd_rme96_interrupt(int irq, 1158 1158 void *dev_id, … … 1166 1166 (rme96->rcreg & RME96_RCR_IRQ_2))) 1167 1167 { 1168 return ;1168 return IRQ_NONE; 1169 1169 } 1170 1170 … … 1179 1179 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1180 1180 } 1181 return IRQ_HANDLED; 1181 1182 } 1182 1183 -
GPL/branches/alsa-resync1/alsa-kernel/pci/rme9652/hdsp.c
r224 r246 3 3 * 4 4 * Copyright (c) 2002 Paul Davis 5 * Marcus Andersson 6 * Thomas Charbonnel 5 7 * 6 8 * This program is free software; you can redistribute it and/or modify … … 21 23 22 24 #include <sound/driver.h> 23 #include <asm/io.h>24 #include <asm/byteorder.h>25 25 #include <linux/delay.h> 26 #include <linux/in it.h>26 #include <linux/interrupt.h> 27 27 #include <linux/slab.h> 28 28 #include <linux/pci.h> 29 29 30 #include <sound/core.h> 30 31 #include <sound/control.h> … … 33 34 #include <sound/asoundef.h> 34 35 #include <sound/rawmidi.h> 36 #include <sound/hwdep.h> 35 37 #define SNDRV_GET_ID 36 38 #include <sound/initval.h> 37 38 #include "multiface_firmware.dat" 39 #include "digiface_firmware.dat" 39 #include <sound/hdsp.h> 40 41 #include <asm/byteorder.h> 42 #include <asm/current.h> 43 #include <asm/io.h> 40 44 41 45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ … … 44 48 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */ 45 49 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */ 46 static int force_firmware[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Force firmware reload */47 50 48 51 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i"); … … 61 64 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default."); 62 65 MODULE_PARM_SYNTAX(line_outs_monitor, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC); 63 MODULE_PARM(force_firmware,"1-" __MODULE_STRING(SNDRV_CARDS) "i"); 64 MODULE_PARM_DESC(force_firmware, "Force a reload of the I/O box firmware"); 65 MODULE_PARM_SYNTAX(force_firmware, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC); 66 MODULE_AUTHOR("Paul Davis <pbd@op.net>"); 66 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); 67 67 MODULE_DESCRIPTION("RME Hammerfall DSP"); 68 68 MODULE_LICENSE("GPL"); 69 69 MODULE_CLASSES("{sound}"); 70 MODULE_DEVICES("{{RME,Hammerfall-DSP}}"); 71 72 typedef enum { 73 Digiface, 74 Multiface 75 } HDSP_Type; 70 MODULE_DEVICES("{{RME Hammerfall-DSP}," 71 "{RME HDSP-9652}}"); 76 72 77 73 #define HDSP_MAX_CHANNELS 26 … … 79 75 #define DIGIFACE_DS_CHANNELS 14 80 76 #define MULTIFACE_SS_CHANNELS 18 81 #define MULTIFACE_DS_CHANNELS 1 077 #define MULTIFACE_DS_CHANNELS 14 82 78 83 79 /* Write registers. These are defined as byte-offsets from the iobase value. … … 119 115 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ 120 116 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ 121 #define HDSP_outputPeakLevel 4 100 /* 26* 32 bit values */117 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ 122 118 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ 123 #define HDSP_inputRmsLevel 48 84/* 26 * 64 bit values */119 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 124 120 125 121 #define HDSP_IO_EXTENT 5192 … … 144 140 /* Control Register bits */ 145 141 146 #define HDSP_Start (1<<0) / / start engine147 #define HDSP_Latency0 (1<<1) / / buffer size = 2^n where n is defined by Latency{2,1,0}148 #define HDSP_Latency1 (1<<2) / / [ see above ]149 #define HDSP_Latency2 (1<<3) / / ] see above ]150 #define HDSP_ClockModeMaster (1<<4) / / 1=Master, 0=Slave/Autosync151 #define HDSP_AudioInterruptEnable (1<<5) / / what do you think ?152 #define HDSP_Frequency0 (1<<6) / / 0=44.1kHz/88.2kHz 1=48kHz/96kHz153 #define HDSP_Frequency1 (1<<7) / / 0=32kHz/64kHz154 #define HDSP_DoubleSpeed (1<<8) / / 0=normal speed, 1=double speed155 #define HDSP_SPDIFProfessional (1<<9) / / 0=consumer, 1=professional156 #define HDSP_SPDIFEmphasis (1<<10) / / 0=none, 1=on157 #define HDSP_SPDIFNonAudio (1<<11) / / 0=off, 1=on158 #define HDSP_SPDIFOpticalOut (1<<12) / / 1=use 1st ADAT connector for SPDIF, 0=do not142 #define HDSP_Start (1<<0) /* start engine */ 143 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 144 #define HDSP_Latency1 (1<<2) /* [ see above ] */ 145 #define HDSP_Latency2 (1<<3) /* ] see above ] */ 146 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 147 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 148 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 149 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 150 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 151 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ 152 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ 153 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ 154 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ 159 155 #define HDSP_SyncRef2 (1<<13) 160 156 #define HDSP_SPDIFInputSelect0 (1<<14) … … 182 178 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) 183 179 184 /* Preferred sync source choices - used by "sync_pref" control switch */ 185 186 #define HDSP_SYNC_FROM_SELF 0 187 #define HDSP_SYNC_FROM_WORD 1 188 #define HDSP_SYNC_FROM_ADAT_SYNC 2 189 #define HDSP_SYNC_FROM_SPDIF 3 190 #define HDSP_SYNC_FROM_ADAT1 4 191 #define HDSP_SYNC_FROM_ADAT2 5 192 #define HDSP_SYNC_FROM_ADAT3 6 180 /* Sample Clock Sources */ 181 182 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 183 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 184 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 185 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 186 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 187 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 188 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 189 190 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 191 192 #define HDSP_SYNC_FROM_WORD 0 193 #define HDSP_SYNC_FROM_ADAT_SYNC 1 194 #define HDSP_SYNC_FROM_SPDIF 2 195 #define HDSP_SYNC_FROM_ADAT1 3 196 #define HDSP_SYNC_FROM_ADAT2 4 197 #define HDSP_SYNC_FROM_ADAT3 5 198 199 /* SyncCheck status */ 200 201 #define HDSP_SYNC_CHECK_NO_LOCK 0 202 #define HDSP_SYNC_CHECK_LOCK 1 203 #define HDSP_SYNC_CHECK_SYNC 2 204 205 /* AutoSync references - used by "autosync_ref" control switch */ 206 207 #define HDSP_AUTOSYNC_FROM_WORD 0 208 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 209 #define HDSP_AUTOSYNC_FROM_SPDIF 2 210 #define HDSP_AUTOSYNC_FROM_NONE 3 211 #define HDSP_AUTOSYNC_FROM_ADAT1 4 212 #define HDSP_AUTOSYNC_FROM_ADAT2 5 213 #define HDSP_AUTOSYNC_FROM_ADAT3 6 193 214 194 215 /* Possible sources of S/PDIF input */ … … 238 259 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) 239 260 240 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0 |HDSP_spdifFrequency1|HDSP_spdifFrequency2)241 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency 2|HDSP_spdifFrequency1)242 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency 2)243 244 #define HDSP_spdifFrequency64KHz 0245 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency 2)246 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency 0|HDSP_spdifFrequency1)261 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) 262 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) 263 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) 264 265 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) 266 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 267 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 247 268 248 269 /* Status2 Register bits */ … … 278 299 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) 279 300 280 /* FIFO wait times, defined in terms of loops on readl() */ 281 282 #define HDSP_LONG_WAIT 40000 283 #define HDSP_SHORT_WAIT 100 284 285 /* Computing addresses for adjusting gains */ 286 287 #define INPUT_TO_OUTPUT_KEY(in,out) ((64 * (out)) + (in)) 288 #define PLAYBACK_TO_OUTPUT_KEY(chn,out) ((64 * (out)) + 32 + (chn)) 301 /* Card state flags */ 302 303 #define HDSP_InitializationComplete (1<<0) 304 #define HDSP_FirmwareLoaded (1<<1) 305 #define HDSP_FirmwareCached (1<<2) 306 307 /* FIFO wait times, defined in terms of 1/10ths of msecs */ 308 309 #define HDSP_LONG_WAIT 5000 310 #define HDSP_SHORT_WAIT 30 311 289 312 #define UNITY_GAIN 32768 290 313 #define MINUS_INFINITY_GAIN 0 … … 314 337 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 315 338 316 #define HDSP_MATRIX_MIXER_SIZE 2048 317 318 typedef struct _hdsp hdsp_t; 319 typedef struct _hdsp_midi hdsp_midi_t; 339 typedef struct _hdsp hdsp_t; 340 typedef struct _hdsp_midi hdsp_midi_t; 320 341 321 342 struct _hdsp_midi { … … 328 349 struct timer_list timer; 329 350 spinlock_t lock; 351 int pending; 330 352 }; 331 353 332 354 struct _hdsp { 333 spinlock_t lock; 334 snd_pcm_substream_t *capture_substream; 335 snd_pcm_substream_t *playback_substream; 336 hdsp_midi_t midi[2]; 337 int precise_ptr; 338 u32 control_register; /* cached value */ 339 u32 creg_spdif; 340 u32 creg_spdif_stream; 341 char *card_name; /* digiface/multiface */ 342 HDSP_Type type; /* ditto, but for code use */ 343 size_t period_bytes; /* guess what this is */ 344 unsigned char ds_channels; 345 unsigned char ss_channels; /* different for multiface/digiface */ 346 void *capture_buffer_unaligned; /* original buffer addresses */ 347 void *playback_buffer_unaligned; /* original buffer addresses */ 348 unsigned char *capture_buffer; /* suitably aligned address */ 349 unsigned char *playback_buffer; /* suitably aligned address */ 350 dma_addr_t capture_buffer_addr; 351 dma_addr_t playback_buffer_addr; 352 pid_t capture_pid; 353 pid_t playback_pid; 354 int running; 355 int passthru; /* non-zero if doing pass-thru */ 356 int last_spdif_sample_rate; /* so that we can catch externally ... */ 357 int last_adat_sample_rate; /* ... induced rate changes */ 358 char *channel_map; 359 int dev; 360 int irq; 361 unsigned long port; 362 struct resource *res_port; 363 unsigned long iobase; 364 snd_card_t *card; 365 snd_pcm_t *pcm; 366 struct pci_dev *pci; 367 snd_info_entry_t *proc_entry; 368 snd_kcontrol_t *spdif_ctl; 369 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 355 spinlock_t lock; 356 snd_pcm_substream_t *capture_substream; 357 snd_pcm_substream_t *playback_substream; 358 hdsp_midi_t midi[2]; 359 struct tasklet_struct midi_tasklet; 360 int precise_ptr; 361 u32 control_register; /* cached value */ 362 u32 creg_spdif; 363 u32 creg_spdif_stream; 364 char *card_name; /* digiface/multiface */ 365 HDSP_IO_Type io_type; /* ditto, but for code use */ 366 unsigned short firmware_rev; 367 unsigned short state; /* stores state bits */ 368 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ 369 size_t period_bytes; /* guess what this is */ 370 unsigned char ds_channels; 371 unsigned char ss_channels; /* different for multiface/digiface */ 372 void *capture_buffer_unaligned; /* original buffer addresses */ 373 void *playback_buffer_unaligned; /* original buffer addresses */ 374 unsigned char *capture_buffer; /* suitably aligned address */ 375 unsigned char *playback_buffer; /* suitably aligned address */ 376 dma_addr_t capture_buffer_addr; 377 dma_addr_t playback_buffer_addr; 378 pid_t capture_pid; 379 pid_t playback_pid; 380 int running; 381 int passthru; /* non-zero if doing pass-thru */ 382 int last_spdif_sample_rate;/* for information reporting */ 383 int last_external_sample_rate; 384 int last_internal_sample_rate; 385 int system_sample_rate; 386 char *channel_map; 387 int dev; 388 int irq; 389 unsigned long port; 390 struct resource *res_port; 391 unsigned long iobase; 392 snd_card_t *card; 393 snd_pcm_t *pcm; 394 snd_hwdep_t *hwdep; 395 struct pci_dev *pci; 396 snd_kcontrol_t *spdif_ctl; 397 snd_kcontrol_t *playback_mixer_ctls[HDSP_MAX_CHANNELS]; 398 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 370 399 }; 371 400 … … 384 413 385 414 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ 386 /* A DAT 0*/415 /* Analog */ 387 416 0, 1, 2, 3, 4, 5, 6, 7, 388 417 /* ADAT 2 */ … … 410 439 411 440 static struct pci_device_id snd_hdsp_ids[] __devinitdata = { 412 {PCI_VENDOR_ID_XILINX, 413 PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, /* RME Hammerfall-DSP */ 415 {0,} 441 { 442 .vendor = PCI_VENDOR_ID_XILINX, 443 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 444 .subvendor = PCI_ANY_ID, 445 .subdevice = PCI_ANY_ID, 446 }, /* RME Hammerfall-DSP */ 447 { 0, }, 416 448 }; 417 449 418 450 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); 419 451 452 /* prototypes */ 453 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp); 454 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp); 455 static inline int snd_hdsp_initialize_input_enable (hdsp_t *hdsp); 456 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp); 457 static inline void snd_hdsp_initialize_channels (hdsp_t *hdsp); 458 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout); 459 static int hdsp_update_simple_mixer_controls(hdsp_t *hdsp); 460 static int hdsp_autosync_ref(hdsp_t *hdsp); 461 static int snd_hdsp_set_defaults(hdsp_t *hdsp); 462 463 static inline int hdsp_is_9652 (hdsp_t *hdsp) 464 { 465 switch (hdsp->firmware_rev) { 466 case 0x64: 467 case 0x65: 468 case 0x68: 469 return 1; 470 default: 471 return 0; 472 } 473 } 474 475 static inline int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out) 476 { 477 switch (hdsp->firmware_rev) { 478 case 0xa: 479 return (64 * out) + (32 + (in)); 480 default: 481 return (52 * out) + (26 + (in)); 482 } 483 } 484 485 static inline int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out) 486 { 487 switch (hdsp->firmware_rev) { 488 case 0xa: 489 return (64 * out) + in; 490 default: 491 return (52 * out) + in; 492 } 493 } 494 420 495 static inline void hdsp_write(hdsp_t *hdsp, int reg, int val) 421 496 { … … 426 501 { 427 502 return readl (hdsp->iobase + reg); 428 }429 430 static inline unsigned long long hdsp_read64 (hdsp_t *hdsp, int reg)431 {432 unsigned long long val;433 val = hdsp_read(hdsp, reg);434 val = (val<<32)|hdsp_read(hdsp, reg + 4);435 436 return val;437 503 } 438 504 … … 441 507 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { 442 508 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); 509 hdsp->state &= ~HDSP_FirmwareLoaded; 443 510 return -EIO; 444 511 } 445 512 return 0; 446 513 } 514 515 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) { 516 517 int i; 518 unsigned long flags; 519 520 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 521 522 snd_printk ("loading firmware\n"); 523 524 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_PROGRAM); 525 hdsp_write (hdsp, HDSP_fifoData, 0); 526 527 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 528 snd_printk ("timeout waiting for download preparation\n"); 529 return -EIO; 530 } 531 532 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD); 533 534 for (i = 0; i < 24413; ++i) { 535 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]); 536 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 537 snd_printk ("timeout during firmware loading\n"); 538 return -EIO; 539 } 540 } 541 542 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 543 snd_printk ("timeout at end of firmware loading\n"); 544 return -EIO; 545 } 546 547 hdsp_write (hdsp, HDSP_jtagReg, 0); 548 snd_printk ("finished firmware loading\n"); 549 550 if ((1000 / HZ) < 3000) { 551 set_current_state(TASK_UNINTERRUPTIBLE); 552 schedule_timeout((3000 * HZ + 999) / 1000); 553 } else { 554 mdelay(3000); 555 } 556 } 557 if (hdsp->state & HDSP_InitializationComplete) { 558 snd_printk("firmware loaded from cache, restoring defaults\n"); 559 spin_lock_irqsave(&hdsp->lock, flags); 560 snd_hdsp_set_defaults(hdsp); 561 spin_unlock_irqrestore(&hdsp->lock, flags); 562 } 563 564 hdsp->state |= HDSP_FirmwareLoaded; 565 566 return 0; 567 } 568 569 static inline int hdsp_get_iobox_version (hdsp_t *hdsp) 570 { 571 int err; 572 573 if (hdsp_check_for_iobox (hdsp)) { 574 return -EIO; 575 } 576 577 if ((err = snd_hdsp_initialize_input_enable(hdsp)) < 0) { 578 return err; 579 } 580 581 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 582 583 hdsp_write (hdsp, HDSP_jtagReg, HDSP_PROGRAM); 584 hdsp_write (hdsp, HDSP_fifoData, 0); 585 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) { 586 return -EIO; 587 } 588 589 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD); 590 hdsp_write (hdsp, HDSP_fifoData, 0); 591 592 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { 593 hdsp->io_type = Multiface; 594 hdsp_write (hdsp, HDSP_jtagReg, HDSP_VERSION_BIT); 595 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD); 596 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); 597 } else { 598 hdsp->io_type = Digiface; 599 } 600 } else { 601 /* firmware was already loaded, get iobox type */ 602 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) { 603 hdsp->io_type = Multiface; 604 } else { 605 hdsp->io_type = Digiface; 606 } 607 } 608 return 0; 609 } 610 611 612 static inline int hdsp_check_for_firmware (hdsp_t *hdsp) 613 { 614 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 615 snd_printk("firmware not present.\n"); 616 hdsp->state &= ~HDSP_FirmwareLoaded; 617 return -EIO; 618 } 619 return 0; 620 } 621 447 622 448 623 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout) … … 454 629 */ 455 630 456 for (i = 0; i < timeout; i++) 631 for (i = 0; i < timeout; i++) { 632 457 633 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) 458 634 return 0; 635 636 /* not very friendly, but we only do this during a firmware 637 load and changing the mixer, so we just put up with it. 638 */ 639 640 udelay (100); 641 } 459 642 460 643 snd_printk ("wait for FIFO status <= %d failed after %d iterations\n", … … 475 658 unsigned int ad; 476 659 477 if (addr >= HDSP_MATRIX_MIXER_SIZE) 478 return -1; 479 480 ad = data + addr * 65536; 481 482 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) { 483 return -1; 484 } 485 hdsp_write (hdsp, HDSP_fifoData, ad); 486 hdsp->mixer_matrix[addr] = data; 660 if (hdsp_is_9652 (hdsp)) { 661 662 if ((ad = addr/2) < 676) { 663 664 /* from martin björnsen: 665 666 "You can only write dwords to the 667 mixer memory which contain two 668 mixer values in the low and high 669 word. So if you want to change 670 value 0 you have to read value 1 671 from the cache and write both to 672 the first dword in the mixer 673 memory." 674 */ 675 676 hdsp->mixer_matrix[addr] = data; 677 hdsp_write (hdsp, 1024 + ad, 678 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 679 hdsp->mixer_matrix[addr&0x7fe]); 680 return 0; 681 } else { 682 return -1; 683 } 684 685 686 } else { 687 if (addr >= HDSP_MATRIX_MIXER_SIZE) 688 return -1; 689 690 ad = (addr << 16) + data; 691 692 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) { 693 return -1; 694 } 695 696 hdsp_write (hdsp, HDSP_fifoData, ad); 697 hdsp->mixer_matrix[addr] = data; 698 699 } 487 700 488 701 return 0; … … 503 716 } 504 717 505 static inline int hdsp_ system_sample_rate (hdsp_t *hdsp)718 static inline int hdsp_external_sample_rate (hdsp_t *hdsp) 506 719 { 507 720 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); … … 515 728 case HDSP_systemFrequency88_2: return 88200; 516 729 case HDSP_systemFrequency96: return 96000; 517 default: return 0; 730 default: 731 return 0; 518 732 } 519 733 } … … 527 741 return 0; 528 742 } 529 743 530 744 switch (rate_bits) { 531 745 case HDSP_spdifFrequency32KHz: return 32000; … … 536 750 case HDSP_spdifFrequency96KHz: return 96000; 537 751 default: 538 snd_printk ("unknown frequency status; bits = 0x%x, status = 0x%x", rate_bits, status);752 snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); 539 753 return 0; 540 754 } … … 565 779 static inline void hdsp_reset_hw_pointer(hdsp_t *hdsp) 566 780 { 567 #if 0 568 /* reset the hw pointer to zero. We do this by writing to 8 569 registers, each of which is a 32bit wide register, and set 570 them all to zero. 571 */ 572 573 for (i = 0; i < 8; ++i) { 574 hdsp_write(hdsp, i, 0); 575 udelay(10); 576 } 577 #endif 781 hdsp_write (hdsp, HDSP_resetPointer, 0); 578 782 } 579 783 … … 620 824 } 621 825 622 static int hdsp_set_rate(hdsp_t *hdsp, int rate )826 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally) 623 827 { 624 828 int reject_if_open = 0; 625 829 int current_rate; 626 627 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 628 snd_printk ("device is not running as a clock master: cannot set sample rate.\n"); 629 return -1; 630 } 830 int rate_bits; 831 832 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 833 if (called_internally) { 834 /* request from ctl or card initialization */ 835 snd_printk("device is not running as a clock master: cannot set sample rate.\n"); 836 return -1; 837 } else { 838 /* hw_param request while in AutoSync mode */ 839 int external_freq = hdsp_external_sample_rate(hdsp); 840 int spdif_freq = hdsp_spdif_sample_rate(hdsp); 841 842 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) { 843 snd_printk("Detected ADAT in double speed mode\n"); 844 } else if (rate != external_freq) { 845 snd_printk("No AutoSync source for requested rate\n"); 846 return -1; 847 } 848 } 849 } 850 851 current_rate = hdsp->system_sample_rate; 631 852 632 853 /* Changing from a "single speed" to a "double speed" rate is … … 638 859 Note that a similar but essentially insoluble problem 639 860 exists for externally-driven rate changes. All we can do 640 is to flag rate changes in the read/write routines. 641 */ 861 is to flag rate changes in the read/write routines. */ 642 862 643 863 spin_lock_irq(&hdsp->lock); 644 current_rate = hdsp_system_sample_rate(hdsp);645 864 646 865 switch (rate) { … … 649 868 reject_if_open = 1; 650 869 } 651 rate = HDSP_Frequency32KHz;870 rate_bits = HDSP_Frequency32KHz; 652 871 break; 653 872 case 44100: … … 655 874 reject_if_open = 1; 656 875 } 657 rate = HDSP_Frequency44_1KHz;876 rate_bits = HDSP_Frequency44_1KHz; 658 877 break; 659 878 case 48000: … … 661 880 reject_if_open = 1; 662 881 } 663 rate = HDSP_Frequency48KHz;882 rate_bits = HDSP_Frequency48KHz; 664 883 break; 665 884 case 64000: 666 if (current_rate < 48000) {885 if (current_rate <= 48000) { 667 886 reject_if_open = 1; 668 887 } 669 rate = HDSP_Frequency64KHz;888 rate_bits = HDSP_Frequency64KHz; 670 889 break; 671 890 case 88200: 672 if (current_rate < 48000) {891 if (current_rate <= 48000) { 673 892 reject_if_open = 1; 674 893 } 675 rate = HDSP_Frequency88_2KHz;894 rate_bits = HDSP_Frequency88_2KHz; 676 895 break; 677 896 case 96000: 678 if (current_rate < 48000) {897 if (current_rate <= 48000) { 679 898 reject_if_open = 1; 680 899 } 681 rate = HDSP_Frequency96KHz;900 rate_bits = HDSP_Frequency96KHz; 682 901 break; 683 902 default: 903 spin_unlock_irq(&hdsp->lock); 684 904 return -EINVAL; 685 905 } … … 694 914 695 915 hdsp->control_register &= ~HDSP_FrequencyMask; 696 hdsp->control_register |= rate ;916 hdsp->control_register |= rate_bits; 697 917 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 698 918 … … 700 920 hdsp->channel_map = channel_map_ds; 701 921 } else { 702 switch (hdsp-> type) {922 switch (hdsp->io_type) { 703 923 case Multiface: 704 924 hdsp->channel_map = channel_map_mf_ss; … … 707 927 hdsp->channel_map = channel_map_df_ss; 708 928 break; 709 } 929 default: 930 /* should never happen */ 931 break; 932 } 933 } 934 935 hdsp->system_sample_rate = rate; 936 937 if (reject_if_open) { 938 hdsp_update_simple_mixer_controls (hdsp); 710 939 } 711 940 … … 727 956 if (enable) { 728 957 for (i = 0; i < 26; i++) { 729 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(i,i), UNITY_GAIN);958 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN); 730 959 } 731 960 } else { 732 961 for (i = 0; i < 26; i++) { 733 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(i,i), MINUS_INFINITY_GAIN);962 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN); 734 963 } 735 964 } … … 742 971 mapped_channel = hdsp->channel_map[channel]; 743 972 973 snd_assert(mapped_channel > -1, return); 974 744 975 if (enable) { 745 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(channel,channel), UNITY_GAIN);976 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN); 746 977 } else { 747 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(channel,channel), MINUS_INFINITY_GAIN);978 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN); 748 979 } 749 980 } … … 809 1040 static inline int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id) 810 1041 { 1042 int fifo_bytes_used; 1043 811 1044 if (id) { 812 return (hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff) < 128;1045 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; 813 1046 } else { 814 return (hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff)< 128; 1047 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; 1048 } 1049 1050 if (fifo_bytes_used < 128) { 1051 return 128 - fifo_bytes_used; 1052 } else { 1053 return 0; 815 1054 } 816 1055 } … … 827 1066 unsigned long flags; 828 1067 int n_pending; 829 int clear_timer = 0;830 1068 int to_write; 831 1069 int i; … … 835 1073 836 1074 spin_lock_irqsave (&hmidi->lock, flags); 837 838 1075 if (hmidi->output) { 839 1076 if (!snd_rawmidi_transmit_empty (hmidi->output)) { … … 845 1082 for (i = 0; i < to_write; ++i) 846 1083 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); 847 } else {848 clear_timer = 1;849 1084 } 850 1085 } 851 } else { 852 clear_timer = 1; 853 } 854 855 if (clear_timer && hmidi->istimer && --hmidi->istimer <= 0) { 856 del_timer(&hmidi->timer); 857 } 858 } 859 1086 } 1087 } 860 1088 spin_unlock_irqrestore (&hmidi->lock, flags); 861 1089 return 0; … … 870 1098 871 1099 spin_lock_irqsave (&hmidi->lock, flags); 872 873 1100 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { 874 1101 if (hmidi->input) { … … 888 1115 } 889 1116 } 890 } 1117 } 1118 hmidi->pending = 0; 1119 if (hmidi->id) { 1120 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; 1121 } else { 1122 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; 1123 } 1124 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); 891 1125 spin_unlock_irqrestore (&hmidi->lock, flags); 892 1126 return snd_hdsp_midi_output_write (hmidi); … … 963 1197 } 964 1198 spin_unlock_irqrestore (&hmidi->lock, flags); 1199 if (up) 1200 snd_hdsp_midi_output_write(hmidi); 965 1201 } 966 1202 … … 1046 1282 hdsp->midi[id].hdsp = hdsp; 1047 1283 hdsp->midi[id].istimer = 0; 1284 hdsp->midi[id].pending = 0; 1048 1285 spin_lock_init (&hdsp->midi[id].lock); 1049 1286 … … 1168 1405 1169 1406 #define HDSP_SPDIF_IN(xname, xindex) \ 1170 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \ 1407 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 1408 .name = xname, \ 1409 .index = xindex, \ 1171 1410 .info = snd_hdsp_info_spdif_in, \ 1172 .get = snd_hdsp_get_spdif_in, .put = snd_hdsp_put_spdif_in } 1411 .get = snd_hdsp_get_spdif_in, \ 1412 .put = snd_hdsp_put_spdif_in } 1173 1413 1174 1414 static unsigned int hdsp_spdif_in(hdsp_t *hdsp) … … 1201 1441 { 1202 1442 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1203 unsigned long flags; 1204 1205 spin_lock_irqsave(&hdsp->lock, flags); 1443 1206 1444 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); 1207 spin_unlock_irqrestore(&hdsp->lock, flags);1208 1445 return 0; 1209 1446 } … … 1228 1465 1229 1466 #define HDSP_SPDIF_OUT(xname, xindex) \ 1230 { .iface = SNDRV_CTL_ELEM_IFACE_ PCM, .name = xname, .index = xindex, \1231 .info = snd_hdsp_info_spdif_ out, \1467 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ 1468 .info = snd_hdsp_info_spdif_bits, \ 1232 1469 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } 1233 1470 … … 1248 1485 } 1249 1486 1250 static int snd_hdsp_info_spdif_ out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)1487 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1251 1488 { 1252 1489 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; … … 1260 1497 { 1261 1498 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1262 unsigned long flags; 1263 1264 spin_lock_irqsave(&hdsp->lock, flags); 1499 1265 1500 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); 1266 spin_unlock_irqrestore(&hdsp->lock, flags);1267 1501 return 0; 1268 1502 } … … 1285 1519 } 1286 1520 1287 #define HDSP_SYNC_PREF(xname, xindex) \ 1288 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \ 1289 .info = snd_hdsp_info_sync_pref, \ 1290 .get = snd_hdsp_get_sync_pref, .put = snd_hdsp_put_sync_pref } 1291 1292 static int hdsp_sync_pref(hdsp_t *hdsp) 1521 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ 1522 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ 1523 .info = snd_hdsp_info_spdif_bits, \ 1524 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } 1525 1526 static int hdsp_spdif_professional(hdsp_t *hdsp) 1527 { 1528 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; 1529 } 1530 1531 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val) 1532 { 1533 if (val) { 1534 hdsp->control_register |= HDSP_SPDIFProfessional; 1535 } else { 1536 hdsp->control_register &= ~HDSP_SPDIFProfessional; 1537 } 1538 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1539 return 0; 1540 } 1541 1542 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1543 { 1544 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1545 1546 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); 1547 return 0; 1548 } 1549 1550 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1551 { 1552 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1553 unsigned long flags; 1554 int change; 1555 unsigned int val; 1556 1557 if (!snd_hdsp_use_is_exclusive(hdsp)) 1558 return -EBUSY; 1559 val = ucontrol->value.integer.value[0] & 1; 1560 spin_lock_irqsave(&hdsp->lock, flags); 1561 change = (int)val != hdsp_spdif_professional(hdsp); 1562 hdsp_set_spdif_professional(hdsp, val); 1563 spin_unlock_irqrestore(&hdsp->lock, flags); 1564 return change; 1565 } 1566 1567 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ 1568 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ 1569 .info = snd_hdsp_info_spdif_bits, \ 1570 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } 1571 1572 static int hdsp_spdif_emphasis(hdsp_t *hdsp) 1573 { 1574 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; 1575 } 1576 1577 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val) 1578 { 1579 if (val) { 1580 hdsp->control_register |= HDSP_SPDIFEmphasis; 1581 } else { 1582 hdsp->control_register &= ~HDSP_SPDIFEmphasis; 1583 } 1584 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1585 return 0; 1586 } 1587 1588 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1589 { 1590 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1591 1592 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); 1593 return 0; 1594 } 1595 1596 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1597 { 1598 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1599 unsigned long flags; 1600 int change; 1601 unsigned int val; 1602 1603 if (!snd_hdsp_use_is_exclusive(hdsp)) 1604 return -EBUSY; 1605 val = ucontrol->value.integer.value[0] & 1; 1606 spin_lock_irqsave(&hdsp->lock, flags); 1607 change = (int)val != hdsp_spdif_emphasis(hdsp); 1608 hdsp_set_spdif_emphasis(hdsp, val); 1609 spin_unlock_irqrestore(&hdsp->lock, flags); 1610 return change; 1611 } 1612 1613 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ 1614 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ 1615 .info = snd_hdsp_info_spdif_bits, \ 1616 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } 1617 1618 static int hdsp_spdif_nonaudio(hdsp_t *hdsp) 1619 { 1620 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; 1621 } 1622 1623 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val) 1624 { 1625 if (val) { 1626 hdsp->control_register |= HDSP_SPDIFNonAudio; 1627 } else { 1628 hdsp->control_register &= ~HDSP_SPDIFNonAudio; 1629 } 1630 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1631 return 0; 1632 } 1633 1634 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1635 { 1636 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1637 1638 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); 1639 return 0; 1640 } 1641 1642 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1643 { 1644 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1645 unsigned long flags; 1646 int change; 1647 unsigned int val; 1648 1649 if (!snd_hdsp_use_is_exclusive(hdsp)) 1650 return -EBUSY; 1651 val = ucontrol->value.integer.value[0] & 1; 1652 spin_lock_irqsave(&hdsp->lock, flags); 1653 change = (int)val != hdsp_spdif_nonaudio(hdsp); 1654 hdsp_set_spdif_nonaudio(hdsp, val); 1655 spin_unlock_irqrestore(&hdsp->lock, flags); 1656 return change; 1657 } 1658 1659 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ 1660 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 1661 .name = xname, \ 1662 .index = xindex, \ 1663 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1664 .info = snd_hdsp_info_spdif_sample_rate, \ 1665 .get = snd_hdsp_get_spdif_sample_rate \ 1666 } 1667 1668 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1669 { 1670 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None"}; 1671 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1672 uinfo->count = 1; 1673 uinfo->value.enumerated.items = 7 ; 1674 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1675 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1676 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1677 return 0; 1678 } 1679 1680 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1681 { 1682 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1683 1684 switch (hdsp_spdif_sample_rate(hdsp)) { 1685 case 32000: 1686 ucontrol->value.enumerated.item[0] = 0; 1687 break; 1688 case 44100: 1689 ucontrol->value.enumerated.item[0] = 1; 1690 break; 1691 case 48000: 1692 ucontrol->value.enumerated.item[0] = 2; 1693 break; 1694 case 64000: 1695 ucontrol->value.enumerated.item[0] = 3; 1696 break; 1697 case 88200: 1698 ucontrol->value.enumerated.item[0] = 4; 1699 break; 1700 case 96000: 1701 ucontrol->value.enumerated.item[0] = 5; 1702 break; 1703 default: 1704 ucontrol->value.enumerated.item[0] = 6; 1705 } 1706 return 0; 1707 } 1708 1709 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1710 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 1711 .name = xname, \ 1712 .index = xindex, \ 1713 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1714 .info = snd_hdsp_info_system_sample_rate, \ 1715 .get = snd_hdsp_get_system_sample_rate \ 1716 } 1717 1718 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1719 { 1720 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1721 uinfo->count = 1; 1722 return 0; 1723 } 1724 1725 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1726 { 1727 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1728 1729 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; 1730 return 0; 1731 } 1732 1733 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 1734 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 1735 .name = xname, \ 1736 .index = xindex, \ 1737 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1738 .info = snd_hdsp_info_autosync_sample_rate, \ 1739 .get = snd_hdsp_get_autosync_sample_rate \ 1740 } 1741 1742 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1743 { 1744 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None"}; 1745 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1746 uinfo->count = 1; 1747 uinfo->value.enumerated.items = 7 ; 1748 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1749 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1750 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1751 return 0; 1752 } 1753 1754 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1755 { 1756 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1757 1758 switch (hdsp_external_sample_rate(hdsp)) { 1759 case 32000: 1760 ucontrol->value.enumerated.item[0] = 0; 1761 break; 1762 case 44100: 1763 ucontrol->value.enumerated.item[0] = 1; 1764 break; 1765 case 48000: 1766 ucontrol->value.enumerated.item[0] = 2; 1767 break; 1768 case 64000: 1769 ucontrol->value.enumerated.item[0] = 3; 1770 break; 1771 case 88200: 1772 ucontrol->value.enumerated.item[0] = 4; 1773 break; 1774 case 96000: 1775 ucontrol->value.enumerated.item[0] = 5; 1776 break; 1777 default: 1778 ucontrol->value.enumerated.item[0] = 6; 1779 } 1780 return 0; 1781 } 1782 1783 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ 1784 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 1785 .name = xname, \ 1786 .index = xindex, \ 1787 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1788 .info = snd_hdsp_info_system_clock_mode, \ 1789 .get = snd_hdsp_get_system_clock_mode \ 1790 } 1791 1792 static int hdsp_system_clock_mode(hdsp_t *hdsp) 1793 { 1794 if (hdsp->control_register & HDSP_ClockModeMaster) { 1795 return 0; 1796 } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) { 1797 return 0; 1798 } 1799 return 1; 1800 } 1801 1802 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1803 { 1804 static char *texts[] = {"Master", "Slave" }; 1805 1806 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1807 uinfo->count = 1; 1808 uinfo->value.enumerated.items = 2; 1809 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1810 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1811 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1812 return 0; 1813 } 1814 1815 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1816 { 1817 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1818 1819 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); 1820 return 0; 1821 } 1822 1823 #define HDSP_CLOCK_SOURCE(xname, xindex) \ 1824 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 1825 .name = xname, \ 1826 .index = xindex, \ 1827 .info = snd_hdsp_info_clock_source, \ 1828 .get = snd_hdsp_get_clock_source, \ 1829 .put = snd_hdsp_put_clock_source \ 1830 } 1831 1832 static int hdsp_clock_source(hdsp_t *hdsp) 1833 { 1834 if (hdsp->control_register & HDSP_ClockModeMaster) { 1835 switch (hdsp->system_sample_rate) { 1836 case 32000: 1837 return 1; 1838 case 44100: 1839 return 2; 1840 case 48000: 1841 return 3; 1842 case 64000: 1843 return 4; 1844 case 88200: 1845 return 5; 1846 case 96000: 1847 return 6; 1848 default: 1849 return 3; 1850 } 1851 } else { 1852 return 0; 1853 } 1854 } 1855 1856 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode) 1857 { 1858 int rate; 1859 switch (mode) { 1860 case HDSP_CLOCK_SOURCE_AUTOSYNC: 1861 if (hdsp_external_sample_rate(hdsp) != 0) { 1862 hdsp->control_register &= ~HDSP_ClockModeMaster; 1863 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1864 return 0; 1865 } 1866 return -1; 1867 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 1868 rate = 32000; 1869 break; 1870 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 1871 rate = 44100; 1872 break; 1873 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 1874 rate = 48000; 1875 break; 1876 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 1877 rate = 64000; 1878 break; 1879 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 1880 rate = 88200; 1881 break; 1882 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 1883 rate = 96000; 1884 break; 1885 default: 1886 rate = 48000; 1887 } 1888 hdsp->control_register |= HDSP_ClockModeMaster; 1889 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1890 hdsp_set_rate(hdsp, rate, 1); 1891 return 0; 1892 } 1893 1894 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1895 { 1896 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz" }; 1897 1898 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1899 uinfo->count = 1; 1900 uinfo->value.enumerated.items = 7; 1901 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1902 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1903 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1904 return 0; 1905 } 1906 1907 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1908 { 1909 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1910 1911 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); 1912 return 0; 1913 } 1914 1915 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1916 { 1917 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1918 unsigned long flags; 1919 int change; 1920 int val; 1921 1922 if (!snd_hdsp_use_is_exclusive(hdsp)) 1923 return -EBUSY; 1924 val = ucontrol->value.enumerated.item[0]; 1925 if (val < 0) val = 0; 1926 if (val > 6) val = 6; 1927 spin_lock_irqsave(&hdsp->lock, flags); 1928 if (val != hdsp_clock_source(hdsp)) { 1929 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; 1930 } else { 1931 change = 0; 1932 } 1933 spin_unlock_irqrestore(&hdsp->lock, flags); 1934 return change; 1935 } 1936 1937 #define HDSP_PREF_SYNC_REF(xname, xindex) \ 1938 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 1939 .name = xname, \ 1940 .index = xindex, \ 1941 .info = snd_hdsp_info_pref_sync_ref, \ 1942 .get = snd_hdsp_get_pref_sync_ref, \ 1943 .put = snd_hdsp_put_pref_sync_ref \ 1944 } 1945 1946 static int hdsp_pref_sync_ref(hdsp_t *hdsp) 1293 1947 { 1294 1948 /* Notice that this looks at the requested sync source, 1295 1949 not the one actually in use. 1296 1950 */ 1297 1298 if (hdsp->control_register & HDSP_ClockModeMaster) {1299 return HDSP_SYNC_FROM_SELF;1300 }1301 1951 1302 1952 switch (hdsp->control_register & HDSP_SyncRefMask) { … … 1314 1964 return HDSP_SYNC_FROM_ADAT_SYNC; 1315 1965 default: 1316 return HDSP_SYNC_FROM_ SELF;1317 } 1318 return 0; 1319 } 1320 1321 static int hdsp_set_ sync_pref(hdsp_t *hdsp, int pref)1966 return HDSP_SYNC_FROM_WORD; 1967 } 1968 return 0; 1969 } 1970 1971 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref) 1322 1972 { 1323 1973 hdsp->control_register &= ~HDSP_SyncRefMask; 1324 1974 switch (pref) { 1325 1975 case HDSP_SYNC_FROM_ADAT1: 1326 hdsp->control_register &= ~HDSP_ClockModeMaster;1327 1976 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ 1328 1977 break; 1329 1978 case HDSP_SYNC_FROM_ADAT2: 1330 hdsp->control_register &= ~HDSP_ClockModeMaster;1331 1979 hdsp->control_register |= HDSP_SyncRef_ADAT2; 1332 1980 break; 1333 1981 case HDSP_SYNC_FROM_ADAT3: 1334 hdsp->control_register &= ~HDSP_ClockModeMaster;1335 1982 hdsp->control_register |= HDSP_SyncRef_ADAT3; 1336 1983 break; 1337 1984 case HDSP_SYNC_FROM_SPDIF: 1338 hdsp->control_register &= ~HDSP_ClockModeMaster;1339 1985 hdsp->control_register |= HDSP_SyncRef_SPDIF; 1340 1986 break; 1341 1987 case HDSP_SYNC_FROM_WORD: 1342 hdsp->control_register &= ~HDSP_ClockModeMaster;1343 1988 hdsp->control_register |= HDSP_SyncRef_WORD; 1344 1989 break; 1345 1990 case HDSP_SYNC_FROM_ADAT_SYNC: 1346 hdsp->control_register &= ~HDSP_ClockModeMaster;1347 1991 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; 1348 break;1349 case HDSP_SYNC_FROM_SELF:1350 hdsp->control_register |= HDSP_ClockModeMaster;1351 1992 break; 1352 1993 default: … … 1357 1998 } 1358 1999 1359 static int snd_hdsp_info_ sync_pref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)1360 { 1361 static char *texts[] = {" Internal", "Word", "ADAT Sync", "IEC958", "ADAT1", "ADAT2", "ADAT3" };2000 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2001 { 2002 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "ADAT1", "ADAT2", "ADAT3" }; 1362 2003 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1363 2004 1364 2005 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1365 2006 uinfo->count = 1; 1366 uinfo->value.enumerated.items = (hdsp-> type == Digiface) ? 7 : 6;2007 uinfo->value.enumerated.items = (hdsp->io_type == Digiface) ? 6 : 4; 1367 2008 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1368 2009 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; … … 1371 2012 } 1372 2013 1373 static int snd_hdsp_get_ sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)2014 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1374 2015 { 1375 2016 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1376 unsigned long flags; 1377 1378 spin_lock_irqsave(&hdsp->lock, flags); 1379 ucontrol->value.enumerated.item[0] = hdsp_sync_pref(hdsp); 1380 spin_unlock_irqrestore(&hdsp->lock, flags); 1381 return 0; 1382 } 1383 1384 static int snd_hdsp_put_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2017 2018 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2019 return 0; 2020 } 2021 2022 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1385 2023 { 1386 2024 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); … … 1391 2029 if (!snd_hdsp_use_is_exclusive(hdsp)) 1392 2030 return -EBUSY; 1393 max = hdsp->ss_channels == (hdsp->type == Digiface) ? 7 : 6;2031 max = (hdsp->io_type == Digiface) ? 6 : 4; 1394 2032 val = ucontrol->value.enumerated.item[0] % max; 1395 2033 spin_lock_irqsave(&hdsp->lock, flags); 1396 change = (int)val != hdsp_ sync_pref(hdsp);1397 hdsp_set_ sync_pref(hdsp, val);2034 change = (int)val != hdsp_pref_sync_ref(hdsp); 2035 hdsp_set_pref_sync_ref(hdsp, val); 1398 2036 spin_unlock_irqrestore(&hdsp->lock, flags); 1399 2037 return change; 1400 2038 } 1401 2039 2040 #define HDSP_AUTOSYNC_REF(xname, xindex) \ 2041 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2042 .name = xname, \ 2043 .index = xindex, \ 2044 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2045 .info = snd_hdsp_info_autosync_ref, \ 2046 .get = snd_hdsp_get_autosync_ref, \ 2047 } 2048 2049 static int hdsp_autosync_ref(hdsp_t *hdsp) 2050 { 2051 /* This looks at the autosync selected sync reference */ 2052 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 2053 2054 switch (status2 & HDSP_SelSyncRefMask) { 2055 case HDSP_SelSyncRef_WORD: 2056 return HDSP_AUTOSYNC_FROM_WORD; 2057 case HDSP_SelSyncRef_ADAT_SYNC: 2058 return HDSP_AUTOSYNC_FROM_ADAT_SYNC; 2059 case HDSP_SelSyncRef_SPDIF: 2060 return HDSP_AUTOSYNC_FROM_SPDIF; 2061 case HDSP_SelSyncRefMask: 2062 return HDSP_AUTOSYNC_FROM_NONE; 2063 case HDSP_SelSyncRef_ADAT1: 2064 return HDSP_AUTOSYNC_FROM_ADAT1; 2065 case HDSP_SelSyncRef_ADAT2: 2066 return HDSP_AUTOSYNC_FROM_ADAT2; 2067 case HDSP_SelSyncRef_ADAT3: 2068 return HDSP_AUTOSYNC_FROM_ADAT3; 2069 default: 2070 return HDSP_AUTOSYNC_FROM_WORD; 2071 } 2072 return 0; 2073 } 2074 2075 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2076 { 2077 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; 2078 2079 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2080 uinfo->count = 1; 2081 uinfo->value.enumerated.items = 7; 2082 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2083 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2084 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2085 return 0; 2086 } 2087 2088 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2089 { 2090 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 2091 2092 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2093 return 0; 2094 } 2095 1402 2096 #define HDSP_PASSTHRU(xname, xindex) \ 1403 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \ 2097 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2098 .name = xname, \ 2099 .index = xindex, \ 1404 2100 .info = snd_hdsp_info_passthru, \ 1405 2101 .put = snd_hdsp_put_passthru, \ 1406 .get = snd_hdsp_get_passthru } 2102 .get = snd_hdsp_get_passthru \ 2103 } 1407 2104 1408 2105 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) … … 1447 2144 1448 2145 #define HDSP_LINE_OUT(xname, xindex) \ 1449 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \ 2146 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2147 .name = xname, \ 2148 .index = xindex, \ 1450 2149 .info = snd_hdsp_info_line_out, \ 1451 .get = snd_hdsp_get_line_out, .put = snd_hdsp_put_line_out } 2150 .get = snd_hdsp_get_line_out, \ 2151 .put = snd_hdsp_put_line_out \ 2152 } 1452 2153 1453 2154 static int hdsp_line_out(hdsp_t *hdsp) … … 1505 2206 1506 2207 #define HDSP_MIXER(xname, xindex) \ 1507 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \ 2208 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2209 .name = xname, \ 2210 .index = xindex, \ 2211 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2212 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1508 2213 .info = snd_hdsp_info_mixer, \ 1509 .get = snd_hdsp_get_mixer, .put = snd_hdsp_put_mixer } 2214 .get = snd_hdsp_get_mixer, \ 2215 .put = snd_hdsp_put_mixer \ 2216 } 1510 2217 1511 2218 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) … … 1531 2238 1532 2239 if (source > 25) { 1533 addr = PLAYBACK_TO_OUTPUT_KEY(source-26,destination);2240 addr = hdsp_playback_to_output_key(hdsp,source-26,destination); 1534 2241 } else { 1535 addr = INPUT_TO_OUTPUT_KEY(source, destination);2242 addr = hdsp_input_to_output_key(hdsp,source, destination); 1536 2243 } 1537 2244 1538 2245 spin_lock_irqsave(&hdsp->lock, flags); 1539 ucontrol->value.integer.value[ 0] = hdsp_read_gain (hdsp, addr);2246 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); 1540 2247 spin_unlock_irqrestore(&hdsp->lock, flags); 1541 2248 return 0; … … 1559 2266 1560 2267 if (source > 25) { 1561 addr = PLAYBACK_TO_OUTPUT_KEY(source-26, destination);2268 addr = hdsp_playback_to_output_key(hdsp,source-26, destination); 1562 2269 } else { 1563 addr = INPUT_TO_OUTPUT_KEY(source, destination);2270 addr = hdsp_input_to_output_key(hdsp,source, destination); 1564 2271 } 1565 2272 … … 1584 2291 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1585 2292 .info = snd_hdsp_info_playback_mixer, \ 1586 .get = snd_hdsp_get_playback_mixer, .put = snd_hdsp_put_playback_mixer } 2293 .get = snd_hdsp_get_playback_mixer, \ 2294 .put = snd_hdsp_put_playback_mixer \ 2295 } 1587 2296 1588 2297 static int snd_hdsp_info_playback_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) … … 1601 2310 unsigned long flags; 1602 2311 int addr; 1603 int chn; 1604 1605 chn = ucontrol->id.index - 1; 1606 addr = PLAYBACK_TO_OUTPUT_KEY(chn, chn); 2312 int channel; 2313 int mapped_channel; 2314 2315 channel = ucontrol->id.index - 1; 2316 2317 snd_assert(channel >= 0 || channel < HDSP_MAX_CHANNELS, return -EINVAL); 2318 2319 if ((mapped_channel = hdsp->channel_map[channel]) < 0) { 2320 return -EINVAL; 2321 } 2322 2323 addr = hdsp_playback_to_output_key(hdsp,mapped_channel, mapped_channel); 1607 2324 1608 2325 spin_lock_irqsave(&hdsp->lock, flags); … … 1618 2335 int change; 1619 2336 int addr; 1620 int chn; 2337 int channel; 2338 int mapped_channel; 1621 2339 int gain; 1622 2340 … … 1624 2342 return -EBUSY; 1625 2343 1626 chn = ucontrol->id.index - 1; 1627 addr = PLAYBACK_TO_OUTPUT_KEY(chn, chn); 2344 channel = ucontrol->id.index - 1; 2345 2346 snd_assert(channel >= 0 || channel < HDSP_MAX_CHANNELS, return -EINVAL); 2347 2348 if ((mapped_channel = hdsp->channel_map[channel]) < 0) { 2349 return -EINVAL; 2350 } 2351 2352 addr = hdsp_playback_to_output_key(hdsp,mapped_channel, mapped_channel); 1628 2353 gain = ucontrol->value.integer.value[0]; 1629 2354 … … 1637 2362 } 1638 2363 1639 #define HDSP_PEAK_PLAYBACK \ 1640 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 2364 #define HDSP_WC_SYNC_CHECK(xname, xindex) \ 2365 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2366 .name = xname, \ 2367 .index = xindex, \ 1641 2368 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1642 .info = snd_hdsp_info_peak_playback, \ 1643 .get = snd_hdsp_get_peak_playback \ 1644 } 1645 1646 static int snd_hdsp_info_peak_playback(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1647 { 1648 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1649 uinfo->count = 2; 1650 return 0; 1651 } 1652 1653 static int snd_hdsp_get_peak_playback(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2369 .info = snd_hdsp_info_sync_check, \ 2370 .get = snd_hdsp_get_wc_sync_check \ 2371 } 2372 2373 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2374 { 2375 static char *texts[] = {"No Lock", "Lock", "Sync" }; 2376 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2377 uinfo->count = 1; 2378 uinfo->value.enumerated.items = 3; 2379 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2380 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2381 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2382 return 0; 2383 } 2384 2385 static int hdsp_wc_sync_check(hdsp_t *hdsp) 2386 { 2387 int status2 = hdsp_read(hdsp, HDSP_status2Register); 2388 if (status2 & HDSP_wc_lock) { 2389 if (status2 & HDSP_wc_sync) { 2390 return 2; 2391 } else { 2392 return 1; 2393 } 2394 } else { 2395 return 0; 2396 } 2397 return 0; 2398 } 2399 2400 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1654 2401 { 1655 2402 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1656 unsigned int peakval = hdsp_read (hdsp, HDSP_playbackPeakLevel + (4 * (ucontrol->id.index-1))); 1657 ucontrol->value.integer.value[0] = peakval & 0xffffff00; /* peak */ 1658 ucontrol->value.integer.value[1] = peakval & 0xf; /* overs */ 1659 return 0; 1660 } 1661 1662 #define HDSP_PEAK_INPUT \ 1663 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 2403 2404 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); 2405 return 0; 2406 } 2407 2408 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ 2409 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2410 .name = xname, \ 2411 .index = xindex, \ 1664 2412 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1665 .info = snd_hdsp_info_peak_input, \ 1666 .get = snd_hdsp_get_peak_input \ 1667 } 1668 1669 static int snd_hdsp_info_peak_input(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1670 { 1671 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1672 uinfo->count = 2; 1673 return 0; 1674 } 1675 1676 static int snd_hdsp_get_peak_input(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2413 .info = snd_hdsp_info_sync_check, \ 2414 .get = snd_hdsp_get_spdif_sync_check \ 2415 } 2416 2417 static int hdsp_spdif_sync_check(hdsp_t *hdsp) 2418 { 2419 int status = hdsp_read(hdsp, HDSP_statusRegister); 2420 if (status & HDSP_SPDIFErrorFlag) { 2421 return 0; 2422 } else { 2423 if (status & HDSP_SPDIFSync) { 2424 return 2; 2425 } else { 2426 return 1; 2427 } 2428 } 2429 return 0; 2430 } 2431 2432 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1677 2433 { 1678 2434 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1679 unsigned int peakval = hdsp_read (hdsp, HDSP_inputPeakLevel + (4 * (ucontrol->id.index-1))); 1680 ucontrol->value.integer.value[0] = peakval & 0xffffff00; /* peak */ 1681 ucontrol->value.integer.value[1] = peakval & 0xf; /* overs */ 1682 return 0; 1683 } 1684 1685 #define HDSP_PEAK_OUTPUT \ 1686 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 2435 2436 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); 2437 return 0; 2438 } 2439 2440 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ 2441 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2442 .name = xname, \ 2443 .index = xindex, \ 1687 2444 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1688 .info = snd_hdsp_info_peak_output, \ 1689 .get = snd_hdsp_get_peak_output \ 1690 } 1691 1692 static int snd_hdsp_info_peak_output(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1693 { 1694 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1695 uinfo->count = 2; 1696 return 0; 1697 } 1698 1699 static int snd_hdsp_get_peak_output(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2445 .info = snd_hdsp_info_sync_check, \ 2446 .get = snd_hdsp_get_adatsync_sync_check \ 2447 } 2448 2449 static int hdsp_adatsync_sync_check(hdsp_t *hdsp) 2450 { 2451 int status = hdsp_read(hdsp, HDSP_statusRegister); 2452 if (status & HDSP_TimecodeLock) { 2453 if (status & HDSP_TimecodeSync) { 2454 return 2; 2455 } else { 2456 return 1; 2457 } 2458 } else { 2459 return 0; 2460 } 2461 } 2462 2463 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1700 2464 { 1701 2465 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1702 unsigned int peakval = hdsp_read (hdsp, HDSP_outputPeakLevel + (4 * (ucontrol->id.index-1))); 1703 ucontrol->value.integer.value[0] = peakval & 0xffffff00; /* peak */ 1704 ucontrol->value.integer.value[1] = peakval & 0xf; /* overs */ 1705 return 0; 1706 } 1707 1708 #define HDSP_RMS_INPUT \ 1709 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 2466 2467 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); 2468 return 0; 2469 } 2470 2471 #define HDSP_ADAT_SYNC_CHECK \ 2472 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 1710 2473 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1711 .info = snd_hdsp_info_rms_input, \ 1712 .get = snd_hdsp_get_rms_input \ 1713 } 1714 1715 static int snd_hdsp_info_rms_input(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1716 { 1717 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER64; 1718 uinfo->count = 1; 1719 return 0; 1720 } 1721 1722 static int snd_hdsp_get_rms_input(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1723 { 2474 .info = snd_hdsp_info_sync_check, \ 2475 .get = snd_hdsp_get_adat_sync_check \ 2476 } 2477 2478 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx) 2479 { 2480 int status = hdsp_read(hdsp, HDSP_statusRegister); 2481 2482 if (status & (HDSP_Lock0>>idx)) { 2483 if (status & (HDSP_Sync0>>idx)) { 2484 return 2; 2485 } else { 2486 return 1; 2487 } 2488 } else { 2489 return 0; 2490 } 2491 } 2492 2493 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2494 { 2495 int offset; 1724 2496 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1725 ucontrol->value.integer64.value[0] = hdsp_read64 (hdsp, HDSP_inputRmsLevel + (8 * (ucontrol->id.index-1))); 1726 return 0; 1727 } 1728 1729 #define HDSP_RMS_PLAYBACK \ 1730 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ 1731 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 1732 .info = snd_hdsp_info_rms_playback, \ 1733 .get = snd_hdsp_get_rms_playback \ 1734 } 1735 1736 static int snd_hdsp_info_rms_playback(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1737 { 1738 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER64; 1739 uinfo->count = 1; 1740 return 0; 1741 } 1742 1743 static int snd_hdsp_get_rms_playback(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1744 { 1745 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol); 1746 ucontrol->value.integer64.value[0] = hdsp_read64 (hdsp, HDSP_playbackRmsLevel + (8 * (ucontrol->id.index-1))); 2497 2498 offset = ucontrol->id.index - 1; 2499 snd_assert(offset >= 0 || offset < ((hdsp->io_type == Digiface) ? 3 : 1), return -EINVAL); 2500 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); 1747 2501 return 0; 1748 2502 } … … 1771 2525 .get = snd_hdsp_control_spdif_mask_get, 1772 2526 .private_value = IEC958_AES0_NONAUDIO | 1773 IEC958_AES0_PROFESSIONAL |1774 IEC958_AES0_CON_EMPHASIS,2527 IEC958_AES0_PROFESSIONAL | 2528 IEC958_AES0_CON_EMPHASIS, 1775 2529 }, 1776 2530 { … … 1781 2535 .get = snd_hdsp_control_spdif_mask_get, 1782 2536 .private_value = IEC958_AES0_NONAUDIO | 1783 IEC958_AES0_PROFESSIONAL |1784 IEC958_AES0_PRO_EMPHASIS,2537 IEC958_AES0_PROFESSIONAL | 2538 IEC958_AES0_PRO_EMPHASIS, 1785 2539 }, 1786 2540 HDSP_MIXER("Mixer", 0), 1787 2541 HDSP_SPDIF_IN("IEC958 Input Connector", 0), 1788 2542 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), 1789 HDSP_SYNC_PREF("Preferred Sync Source", 0), 2543 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), 2544 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), 2545 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), 2546 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 2547 HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 2548 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 2549 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 2550 HDSP_AUTOSYNC_REF("AutoSync Reference", 0), 2551 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), 2552 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 2553 /* 'External Rate' complies with the alsa control naming scheme */ 2554 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 2555 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), 2556 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), 2557 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), 1790 2558 HDSP_PASSTHRU("Passthru", 0), 1791 2559 HDSP_LINE_OUT("Line Out", 0), … … 1795 2563 1796 2564 static snd_kcontrol_new_t snd_hdsp_playback_mixer = HDSP_PLAYBACK_MIXER; 1797 static snd_kcontrol_new_t snd_hdsp_input_peak = HDSP_PEAK_INPUT; 1798 static snd_kcontrol_new_t snd_hdsp_output_peak = HDSP_PEAK_OUTPUT; 1799 static snd_kcontrol_new_t snd_hdsp_playback_peak = HDSP_PEAK_PLAYBACK; 1800 static snd_kcontrol_new_t snd_hdsp_input_rms = HDSP_RMS_INPUT; 1801 static snd_kcontrol_new_t snd_hdsp_playback_rms = HDSP_RMS_PLAYBACK; 2565 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 2566 2567 2568 static int hdsp_update_simple_mixer_controls(hdsp_t *hdsp) 2569 { 2570 int i; 2571 2572 for (i = hdsp->ds_channels; i < hdsp->ss_channels; ++i) { 2573 if (hdsp->system_sample_rate > 48000) { 2574 hdsp->playback_mixer_ctls[i]->vd[0].access = SNDRV_CTL_ELEM_ACCESS_INACTIVE | 2575 SNDRV_CTL_ELEM_ACCESS_READ | 2576 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 2577 } else { 2578 hdsp->playback_mixer_ctls[i]->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 2579 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 2580 } 2581 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 2582 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->playback_mixer_ctls[i]->id); 2583 } 2584 2585 return 0; 2586 } 2587 1802 2588 1803 2589 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp) … … 1814 2600 } 1815 2601 1816 if (hdsp->type == Digiface) { 2602 snd_hdsp_playback_mixer.name = "Chn"; 2603 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 2604 2605 if (hdsp->io_type == Digiface) { 1817 2606 limit = DIGIFACE_SS_CHANNELS; 1818 2607 } else { 1819 2608 limit = MULTIFACE_SS_CHANNELS; 1820 2609 } 1821 2610 1822 2611 /* The index values are one greater than the channel ID so that alsamixer 1823 2612 will display them correctly. We want to use the index for fast lookup … … 1826 2615 */ 1827 2616 1828 snd_hdsp_playback_mixer.name = "Chn";1829 snd_hdsp_input_peak.name = "Input Peak";1830 snd_hdsp_output_peak.name = "Output Peak";1831 snd_hdsp_playback_peak.name = "Playback Peak";1832 snd_hdsp_playback_rms.name = "Playback RMS";1833 snd_hdsp_input_rms.name = "Input RMS";1834 1835 2617 for (idx = 0; idx < limit; ++idx) { 1836 2618 snd_hdsp_playback_mixer.index = idx+1; … … 1838 2620 return err; 1839 2621 } 1840 snd_hdsp_input_peak.index = idx+1; 1841 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_input_peak, hdsp)))) { 1842 return err; 1843 } 1844 snd_hdsp_output_peak.index = idx+1; 1845 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_output_peak, hdsp)))) { 1846 return err; 1847 } 1848 snd_hdsp_playback_peak.index = idx+1; 1849 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_playback_peak, hdsp)))) { 1850 return err; 1851 } 1852 snd_hdsp_playback_rms.index = idx+1; 1853 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_playback_rms, hdsp)))) { 1854 return err; 1855 } 1856 snd_hdsp_input_rms.index = idx+1; 1857 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_input_rms, hdsp)))) { 1858 return err; 2622 hdsp->playback_mixer_ctls[idx] = kctl; 2623 } 2624 2625 /* ADAT SyncCheck status */ 2626 snd_hdsp_adat_sync_check.index = 1; 2627 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) { 2628 return err; 2629 } 2630 if (hdsp->io_type == Digiface) { 2631 for (idx = 1; idx < 3; ++idx) { 2632 snd_hdsp_adat_sync_check.index = idx+1; 2633 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) { 2634 return err; 2635 } 1859 2636 } 1860 2637 } … … 1873 2650 unsigned int status; 1874 2651 unsigned int status2; 1875 char *requested_sync_ref; 2652 char *pref_sync_ref; 2653 char *autosync_ref; 2654 char *system_clock_mode; 2655 char *clock_source; 1876 2656 int x; 1877 2657 1878 2658 if (hdsp_check_for_iobox (hdsp)) { 2659 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n"); 1879 2660 return; 1880 2661 } 1881 2662 2663 if (hdsp_check_for_firmware(hdsp)) { 2664 if (hdsp->state & HDSP_FirmwareCached) { 2665 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 2666 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n"); 2667 return; 2668 } 2669 } else { 2670 snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n"); 2671 return; 2672 } 2673 } 2674 1882 2675 status = hdsp_read(hdsp, HDSP_statusRegister); 1883 2676 status2 = hdsp_read(hdsp, HDSP_status2Register); … … 1902 2695 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); 1903 2696 1904 snd_iprintf(buffer, " Latency: %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);2697 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); 1905 2698 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); 1906 2699 snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no"); … … 1909 2702 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); 1910 2703 1911 switch (hdsp_sync_pref (hdsp)) { 2704 snd_iprintf(buffer, "\n"); 2705 2706 2707 switch (hdsp_clock_source(hdsp)) { 2708 case HDSP_CLOCK_SOURCE_AUTOSYNC: 2709 clock_source = "AutoSync"; 2710 break; 2711 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 2712 clock_source = "Internal 32 kHz"; 2713 break; 2714 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 2715 clock_source = "Internal 44.1 kHz"; 2716 break; 2717 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 2718 clock_source = "Internal 48 kHz"; 2719 break; 2720 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 2721 clock_source = "Internal 64 kHz"; 2722 break; 2723 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 2724 clock_source = "Internal 88.2 kHz"; 2725 break; 2726 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 2727 clock_source = "Internal 96 kHz"; 2728 break; 2729 default: 2730 clock_source = "Error"; 2731 } 2732 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); 2733 2734 if (hdsp_system_clock_mode(hdsp)) { 2735 system_clock_mode = "Slave"; 2736 } else { 2737 system_clock_mode = "Master"; 2738 } 2739 2740 switch (hdsp_pref_sync_ref (hdsp)) { 1912 2741 case HDSP_SYNC_FROM_WORD: 1913 requested_sync_ref = "Word";2742 pref_sync_ref = "Word Clock"; 1914 2743 break; 1915 2744 case HDSP_SYNC_FROM_ADAT_SYNC: 1916 requested_sync_ref = "ADAT Sync";2745 pref_sync_ref = "ADAT Sync"; 1917 2746 break; 1918 2747 case HDSP_SYNC_FROM_SPDIF: 1919 requested_sync_ref = "SPDIF";2748 pref_sync_ref = "SPDIF"; 1920 2749 break; 1921 2750 case HDSP_SYNC_FROM_ADAT1: 1922 requested_sync_ref = "ADAT1";2751 pref_sync_ref = "ADAT1"; 1923 2752 break; 1924 2753 case HDSP_SYNC_FROM_ADAT2: 1925 requested_sync_ref = "ADAT2";2754 pref_sync_ref = "ADAT2"; 1926 2755 break; 1927 2756 case HDSP_SYNC_FROM_ADAT3: 1928 requested_sync_ref = "ADAT3"; 1929 break; 1930 case HDSP_SYNC_FROM_SELF: 2757 pref_sync_ref = "ADAT3"; 2758 break; 1931 2759 default: 1932 requested_sync_ref = "Master"; 1933 break; 1934 } 1935 1936 if ((hdsp->control_register & HDSP_ClockModeMaster)) { 1937 snd_iprintf (buffer, "Sync reference: %s/Master (chosen)\n", requested_sync_ref); 1938 } else if (hdsp_system_sample_rate(hdsp) == 0) { 1939 snd_iprintf (buffer, "Sync reference: %s/Master (forced)\n", requested_sync_ref); 1940 } else { 1941 switch (status2 & HDSP_SelSyncRefMask) { 1942 case HDSP_SelSyncRef_ADAT1: 1943 snd_iprintf (buffer, "Sync reference: %s/ADAT1\n", requested_sync_ref); 1944 break; 1945 case HDSP_SelSyncRef_ADAT2: 1946 snd_iprintf (buffer, "Sync reference: %s/ADAT2\n", requested_sync_ref); 1947 break; 1948 case HDSP_SelSyncRef_ADAT3: 1949 snd_iprintf (buffer, "Sync reference: %s/ADAT3\n", requested_sync_ref); 1950 break; 1951 case HDSP_SelSyncRef_SPDIF: 1952 snd_iprintf (buffer, "Sync reference: %s/SPDIF\n", requested_sync_ref); 1953 break; 1954 case HDSP_SelSyncRef_WORD: 1955 snd_iprintf (buffer, "Sync reference: %s/WORD\n", requested_sync_ref); 1956 break; 1957 case HDSP_SelSyncRef_ADAT_SYNC: 1958 snd_iprintf (buffer, "Sync reference: %s/ADAT Sync\n", requested_sync_ref); 1959 break; 1960 default: 1961 snd_iprintf (buffer, "Sync reference: %s/Master (fallback)\n", requested_sync_ref); 1962 break; 1963 } 1964 } 1965 snd_iprintf (buffer, "Sample rate: %d\n", hdsp_system_sample_rate(hdsp)); 1966 2760 pref_sync_ref = "Word Clock"; 2761 break; 2762 } 2763 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); 2764 2765 switch (hdsp_autosync_ref (hdsp)) { 2766 case HDSP_AUTOSYNC_FROM_WORD: 2767 autosync_ref = "Word Clock"; 2768 break; 2769 case HDSP_AUTOSYNC_FROM_ADAT_SYNC: 2770 autosync_ref = "ADAT Sync"; 2771 break; 2772 case HDSP_AUTOSYNC_FROM_SPDIF: 2773 autosync_ref = "SPDIF"; 2774 break; 2775 case HDSP_AUTOSYNC_FROM_NONE: 2776 autosync_ref = "None"; 2777 break; 2778 case HDSP_AUTOSYNC_FROM_ADAT1: 2779 autosync_ref = "ADAT1"; 2780 break; 2781 case HDSP_AUTOSYNC_FROM_ADAT2: 2782 autosync_ref = "ADAT2"; 2783 break; 2784 case HDSP_AUTOSYNC_FROM_ADAT3: 2785 autosync_ref = "ADAT3"; 2786 break; 2787 default: 2788 autosync_ref = "---"; 2789 break; 2790 } 2791 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); 2792 2793 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); 2794 2795 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 2796 2797 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 2798 1967 2799 snd_iprintf(buffer, "\n"); 1968 2800 … … 2005 2837 snd_iprintf(buffer, "IEC958 NonAudio: off\n"); 2006 2838 } 2007 2008 snd_iprintf(buffer, "\n");2009 2010 2839 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) { 2011 2840 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x); … … 2024 2853 } 2025 2854 2026 x = status & HDSP_Sync1;2027 if (status & HDSP_Lock1) {2028 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");2029 } else{2030 snd_iprintf(buffer, "ADAT2: No Lock\n");2031 }2032 2033 if (hdsp->type == Digiface) {2855 switch (hdsp->io_type) { 2856 case Digiface: 2857 x = status & HDSP_Sync1; 2858 if (status & HDSP_Lock1) { 2859 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); 2860 } else { 2861 snd_iprintf(buffer, "ADAT2: No Lock\n"); 2862 } 2034 2863 x = status & HDSP_Sync2; 2035 2864 if (status & HDSP_Lock2) { … … 2038 2867 snd_iprintf(buffer, "ADAT3: No Lock\n"); 2039 2868 } 2869 default: 2870 /* relax */ 2871 break; 2872 } 2873 2874 x = status & HDSP_SPDIFSync; 2875 if (status & HDSP_SPDIFErrorFlag) { 2876 snd_iprintf (buffer, "SPDIF: No Lock\n"); 2877 } else { 2878 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); 2879 } 2880 2881 x = status2 & HDSP_wc_sync; 2882 if (status2 & HDSP_wc_lock) { 2883 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); 2884 } else { 2885 snd_iprintf (buffer, "Word Clock: No Lock\n"); 2886 } 2887 2888 x = status & HDSP_TimecodeSync; 2889 if (status & HDSP_TimecodeLock) { 2890 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); 2891 } else { 2892 snd_iprintf(buffer, "ADAT Sync: No Lock\n"); 2040 2893 } 2041 2894 … … 2054 2907 snd_info_entry_t *entry; 2055 2908 2056 if ((entry = snd_info_create_card_entry(hdsp->card, "hdsp", hdsp->card->proc_root)) != 2057 NULL) { 2058 entry->content = SNDRV_INFO_CONTENT_TEXT; 2059 entry->private_data = hdsp; 2060 entry->mode = S_IFREG | S_IRUGO | S_IWUSR; 2061 entry->c.text.read_size = 256; 2062 entry->c.text.read = snd_hdsp_proc_read; 2063 if (snd_info_register(entry) < 0) { 2064 snd_info_free_entry(entry); 2065 entry = NULL; 2066 } 2067 } 2068 hdsp->proc_entry = entry; 2069 } 2070 2071 static void snd_hdsp_proc_done(hdsp_t *hdsp) 2072 { 2073 if (hdsp->proc_entry) { 2074 snd_info_unregister(hdsp->proc_entry); 2075 hdsp->proc_entry = NULL; 2076 } 2909 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) 2910 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read); 2077 2911 } 2078 2912 … … 2159 2993 } 2160 2994 2161 static voidsnd_hdsp_set_defaults(hdsp_t *hdsp)2995 static int snd_hdsp_set_defaults(hdsp_t *hdsp) 2162 2996 { 2163 2997 unsigned int i; … … 2192 3026 } 2193 3027 2194 for (i = 0; i < 2048; i++) 2195 hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN); 2196 2197 if (line_outs_monitor[hdsp->dev]) { 3028 for (i = 0; i < (hdsp_is_9652(hdsp) ? 1352 : HDSP_MATRIX_MIXER_SIZE); i++) { 3029 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) { 3030 return -EIO; 3031 } 3032 } 3033 3034 if (!hdsp_is_9652(hdsp) && line_outs_monitor[hdsp->dev]) { 2198 3035 2199 3036 snd_printk ("sending all inputs and playback streams to line outs.\n"); … … 2205 3042 for (i = 0; i < HDSP_MAX_CHANNELS; i++) { 2206 3043 if (i & 1) { 2207 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY (i, 26), UNITY_GAIN); 2208 hdsp_write_gain (hdsp, PLAYBACK_TO_OUTPUT_KEY (i, 26), UNITY_GAIN); 3044 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, 26), UNITY_GAIN) || 3045 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, 26), UNITY_GAIN)) { 3046 return -EIO; 3047 } 2209 3048 } else { 2210 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY (i, 27), UNITY_GAIN); 2211 hdsp_write_gain (hdsp, PLAYBACK_TO_OUTPUT_KEY (i, 27), UNITY_GAIN); 3049 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, 27), UNITY_GAIN) || 3050 hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, 27), UNITY_GAIN)) { 3051 return -EIO; 3052 } 2212 3053 } 2213 3054 } … … 2219 3060 */ 2220 3061 2221 hdsp_set_rate(hdsp, 48000); 2222 } 2223 2224 void snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs) 3062 hdsp_set_rate(hdsp, 48000, 1); 3063 3064 return 0; 3065 } 3066 3067 void hdsp_midi_tasklet(unsigned long arg) 3068 { 3069 hdsp_t *hdsp = (hdsp_t *)arg; 3070 3071 if (hdsp->midi[0].pending) { 3072 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3073 } 3074 if (hdsp->midi[1].pending) { 3075 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3076 } 3077 } 3078 3079 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs) 2225 3080 { 2226 3081 hdsp_t *hdsp = (hdsp_t *) dev_id; … … 2231 3086 unsigned int midi0status; 2232 3087 unsigned int midi1status; 2233 3088 int schedule = 0; 3089 2234 3090 status = hdsp_read(hdsp, HDSP_statusRegister); 2235 3091 … … 2239 3095 2240 3096 if (!audio && !midi0 && !midi1) { 2241 return ;3097 return IRQ_NONE; 2242 3098 } 2243 3099 … … 2246 3102 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; 2247 3103 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; 2248 3104 2249 3105 if (audio) { 2250 3106 if (hdsp->capture_substream) { … … 2256 3112 } 2257 3113 } 2258 2259 /* note: snd_hdsp_midi_input_read() calls output_write() because 2260 output is not interrupt-driven ... 2261 */ 2262 2263 if (midi0status) 2264 snd_hdsp_midi_input_read (&hdsp->midi[0]); 2265 if (midi1status) 2266 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3114 3115 if (midi0 && midi0status) { 3116 /* we disable interrupts for this input until processing is done */ 3117 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; 3118 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3119 hdsp->midi[0].pending = 1; 3120 schedule = 1; 3121 } 3122 if (midi1 && midi1status) { 3123 /* we disable interrupts for this input until processing is done */ 3124 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; 3125 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3126 hdsp->midi[1].pending = 1; 3127 schedule = 1; 3128 } 3129 if (schedule) 3130 tasklet_hi_schedule(&hdsp->midi_tasklet); 3131 return IRQ_HANDLED; 2267 3132 } 2268 3133 … … 2303 3168 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 2304 3169 snd_assert(channel_buf != NULL, return -EIO); 2305 if (copy_from_user(channel_buf + pos * 4, src, count * 4)) 2306 return -EFAULT; 3170 copy_from_user(channel_buf + pos * 4, src, count * 4); 2307 3171 return count; 2308 3172 } … … 2318 3182 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 2319 3183 snd_assert(channel_buf != NULL, return -EIO); 2320 if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) 2321 return -EFAULT; 3184 copy_to_user(dst, channel_buf + pos * 4, count * 4); 2322 3185 return count; 2323 3186 } … … 2349 3212 runtime->status->hw_ptr = 0; 2350 3213 if (other) { 2351 snd_pcm_substream_t *s = substream; 3214 struct list_head *pos; 3215 snd_pcm_substream_t *s; 2352 3216 snd_pcm_runtime_t *oruntime = other->runtime; 2353 do{2354 s = s ->link_next;3217 snd_pcm_group_for_each(pos, substream) { 3218 s = snd_pcm_group_substream_entry(pos); 2355 3219 if (s == other) { 2356 3220 oruntime->status->hw_ptr = runtime->status->hw_ptr; 2357 3221 break; 2358 3222 } 2359 } while (s != substream);3223 } 2360 3224 } 2361 3225 return 0; … … 2371 3235 2372 3236 if (hdsp_check_for_iobox (hdsp)) { 3237 return -EIO; 3238 } 3239 3240 if (hdsp_check_for_firmware(hdsp)) { 3241 if (hdsp->state & HDSP_FirmwareCached) { 3242 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3243 snd_printk("Firmware loading from cache failed, please upload manually.\n"); 3244 } 3245 } else { 3246 snd_printk("No firmware loaded nor cached, please upload firmware.\n"); 3247 } 2373 3248 return -EIO; 2374 3249 } … … 2393 3268 */ 2394 3269 2395 if ( (int)params_rate(params) != hdsp_system_sample_rate(hdsp)) {3270 if (params_rate(params) != hdsp->system_sample_rate) { 2396 3271 spin_unlock_irq(&hdsp->lock); 2397 3272 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); … … 2417 3292 */ 2418 3293 2419 if ((err = hdsp_set_rate(hdsp, params_rate(params) )) < 0) {3294 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { 2420 3295 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 2421 3296 return err; … … 2434 3309 { 2435 3310 hdsp_t *hdsp = _snd_pcm_substream_chip(substream); 2436 int chn;3311 int mapped_channel; 2437 3312 2438 3313 snd_assert(info->channel < HDSP_MAX_CHANNELS, return -EINVAL); 2439 3314 2440 if (( chn= hdsp->channel_map[info->channel]) < 0) {3315 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) { 2441 3316 return -EINVAL; 2442 3317 } 2443 3318 2444 info->offset = chn* HDSP_CHANNEL_BUFFER_BYTES;3319 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; 2445 3320 info->first = 0; 2446 3321 info->step = 32; … … 2475 3350 2476 3351 if (hdsp_check_for_iobox (hdsp)) { 3352 return -EIO; 3353 } 3354 3355 if (hdsp_check_for_firmware(hdsp)) { 3356 if (hdsp->state & HDSP_FirmwareCached) { 3357 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3358 snd_printk("Firmware loading from cache failed, please upload manually.\n"); 3359 } 3360 } else { 3361 snd_printk("No firmware loaded nor cached, please upload firmware.\n"); 3362 } 2477 3363 return -EIO; 2478 3364 } … … 2498 3384 2499 3385 if (other) { 2500 snd_pcm_substream_t *s = substream; 2501 do { 2502 s = s->link_next; 3386 struct list_head *pos; 3387 snd_pcm_substream_t *s; 3388 snd_pcm_group_for_each(pos, substream) { 3389 s = snd_pcm_group_substream_entry(pos); 2503 3390 if (s == other) { 2504 3391 snd_pcm_trigger_done(s, substream); … … 2509 3396 goto _ok; 2510 3397 } 2511 } while (s != substream);3398 } 2512 3399 if (cmd == SNDRV_PCM_TRIGGER_START) { 2513 3400 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && … … 2541 3428 2542 3429 if (hdsp_check_for_iobox (hdsp)) { 3430 return -EIO; 3431 } 3432 3433 if (hdsp_check_for_firmware(hdsp)) { 3434 if (hdsp->state & HDSP_FirmwareCached) { 3435 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3436 snd_printk("Firmware loading from cache failed, please upload manually.\n"); 3437 } 3438 } else { 3439 snd_printk("No firmware loaded nor cached, please upload firmware.\n"); 3440 } 2543 3441 return -EIO; 2544 3442 } … … 2567 3465 .rate_min = 32000, 2568 3466 .rate_max = 96000, 2569 .channels_min = 1 0,3467 .channels_min = 14, 2570 3468 .channels_max = HDSP_MAX_CHANNELS, 2571 3469 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 2572 .period_bytes_min = (64 * 4) * 10,3470 .period_bytes_min = (64 * 4) * 10, 2573 3471 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 2574 3472 .periods_min = 2, 2575 3473 .periods_max = 2, 2576 .fifo_size = 0 ,3474 .fifo_size = 0 2577 3475 }; 2578 3476 … … 2592 3490 .rate_min = 32000, 2593 3491 .rate_max = 96000, 2594 .channels_min = 1 0,3492 .channels_min = 14, 2595 3493 .channels_max = HDSP_MAX_CHANNELS, 2596 3494 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, … … 2599 3497 .periods_min = 2, 2600 3498 .periods_max = 2, 2601 .fifo_size = 0 ,3499 .fifo_size = 0 2602 3500 }; 2603 3501 … … 2679 3577 } 2680 3578 3579 if (hdsp_check_for_firmware(hdsp)) { 3580 if (hdsp->state & HDSP_FirmwareCached) { 3581 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3582 snd_printk("Firmware loading from cache failed, please upload manually.\n"); 3583 } 3584 } else { 3585 snd_printk("No firmware loaded nor cached, please upload firmware.\n"); 3586 } 3587 return -EIO; 3588 } 3589 2681 3590 spin_lock_irqsave(&hdsp->lock, flags); 2682 3591 … … 2710 3619 2711 3620 hdsp->creg_spdif_stream = hdsp->creg_spdif; 2712 hdsp->spdif_ctl-> access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;3621 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 2713 3622 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 2714 3623 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); … … 2728 3637 spin_unlock_irqrestore(&hdsp->lock, flags); 2729 3638 2730 hdsp->spdif_ctl-> access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;3639 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 2731 3640 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 2732 3641 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); … … 2742 3651 2743 3652 if (hdsp_check_for_iobox (hdsp)) { 3653 return -EIO; 3654 } 3655 3656 if (hdsp_check_for_firmware(hdsp)) { 3657 if (hdsp->state & HDSP_FirmwareCached) { 3658 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3659 snd_printk("Firmware loading from cache failed, please upload manually.\n"); 3660 } 3661 } else { 3662 snd_printk("No firmware loaded nor cached, please upload firmware.\n"); 3663 } 2744 3664 return -EIO; 2745 3665 } … … 2791 3711 } 2792 3712 3713 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file) 3714 { 3715 /* we have nothing to initialize but the call is required */ 3716 return 0; 3717 } 3718 3719 3720 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg) 3721 { 3722 hdsp_t *hdsp = (hdsp_t *)hw->private_data; 3723 hdsp_peak_rms_t *peak_rms; 3724 hdsp_firmware_t *firmware; 3725 hdsp_mixer_t *mixer; 3726 hdsp_config_info_t info; 3727 hdsp_version_t hdsp_version; 3728 int i; 3729 int err; 3730 unsigned long flags; 3731 3732 switch (cmd) { 3733 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: 3734 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 3735 snd_printk("firmware needs to be uploaded to the card.\n"); 3736 return -EINVAL; 3737 } 3738 peak_rms = (hdsp_peak_rms_t *)arg; 3739 if (copy_to_user_fromio((void *)peak_rms->playback_peaks, hdsp->iobase+HDSP_playbackPeakLevel, 26*4) != 0) { 3740 return -EFAULT; 3741 } 3742 if (copy_to_user_fromio((void *)peak_rms->input_peaks, hdsp->iobase+HDSP_inputPeakLevel, 26*4) != 0) { 3743 return -EFAULT; 3744 } 3745 if (copy_to_user_fromio((void *)peak_rms->output_peaks, hdsp->iobase+HDSP_outputPeakLevel, 28*4) != 0) { 3746 return -EFAULT; 3747 } 3748 if (copy_to_user_fromio((void *)peak_rms->playback_rms, hdsp->iobase+HDSP_playbackRmsLevel, 26*8) != 0) { 3749 return -EFAULT; 3750 } 3751 if (copy_to_user_fromio((void *)peak_rms->input_rms, hdsp->iobase+HDSP_inputRmsLevel, 26*8) != 0) { 3752 return -EFAULT; 3753 } 3754 break; 3755 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: 3756 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 3757 snd_printk("Firmware needs to be uploaded to the card.\n"); 3758 return -EINVAL; 3759 } 3760 spin_lock_irqsave(&hdsp->lock, flags); 3761 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 3762 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 3763 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 3764 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 3765 for (i = 0; i < ((hdsp->io_type != Multiface) ? 3 : 1); ++i) { 3766 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 3767 } 3768 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); 3769 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); 3770 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); 3771 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); 3772 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); 3773 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); 3774 info.system_sample_rate = hdsp->system_sample_rate; 3775 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); 3776 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); 3777 info.clock_source = (unsigned char)hdsp_clock_source(hdsp); 3778 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); 3779 info.line_out = (unsigned char)hdsp_line_out(hdsp); 3780 info.passthru = (unsigned char)hdsp->passthru; 3781 spin_unlock_irqrestore(&hdsp->lock, flags); 3782 if (copy_to_user((void *)arg, &info, sizeof(info))) 3783 return -EFAULT; 3784 break; 3785 case SNDRV_HDSP_IOCTL_GET_VERSION: 3786 if (hdsp_is_9652(hdsp)) return -EINVAL; 3787 if (hdsp->io_type == Undefined) { 3788 if ((err = hdsp_get_iobox_version(hdsp)) < 0) { 3789 return err; 3790 } 3791 } 3792 hdsp_version.io_type = hdsp->io_type; 3793 hdsp_version.firmware_rev = hdsp->firmware_rev; 3794 if ((err = copy_to_user((void *)arg, &hdsp_version, sizeof(hdsp_version)))) { 3795 return -EFAULT; 3796 } 3797 break; 3798 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: 3799 if (hdsp_is_9652(hdsp)) return -EINVAL; 3800 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 3801 if (hdsp->io_type == Undefined) return -EINVAL; 3802 3803 snd_printk("initializing firmware upload\n"); 3804 firmware = (hdsp_firmware_t *)arg; 3805 3806 if (hdsp_check_for_iobox (hdsp)) { 3807 return -EIO; 3808 } 3809 3810 if (copy_from_user(hdsp->firmware_cache, firmware->firmware_data, sizeof(unsigned long)*24413) != 0) { 3811 return -EFAULT; 3812 } 3813 3814 hdsp->state |= HDSP_FirmwareCached; 3815 3816 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) { 3817 return err; 3818 } 3819 3820 3821 if (!(hdsp->state & HDSP_InitializationComplete)) { 3822 snd_hdsp_initialize_channels(hdsp); 3823 3824 snd_hdsp_initialize_midi_flush(hdsp); 3825 3826 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 3827 snd_printk("error creating alsa devices\n"); 3828 return err; 3829 } 3830 } 3831 break; 3832 case SNDRV_HDSP_IOCTL_GET_MIXER: 3833 mixer = (hdsp_mixer_t *)arg; 3834 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) 3835 return -EFAULT; 3836 break; 3837 default: 3838 return -EINVAL; 3839 } 3840 return 0; 3841 } 3842 2793 3843 static snd_pcm_ops_t snd_hdsp_playback_ops = { 2794 3844 .open = snd_hdsp_playback_open, … … 2814 3864 }; 2815 3865 3866 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card, 3867 hdsp_t *hdsp) 3868 { 3869 snd_hwdep_t *hw; 3870 int err; 3871 3872 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) 3873 return err; 3874 3875 hdsp->hwdep = hw; 3876 hw->private_data = hdsp; 3877 strcpy(hw->name, "HDSP hwdep interface"); 3878 3879 hw->ops.open = snd_hdsp_hwdep_dummy_op; 3880 hw->ops.ioctl = snd_hdsp_hwdep_ioctl; 3881 hw->ops.release = snd_hdsp_hwdep_dummy_op; 3882 3883 return 0; 3884 } 3885 2816 3886 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, 2817 3887 hdsp_t *hdsp) … … 2835 3905 } 2836 3906 2837 static in t __devinit snd_hdsp_initialize_firmware (hdsp_t *hdsp)3907 static inline int snd_hdsp_initialize_input_enable (hdsp_t *hdsp) 2838 3908 { 2839 3909 int i; 2840 u32 *firmware_ptr; 2841 2842 if (hdsp_check_for_iobox (hdsp)) { 2843 return -EIO; 2844 } 2845 3910 2846 3911 if (hdsp_fifo_wait (hdsp, 0, 100)) { 2847 3912 return -EIO; 2848 3913 } 2849 3914 2850 /* enable all channels */2851 2852 3915 for (i = 0; i < HDSP_MAX_CHANNELS; ++i) { 2853 3916 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 2854 3917 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); 2855 3918 } 2856 2857 if (force_firmware[hdsp->dev] || (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 2858 2859 snd_printk ("loading firmware\n"); 2860 2861 hdsp_write (hdsp, HDSP_jtagReg, HDSP_PROGRAM); 2862 hdsp_write (hdsp, HDSP_fifoData, 0); 2863 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) { 2864 snd_printk ("timeout waiting for firmware setup\n"); 2865 return -EIO; 2866 } 2867 2868 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD); 2869 hdsp_write (hdsp, HDSP_fifoData, 0); 2870 2871 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { 2872 hdsp->type = Multiface; 2873 hdsp_write (hdsp, HDSP_jtagReg, HDSP_VERSION_BIT); 2874 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD); 2875 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); 2876 } else { 2877 hdsp->type = Digiface; 2878 } 2879 2880 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_PROGRAM); 2881 hdsp_write (hdsp, HDSP_fifoData, 0); 2882 2883 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 2884 snd_printk ("timeout waiting for download preparation\n"); 2885 return -EIO; 2886 } 2887 2888 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD); 2889 2890 if (hdsp->type == Digiface) { 2891 firmware_ptr = (u32 *) digiface_firmware; 2892 } else { 2893 firmware_ptr = (u32 *) multiface_firmware; 2894 } 2895 2896 for (i = 0; i < 24413; ++i) { 2897 hdsp_write(hdsp, HDSP_fifoData, firmware_ptr[i]); 2898 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 2899 snd_printk ("timeout during firmware loading\n"); 2900 return -EIO; 2901 } 2902 } 2903 2904 if (hdsp_fifo_wait (hdsp, 3, HDSP_LONG_WAIT)) { 2905 snd_printk ("timeout at end of firmware loading\n"); 2906 return -EIO; 2907 } 2908 2909 } else { 2910 2911 /* firmware already loaded, but we need to know what type 2912 of I/O box is connected. 2913 */ 2914 2915 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) { 2916 hdsp->type = Multiface; 2917 } else { 2918 hdsp->type = Digiface; 2919 } 2920 } 2921 2922 if (hdsp->type == Digiface) { 2923 snd_printk ("I/O Box is a Digiface\n"); 2924 hdsp->card_name = "RME Hammerfall DSP (Digiface)"; 3919 3920 return 0; 3921 } 3922 3923 static inline void snd_hdsp_initialize_channels(hdsp_t *hdsp) 3924 { 3925 if (hdsp->io_type == Digiface) { 3926 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 2925 3927 hdsp->ss_channels = DIGIFACE_SS_CHANNELS; 2926 3928 hdsp->ds_channels = DIGIFACE_DS_CHANNELS; 2927 3929 } else { 2928 snd_printk ("I/O Box is a Multiface\n"); 2929 hdsp->card_name = "RME Hammerfall DSP (Multiface)"; 3930 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 2930 3931 hdsp->ss_channels = MULTIFACE_SS_CHANNELS; 2931 3932 hdsp->ds_channels = MULTIFACE_DS_CHANNELS; 2932 3933 } 2933 3934 } 3935 3936 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp) 3937 { 2934 3938 snd_hdsp_flush_midi_input (hdsp, 0); 2935 3939 snd_hdsp_flush_midi_input (hdsp, 1); … … 2938 3942 hdsp_write(hdsp, HDSP_jtagReg, HDSP_BIGENDIAN_MODE); 2939 3943 #endif 2940 3944 } 3945 3946 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp) 3947 { 3948 int err; 3949 3950 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { 3951 return err; 3952 } 3953 3954 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { 3955 return err; 3956 } 3957 3958 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { 3959 return err; 3960 } 3961 3962 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { 3963 return err; 3964 } 3965 3966 snd_hdsp_proc_init(hdsp); 3967 3968 hdsp->last_spdif_sample_rate = -1; 3969 hdsp->system_sample_rate = -1; 3970 hdsp->last_external_sample_rate = -1; 3971 hdsp->last_internal_sample_rate = -1; 3972 hdsp->playback_pid = -1; 3973 hdsp->capture_pid = -1; 3974 hdsp->capture_substream = NULL; 3975 hdsp->playback_substream = NULL; 3976 3977 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { 3978 return err; 3979 } 3980 3981 hdsp_update_simple_mixer_controls(hdsp); 3982 3983 if (!(hdsp->state & HDSP_InitializationComplete)) { 3984 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 3985 hdsp->port, hdsp->irq); 3986 3987 if ((err = snd_card_register(card)) < 0) { 3988 snd_printk("error registering card\n"); 3989 return err; 3990 } 3991 hdsp->state |= HDSP_InitializationComplete; 3992 } 3993 2941 3994 return 0; 2942 3995 } … … 2948 4001 struct pci_dev *pci = hdsp->pci; 2949 4002 int err; 2950 unsigned short rev;4003 int i; 2951 4004 2952 4005 hdsp->irq = -1; 4006 hdsp->state = 0; 2953 4007 hdsp->midi[0].rmidi = 0; 2954 4008 hdsp->midi[1].rmidi = 0; … … 2961 4015 hdsp->iobase = 0; 2962 4016 hdsp->res_port = 0; 4017 hdsp->io_type = Undefined; 4018 for (i = 0; i < HDSP_MAX_CHANNELS; ++i) 4019 hdsp->playback_mixer_ctls[i] = 0; 2963 4020 2964 4021 hdsp->card = card; … … 2966 4023 spin_lock_init(&hdsp->lock); 2967 4024 2968 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &rev); 4025 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); 4026 4027 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); 2969 4028 strcpy(card->driver, "H-DSP"); 2970 4029 strcpy(card->mixername, "Xilinx FPGA"); 2971 4030 2972 switch ( rev & 0xff) {4031 switch (hdsp->firmware_rev & 0xff) { 2973 4032 case 0xa: 2974 4033 case 0xb: 4034 hdsp->card_name = "RME Hammerfall DSP"; 4035 break; 2975 4036 case 0x64: 2976 /* hdsp_initialize_firmware() will reset this */2977 hdsp->card_name = "RME Hammerfall DSP";2978 break;2979 4037 case 0x65: 4038 case 0x68: 4039 hdsp->card_name = "RME HDSP 9652"; 4040 break; 2980 4041 default: 2981 4042 return -ENODEV; … … 3010 4071 return err; 3011 4072 } 3012 3013 if ((err = snd_hdsp_initialize_firmware(hdsp)) < 0) { 4073 4074 if (hdsp_is_9652(hdsp)) { 4075 4076 if ((err = snd_hdsp_initialize_input_enable(hdsp)) != 0) { 4077 return err; 4078 } 4079 4080 hdsp->io_type = Digiface; 4081 4082 hdsp->ss_channels = DIGIFACE_SS_CHANNELS; 4083 hdsp->ds_channels = DIGIFACE_DS_CHANNELS; 4084 4085 snd_hdsp_initialize_midi_flush(hdsp); 4086 4087 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) { 4088 return err; 4089 } 4090 4091 } else { 4092 4093 if (hdsp_check_for_iobox (hdsp)) { 4094 /* no iobox connected, we defer initialization */ 4095 snd_printk("card initialization pending : waiting for firmware\n"); 4096 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) { 4097 return err; 4098 } 4099 return 0; 4100 } 4101 4102 if ((err = snd_hdsp_initialize_input_enable(hdsp)) != 0) { 4103 return err; 4104 } 4105 4106 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 4107 snd_printk("card initialization pending : waiting for firmware\n"); 4108 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) { 4109 return err; 4110 } 4111 return 0; 4112 } 4113 4114 snd_printk("Firmware already loaded, initializing card.\n"); 4115 4116 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) { 4117 hdsp->io_type = Multiface; 4118 } else { 4119 hdsp->io_type = Digiface; 4120 } 4121 4122 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) { 4123 return err; 4124 } 4125 4126 snd_hdsp_initialize_channels(hdsp); 4127 4128 snd_hdsp_initialize_midi_flush(hdsp); 4129 4130 } 4131 4132 hdsp->state |= HDSP_FirmwareLoaded; 4133 4134 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) { 3014 4135 return err; 3015 4136 } 3016 3017 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { 3018 return err; 3019 } 3020 3021 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { 3022 return err; 3023 } 3024 3025 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { 3026 return err; 3027 } 3028 3029 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { 3030 return err; 3031 } 3032 3033 snd_hdsp_proc_init(hdsp); 3034 3035 hdsp->last_spdif_sample_rate = -1; 3036 hdsp->last_adat_sample_rate = -1; 3037 hdsp->playback_pid = -1; 3038 hdsp->capture_pid = -1; 3039 hdsp->capture_substream = NULL; 3040 hdsp->playback_substream = NULL; 3041 3042 snd_hdsp_set_defaults(hdsp); 3043 3044 return 0; 4137 4138 return 0; 3045 4139 } 3046 4140 3047 4141 static int snd_hdsp_free(hdsp_t *hdsp) 3048 4142 { 3049 /* stop the audio, and cancel all interrupts */ 3050 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 3051 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 4143 if (hdsp->res_port) { 4144 /* stop the audio, and cancel all interrupts */ 4145 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 4146 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 4147 } 3052 4148 3053 4149 if (hdsp->irq >= 0) 3054 4150 free_irq(hdsp->irq, (void *)hdsp); 3055 4151 3056 snd_hdsp_proc_done(hdsp);3057 4152 snd_hdsp_free_buffers(hdsp); 3058 4153 … … 3124 4219 3125 4220 static struct pci_driver driver = { 3126 .name = "RME Hammerfall DSP",4221 .name = "RME Hammerfall DSP", 3127 4222 .id_table = snd_hdsp_ids, 3128 .probe = snd_hdsp_probe,4223 .probe = snd_hdsp_probe, 3129 4224 .remove = __devexit_p(snd_hdsp_remove), 3130 4225 }; -
GPL/branches/alsa-resync1/alsa-kernel/pci/rme9652/rme9652.c
r224 r246 1947 1947 } 1948 1948 1949 voidsnd_rme9652_interrupt(int irq, void *dev_id, struct pt_regs *regs)1949 static irqreturn_t snd_rme9652_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1950 1950 { 1951 1951 rme9652_t *rme9652 = (rme9652_t *) dev_id; 1952 1952 1953 1953 if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) { 1954 return ;1954 return IRQ_NONE; 1955 1955 } 1956 1956 … … 1964 1964 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); 1965 1965 } 1966 return IRQ_HANDLED; 1966 1967 } 1967 1968 … … 2054 2055 runtime->status->hw_ptr = 0; 2055 2056 if (other) { 2056 snd_pcm_substream_t *s = substream; 2057 struct list_head *pos; 2058 snd_pcm_substream_t *s; 2057 2059 snd_pcm_runtime_t *oruntime = other->runtime; 2058 do{2059 s = s ->link_next;2060 snd_pcm_group_for_each(pos, substream) { 2061 s = snd_pcm_group_substream_entry(pos); 2060 2062 if (s == other) { 2061 2063 oruntime->status->hw_ptr = runtime->status->hw_ptr; 2062 2064 break; 2063 2065 } 2064 } while (s != substream);2066 } 2065 2067 } 2066 2068 return 0; … … 2200 2202 2201 2203 if (other) { 2202 snd_pcm_substream_t *s = substream; 2203 do { 2204 s = s->link_next; 2204 struct list_head *pos; 2205 snd_pcm_substream_t *s; 2206 snd_pcm_group_for_each(pos, substream) { 2207 s = snd_pcm_group_substream_entry(pos); 2205 2208 if (s == other) { 2206 2209 snd_pcm_trigger_done(s, substream); … … 2211 2214 goto _ok; 2212 2215 } 2213 } while (s != substream);2216 } 2214 2217 if (cmd == SNDRV_PCM_TRIGGER_START) { 2215 2218 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && … … 2405 2408 2406 2409 rme9652->creg_spdif_stream = rme9652->creg_spdif; 2407 rme9652->spdif_ctl-> access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;2410 rme9652->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 2408 2411 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE | 2409 2412 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id); … … 2423 2426 spin_unlock_irqrestore(&rme9652->lock, flags); 2424 2427 2425 rme9652->spdif_ctl-> access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;2428 rme9652->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 2426 2429 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE | 2427 2430 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id); -
GPL/branches/alsa-resync1/alsa-kernel/pci/sonicvibes.c
r224 r246 602 602 } 603 603 604 static voidsnd_sonicvibes_interrupt(int irq, void *dev_id, struct pt_regs *regs)605 { 606 sonicvibes_t *sonic = snd_magic_cast(sonicvibes_t, dev_id, return );604 static irqreturn_t snd_sonicvibes_interrupt(int irq, void *dev_id, struct pt_regs *regs) 605 { 606 sonicvibes_t *sonic = snd_magic_cast(sonicvibes_t, dev_id, return IRQ_NONE); 607 607 unsigned char status; 608 608 609 609 status = inb(SV_REG(sonic, STATUS)); 610 610 if (!(status & (SV_DMAA_IRQ | SV_DMAC_IRQ | SV_MIDI_IRQ))) 611 return ;611 return IRQ_NONE; 612 612 if (status == 0xff) { /* failure */ 613 613 outb(sonic->irqmask = ~0, SV_REG(sonic, IRQMASK)); 614 614 snd_printk("IRQ failure - interrupts disabled!!\n"); 615 return ;615 return IRQ_HANDLED; 616 616 } 617 617 if (sonic->pcm) { … … 660 660 snd_ctl_notify(sonic->card, SNDRV_CTL_EVENT_MASK_VALUE, &sonic->master_volume->id); 661 661 } 662 return IRQ_HANDLED; 662 663 } 663 664 -
GPL/branches/alsa-resync1/alsa-kernel/pci/trident/trident_main.c
r224 r246 2715 2715 .name = "PCM Front Playback Volume", 2716 2716 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2717 .count = 32, 2717 2718 .info = snd_trident_pcm_vol_control_info, 2718 2719 .get = snd_trident_pcm_vol_control_get, … … 2776 2777 .name = "PCM Pan Playback Control", 2777 2778 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2779 .count = 32, 2778 2780 .info = snd_trident_pcm_pan_control_info, 2779 2781 .get = snd_trident_pcm_pan_control_get, … … 2829 2831 .name = "PCM Reverb Playback Volume", 2830 2832 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2833 .count = 32, 2831 2834 .info = snd_trident_pcm_rvol_control_info, 2832 2835 .get = snd_trident_pcm_rvol_control_get, -
GPL/branches/alsa-resync1/alsa-kernel/pci/ymfpci/ymfpci_main.c
r224 r246 1368 1368 { 1369 1369 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1370 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1371 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),1370 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1371 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1372 1372 .info = snd_ymfpci_spdif_stream_info, 1373 1373 .get = snd_ymfpci_spdif_stream_get,
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