| 1 | /*
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| 2 | * $Id: pci.h 142 2000-04-23 14:55:46Z ktk $
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| 3 | *
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| 4 | * PCI defines and function prototypes
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| 5 | * Copyright 1994, Drew Eckhardt
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| 6 | * Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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| 7 | *
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| 8 | * For more information, please consult the following manuals (look at
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| 9 | * http://www.pcisig.com/ for how to get them):
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| 10 | *
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| 11 | * PCI BIOS Specification
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| 12 | * PCI Local Bus Specification
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| 13 | * PCI to PCI Bridge Specification
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| 14 | * PCI System Design Guide
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| 15 | */
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| 16 |
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| 17 | #ifndef LINUX_PCI_H
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| 18 | #define LINUX_PCI_H
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| 19 |
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| 20 | /*
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| 21 | * Under PCI, each device has 256 bytes of configuration address space,
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| 22 | * of which the first 64 bytes are standardized as follows:
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| 23 | */
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| 24 | #define PCI_VENDOR_ID 0x00 /* 16 bits */
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| 25 | #define PCI_DEVICE_ID 0x02 /* 16 bits */
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| 26 | #define PCI_COMMAND 0x04 /* 16 bits */
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| 27 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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| 28 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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| 29 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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| 30 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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| 31 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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| 32 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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| 33 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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| 34 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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| 35 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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| 36 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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| 37 |
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| 38 | #define PCI_STATUS 0x06 /* 16 bits */
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| 39 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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| 40 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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| 41 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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| 42 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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| 43 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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| 44 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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| 45 | #define PCI_STATUS_DEVSEL_FAST 0x000
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| 46 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200
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| 47 | #define PCI_STATUS_DEVSEL_SLOW 0x400
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| 48 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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| 49 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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| 50 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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| 51 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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| 52 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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| 53 |
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| 54 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
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| 55 | revision */
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| 56 | #define PCI_REVISION_ID 0x08 /* Revision ID */
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| 57 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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| 58 | #define PCI_CLASS_DEVICE 0x0a /* Device class */
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| 59 |
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| 60 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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| 61 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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| 62 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */
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| 63 | #define PCI_HEADER_TYPE_NORMAL 0
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| 64 | #define PCI_HEADER_TYPE_BRIDGE 1
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| 65 | #define PCI_HEADER_TYPE_CARDBUS 2
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| 66 |
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| 67 | #define PCI_BIST 0x0f /* 8 bits */
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| 68 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */
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| 69 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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| 70 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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| 71 |
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| 72 | /*
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| 73 | * Base addresses specify locations in memory or I/O space.
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| 74 | * Decoded size can be determined by writing a value of
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| 75 | * 0xffffffff to the register, and reading it back. Only
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| 76 | * 1 bits are decoded.
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| 77 | */
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| 78 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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| 79 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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| 80 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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| 81 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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| 82 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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| 83 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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| 84 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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| 85 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01
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| 86 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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| 87 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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| 88 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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| 89 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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| 90 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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| 91 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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| 92 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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| 93 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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| 94 | /* bit 1 is reserved if address_space = 1 */
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| 95 |
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| 96 | /* Header type 0 (normal devices) */
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| 97 | #define PCI_CARDBUS_CIS 0x28
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| 98 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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| 99 | #define PCI_SUBSYSTEM_ID 0x2e
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| 100 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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| 101 | #define PCI_ROM_ADDRESS_ENABLE 0x01
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| 102 | #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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| 103 |
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| 104 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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| 105 |
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| 106 | /* 0x35-0x3b are reserved */
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| 107 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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| 108 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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| 109 | #define PCI_MIN_GNT 0x3e /* 8 bits */
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| 110 | #define PCI_MAX_LAT 0x3f /* 8 bits */
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| 111 |
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| 112 | /* Header type 1 (PCI-to-PCI bridges) */
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| 113 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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| 114 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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| 115 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
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| 116 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
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| 117 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
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| 118 | #define PCI_IO_LIMIT 0x1d
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| 119 | #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
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| 120 | #define PCI_IO_RANGE_TYPE_16 0x00
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| 121 | #define PCI_IO_RANGE_TYPE_32 0x01
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| 122 | #define PCI_IO_RANGE_MASK ~0x0f
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| 123 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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| 124 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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| 125 | #define PCI_MEMORY_LIMIT 0x22
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| 126 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
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| 127 | #define PCI_MEMORY_RANGE_MASK ~0x0f
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| 128 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
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| 129 | #define PCI_PREF_MEMORY_LIMIT 0x26
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| 130 | #define PCI_PREF_RANGE_TYPE_MASK 0x0f
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| 131 | #define PCI_PREF_RANGE_TYPE_32 0x00
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| 132 | #define PCI_PREF_RANGE_TYPE_64 0x01
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| 133 | #define PCI_PREF_RANGE_MASK ~0x0f
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| 134 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
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| 135 | #define PCI_PREF_LIMIT_UPPER32 0x2c
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| 136 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
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| 137 | #define PCI_IO_LIMIT_UPPER16 0x32
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| 138 | /* 0x34 same as for htype 0 */
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| 139 | /* 0x35-0x3b is reserved */
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| 140 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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| 141 | /* 0x3c-0x3d are same as for htype 0 */
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| 142 | #define PCI_BRIDGE_CONTROL 0x3e
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| 143 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
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| 144 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
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| 145 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
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| 146 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
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| 147 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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| 148 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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| 149 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
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| 150 |
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| 151 | /* Header type 2 (CardBus bridges) */
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| 152 | /* 0x14-0x15 reserved */
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| 153 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
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| 154 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
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| 155 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
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| 156 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
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| 157 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
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| 158 | #define PCI_CB_MEMORY_BASE_0 0x1c
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| 159 | #define PCI_CB_MEMORY_LIMIT_0 0x20
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| 160 | #define PCI_CB_MEMORY_BASE_1 0x24
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| 161 | #define PCI_CB_MEMORY_LIMIT_1 0x28
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| 162 | #define PCI_CB_IO_BASE_0 0x2c
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| 163 | #define PCI_CB_IO_BASE_0_HI 0x2e
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| 164 | #define PCI_CB_IO_LIMIT_0 0x30
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| 165 | #define PCI_CB_IO_LIMIT_0_HI 0x32
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| 166 | #define PCI_CB_IO_BASE_1 0x34
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| 167 | #define PCI_CB_IO_BASE_1_HI 0x36
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| 168 | #define PCI_CB_IO_LIMIT_1 0x38
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| 169 | #define PCI_CB_IO_LIMIT_1_HI 0x3a
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| 170 | #define PCI_CB_IO_RANGE_MASK ~0x03
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| 171 | /* 0x3c-0x3d are same as for htype 0 */
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| 172 | #define PCI_CB_BRIDGE_CONTROL 0x3e
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| 173 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
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| 174 | #define PCI_CB_BRIDGE_CTL_SERR 0x02
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| 175 | #define PCI_CB_BRIDGE_CTL_ISA 0x04
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| 176 | #define PCI_CB_BRIDGE_CTL_VGA 0x08
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| 177 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
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| 178 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
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| 179 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
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| 180 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
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| 181 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
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| 182 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
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| 183 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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| 184 | #define PCI_CB_SUBSYSTEM_ID 0x42
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| 185 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
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| 186 | /* 0x48-0x7f reserved */
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| 187 |
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| 188 | /* Capability lists */
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| 189 |
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| 190 | #define PCI_CAP_LIST_ID 0 /* Capability ID */
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| 191 | #define PCI_CAP_ID_PM 0x01 /* Power Management */
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| 192 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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| 193 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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| 194 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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| 195 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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| 196 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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| 197 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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| 198 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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| 199 | #define PCI_CAP_SIZEOF 4
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| 200 |
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| 201 | /* Power Management Registers */
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| 202 |
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| 203 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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| 204 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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| 205 | #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
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| 206 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
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| 207 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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| 208 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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| 209 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
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| 210 | #define PCI_PM_CTRL 4 /* PM control and status register */
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| 211 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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| 212 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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| 213 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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| 214 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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| 215 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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| 216 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
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| 217 | #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
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| 218 | #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
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| 219 | #define PCI_PM_DATA_REGISTER 7 /* (??) */
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| 220 | #define PCI_PM_SIZEOF 8
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| 221 |
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| 222 | /* AGP registers */
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| 223 |
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| 224 | #define PCI_AGP_VERSION 2 /* BCD version number */
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| 225 | #define PCI_AGP_RFU 3 /* Rest of capability flags */
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| 226 | #define PCI_AGP_STATUS 4 /* Status register */
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| 227 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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| 228 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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| 229 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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| 230 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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| 231 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
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| 232 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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| 233 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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| 234 | #define PCI_AGP_COMMAND 8 /* Control register */
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| 235 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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| 236 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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| 237 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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| 238 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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| 239 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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| 240 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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| 241 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
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| 242 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
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| 243 | #define PCI_AGP_SIZEOF 12
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| 244 |
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| 245 | /* Slot Identification */
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| 246 |
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| 247 | #define PCI_SID_ESR 2 /* Expansion Slot Register */
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| 248 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
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| 249 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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| 250 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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| 251 |
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| 252 | /* Message Signalled Interrupts registers */
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| 253 |
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| 254 | #define PCI_MSI_FLAGS 2 /* Various flags */
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| 255 | #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
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| 256 | #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
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| 257 | #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
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| 258 | #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
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| 259 | #define PCI_MSI_RFU 3 /* Rest of capability flags */
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| 260 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
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| 261 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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| 262 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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| 263 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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| 264 |
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| 265 | /* Include the ID list */
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| 266 |
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| 267 | #include <linux/pci_ids.h>
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| 268 |
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| 269 | /*
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| 270 | * The PCI interface treats multi-function devices as independent
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| 271 | * devices. The slot/function address of each device is encoded
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| 272 | * in a single byte as follows:
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| 273 | *
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| 274 | * 7:3 = slot
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| 275 | * 2:0 = function
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| 276 | */
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| 277 | #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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| 278 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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| 279 | #define PCI_FUNC(devfn) ((devfn) & 0x07)
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| 280 |
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| 281 | #ifdef __KERNEL__
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| 282 |
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| 283 | #include <linux/types.h>
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| 284 | #include <linux/ioport.h>
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| 285 |
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| 286 | #include <asm/pci.h>
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| 287 |
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| 288 | #define DEVICE_COUNT_COMPATIBLE 4
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| 289 | #define DEVICE_COUNT_IRQ 2
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| 290 | #define DEVICE_COUNT_DMA 2
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| 291 | #define DEVICE_COUNT_RESOURCE 12
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| 292 |
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| 293 | /*
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| 294 | * The pci_dev structure is used to describe both PCI and ISAPnP devices.
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| 295 | */
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| 296 | struct pci_dev {
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| 297 | int active; /* device is active */
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| 298 | int ro; /* Read/Only */
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| 299 |
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| 300 | struct pci_bus *bus; /* bus this device is on */
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| 301 | struct pci_dev *sibling; /* next device on this bus */
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| 302 | struct pci_dev *next; /* chain of all devices */
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| 303 |
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| 304 | void *sysdata; /* hook for sys-specific extension */
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| 305 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
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| 306 |
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| 307 | unsigned int devfn; /* encoded device & function index */
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| 308 | unsigned short vendor;
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| 309 | unsigned short device;
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| 310 | unsigned short subsystem_vendor;
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| 311 | unsigned short subsystem_device;
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| 312 | unsigned int _class; /* 3 bytes: (base,sub,prog-if) */
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| 313 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */
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| 314 | u8 rom_base_reg; /* Which config register controls the ROM */
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| 315 |
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| 316 | unsigned short regs;
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| 317 |
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| 318 | /* device is compatible with these IDs */
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| 319 | unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
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| 320 | unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
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| 321 |
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| 322 | /*
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| 323 | * Instead of touching interrupt line and base address registers
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| 324 | * directly, use the values stored here. They might be different!
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| 325 | */
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| 326 | unsigned int irq;
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| 327 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
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| 328 | struct resource dma_resource[DEVICE_COUNT_DMA];
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| 329 | struct resource irq_resource[DEVICE_COUNT_IRQ];
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| 330 |
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| 331 | char name[48]; /* Device name */
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| 332 | char slot_name[8]; /* Slot name */
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| 333 |
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| 334 | void *driver_data;
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| 335 | unsigned long dma_mask;
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| 336 |
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| 337 | int (*prepare)(struct pci_dev *dev);
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| 338 | int (*activate)(struct pci_dev *dev);
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| 339 | int (*deactivate)(struct pci_dev *dev);
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| 340 | };
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| 341 |
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| 342 | /*
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| 343 | * For PCI devices, the region numbers are assigned this way:
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| 344 | *
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| 345 | * 0-5 standard PCI regions
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| 346 | * 6 expansion ROM
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| 347 | * 7-10 bridges: address space assigned to buses behind the bridge
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| 348 | */
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| 349 |
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| 350 | #define PCI_ROM_RESOURCE 6
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| 351 | #define PCI_BRIDGE_RESOURCES 7
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| 352 | #define PCI_NUM_RESOURCES 11
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| 353 |
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| 354 | #define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
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| 355 |
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| 356 | struct pci_bus {
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| 357 | struct pci_bus *parent; /* parent bus this bridge is on */
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| 358 | struct pci_bus *children; /* chain of P2P bridges on this bus */
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| 359 | struct pci_bus *next; /* chain of all PCI buses */
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| 360 | struct pci_ops *ops; /* configuration access functions */
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| 361 |
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| 362 | struct pci_dev *self; /* bridge device as seen by parent */
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| 363 | struct pci_dev *devices; /* devices behind this bridge */
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| 364 | struct resource *resource[4]; /* address space routed to this bus */
|
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| 365 |
|
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| 366 | void *sysdata; /* hook for sys-specific extension */
|
|---|
| 367 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
|
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| 368 |
|
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| 369 | unsigned char number; /* bus number */
|
|---|
| 370 | unsigned char primary; /* number of primary bridge */
|
|---|
| 371 | unsigned char secondary; /* number of secondary bridge */
|
|---|
| 372 | unsigned char subordinate; /* max number of subordinate buses */
|
|---|
| 373 |
|
|---|
| 374 | char name[48];
|
|---|
| 375 | unsigned short vendor;
|
|---|
| 376 | unsigned short device;
|
|---|
| 377 | unsigned int serial; /* serial number */
|
|---|
| 378 | unsigned char pnpver; /* Plug & Play version */
|
|---|
| 379 | unsigned char productver; /* product version */
|
|---|
| 380 | unsigned char checksum; /* if zero - checksum passed */
|
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| 381 | unsigned char pad1;
|
|---|
| 382 | };
|
|---|
| 383 |
|
|---|
| 384 | //extern struct pci_bus *pci_root; /* root bus */
|
|---|
| 385 | //extern struct pci_dev *pci_devices; /* list of all devices */
|
|---|
| 386 |
|
|---|
| 387 | /*
|
|---|
| 388 | * Error values that may be returned by PCI functions.
|
|---|
| 389 | */
|
|---|
| 390 | #define PCIBIOS_SUCCESSFUL 0x00
|
|---|
| 391 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
|
|---|
| 392 | #define PCIBIOS_BAD_VENDOR_ID 0x83
|
|---|
| 393 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86
|
|---|
| 394 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
|
|---|
| 395 | #define PCIBIOS_SET_FAILED 0x88
|
|---|
| 396 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89
|
|---|
| 397 |
|
|---|
| 398 | /* Low-level architecture-dependent routines */
|
|---|
| 399 |
|
|---|
| 400 | struct pci_ops {
|
|---|
| 401 | int (*read_byte)(struct pci_dev *, int where, u8 *val);
|
|---|
| 402 | int (*read_word)(struct pci_dev *, int where, u16 *val);
|
|---|
| 403 | int (*read_dword)(struct pci_dev *, int where, u32 *val);
|
|---|
| 404 | int (*write_byte)(struct pci_dev *, int where, u8 val);
|
|---|
| 405 | int (*write_word)(struct pci_dev *, int where, u16 val);
|
|---|
| 406 | int (*write_dword)(struct pci_dev *, int where, u32 val);
|
|---|
| 407 | };
|
|---|
| 408 |
|
|---|
| 409 | void pcibios_init(void);
|
|---|
| 410 | void pcibios_fixup_bus(struct pci_bus *);
|
|---|
| 411 | int pcibios_enable_device(struct pci_dev *);
|
|---|
| 412 | char *pcibios_setup (char *str);
|
|---|
| 413 |
|
|---|
| 414 | void pcibios_update_resource(struct pci_dev *, struct resource *,
|
|---|
| 415 | struct resource *, int);
|
|---|
| 416 | void pcibios_update_irq(struct pci_dev *, int irq);
|
|---|
| 417 |
|
|---|
| 418 | /* Backward compatibility, don't use in new code! */
|
|---|
| 419 |
|
|---|
| 420 | int pcibios_present(void);
|
|---|
| 421 | #define pci_present pcibios_present
|
|---|
| 422 | int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
|
|---|
| 423 | unsigned char where, unsigned char *val);
|
|---|
| 424 | int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
|
|---|
| 425 | unsigned char where, unsigned short *val);
|
|---|
| 426 | int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
|
|---|
| 427 | unsigned char where, unsigned int *val);
|
|---|
| 428 | int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
|
|---|
| 429 | unsigned char where, unsigned char val);
|
|---|
| 430 | int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
|
|---|
| 431 | unsigned char where, unsigned short val);
|
|---|
| 432 | int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
|
|---|
| 433 | unsigned char where, unsigned int val);
|
|---|
| 434 | int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
|
|---|
| 435 | int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
|
|---|
| 436 | unsigned short index, unsigned char *bus,
|
|---|
| 437 | unsigned char *dev_fn);
|
|---|
| 438 |
|
|---|
| 439 | /* Generic PCI interface functions */
|
|---|
| 440 |
|
|---|
| 441 | void pci_init(void);
|
|---|
| 442 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
|
|---|
| 443 | int pci_proc_attach_device(struct pci_dev *dev);
|
|---|
| 444 | int pci_proc_detach_device(struct pci_dev *dev);
|
|---|
| 445 | void pci_name_device(struct pci_dev *dev);
|
|---|
| 446 | void pci_read_bridge_bases(struct pci_bus *child);
|
|---|
| 447 | struct resource *pci_find_parent_resource(struct pci_dev *dev, struct resource *res);
|
|---|
| 448 |
|
|---|
| 449 | struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
|
|---|
| 450 | struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
|
|---|
| 451 | unsigned int ss_vendor, unsigned int ss_device,
|
|---|
| 452 | struct pci_dev *from);
|
|---|
| 453 | struct pci_dev *pci_find_class (unsigned int _class, struct pci_dev *from);
|
|---|
| 454 | struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
|
|---|
| 455 | int pci_find_capability (struct pci_dev *dev, int cap);
|
|---|
| 456 | int pci_dma_supported(struct pci_dev *dev, unsigned long mask);
|
|---|
| 457 |
|
|---|
| 458 | #define PCI_ANY_ID (~0)
|
|---|
| 459 |
|
|---|
| 460 | int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
|
|---|
| 461 | int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
|
|---|
| 462 | int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
|
|---|
| 463 | int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
|
|---|
| 464 | int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
|
|---|
| 465 | int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
|
|---|
| 466 | int pci_enable_device(struct pci_dev *dev);
|
|---|
| 467 | void pci_set_master(struct pci_dev *dev);
|
|---|
| 468 | int pci_set_power_state(struct pci_dev *dev, int state);
|
|---|
| 469 |
|
|---|
| 470 | /* Helper functions for low-level code (drivers/pci/setup.c) */
|
|---|
| 471 |
|
|---|
| 472 | int pci_claim_resource(struct pci_dev *, int);
|
|---|
| 473 | void pci_assign_unassigned_resources(u32 min_io, u32 min_mem);
|
|---|
| 474 | void pci_set_bus_ranges(void);
|
|---|
| 475 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
|
|---|
| 476 | int (*)(struct pci_dev *, u8, u8));
|
|---|
| 477 |
|
|---|
| 478 | /*
|
|---|
| 479 | * simple PCI probing for drivers (drivers/pci/helper.c)
|
|---|
| 480 | */
|
|---|
| 481 |
|
|---|
| 482 | struct pci_simple_probe_entry;
|
|---|
| 483 | typedef int (*pci_simple_probe_callback) (struct pci_dev *dev, int match_num,
|
|---|
| 484 | const struct pci_simple_probe_entry *ent,
|
|---|
| 485 | void *drvr_data);
|
|---|
| 486 |
|
|---|
| 487 | struct pci_simple_probe_entry {
|
|---|
| 488 | unsigned short vendor; /* vendor id, PCI_ANY_ID, or 0 for last entry */
|
|---|
| 489 | unsigned short device; /* device id, PCI_ANY_ID, or 0 for last entry */
|
|---|
| 490 | unsigned short subsys_vendor; /* subsystem vendor id, 0 for don't care */
|
|---|
| 491 | unsigned short subsys_device; /* subsystem device id, 0 for don't care */
|
|---|
| 492 | void *dev_data; /* driver-private, entry-specific data */
|
|---|
| 493 | };
|
|---|
| 494 |
|
|---|
| 495 | int pci_simple_probe (const struct pci_simple_probe_entry *list,
|
|---|
| 496 | size_t match_limit, pci_simple_probe_callback cb,
|
|---|
| 497 | void *drvr_data);
|
|---|
| 498 |
|
|---|
| 499 |
|
|---|
| 500 |
|
|---|
| 501 | /*
|
|---|
| 502 | * If the system does not have PCI, clearly these return errors. Define
|
|---|
| 503 | * these as simple inline functions to avoid hair in drivers.
|
|---|
| 504 | */
|
|---|
| 505 |
|
|---|
| 506 | /*
|
|---|
| 507 | * The world is not perfect and supplies us with broken PCI devices.
|
|---|
| 508 | * For at least a part of these bugs we need a work-around, so both
|
|---|
| 509 | * generic (drivers/pci/quirks.c) and per-architecture code can define
|
|---|
| 510 | * fixup hooks to be called for particular buggy devices.
|
|---|
| 511 | */
|
|---|
| 512 |
|
|---|
| 513 | struct pci_fixup {
|
|---|
| 514 | int pass;
|
|---|
| 515 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */
|
|---|
| 516 | void (*hook)(struct pci_dev *dev);
|
|---|
| 517 | };
|
|---|
| 518 |
|
|---|
| 519 | extern struct pci_fixup pcibios_fixups[];
|
|---|
| 520 |
|
|---|
| 521 | #define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
|
|---|
| 522 | #define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
|
|---|
| 523 |
|
|---|
| 524 | void pci_fixup_device(int pass, struct pci_dev *dev);
|
|---|
| 525 |
|
|---|
| 526 | extern int pci_pci_problems;
|
|---|
| 527 | #define PCIPCI_FAIL 1
|
|---|
| 528 | #define PCIPCI_TRITON 2
|
|---|
| 529 | #define PCIPCI_NATOMA 4
|
|---|
| 530 |
|
|---|
| 531 |
|
|---|
| 532 | struct pci_device_id {
|
|---|
| 533 | unsigned int vendor, device;
|
|---|
| 534 | unsigned int subvendor, subdevice;
|
|---|
| 535 | unsigned int class, class_mask;
|
|---|
| 536 | unsigned long driver_data;
|
|---|
| 537 | };
|
|---|
| 538 |
|
|---|
| 539 | struct pci_driver {
|
|---|
| 540 | struct list_head node;
|
|---|
| 541 | char *name;
|
|---|
| 542 | const struct pci_device_id *id_table;
|
|---|
| 543 | int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
|
|---|
| 544 | void (*remove)(struct pci_dev *dev);
|
|---|
| 545 | void (*suspend)(struct pci_dev *dev);
|
|---|
| 546 | void (*resume)(struct pci_dev *dev);
|
|---|
| 547 | };
|
|---|
| 548 |
|
|---|
| 549 | int pci_register_driver(struct pci_driver *driver);
|
|---|
| 550 | #define pci_module_init pci_register_driver
|
|---|
| 551 |
|
|---|
| 552 | int pci_unregister_driver(struct pci_driver *driver);
|
|---|
| 553 |
|
|---|
| 554 | #endif /* __KERNEL__ */
|
|---|
| 555 | #endif /* LINUX_PCI_H */
|
|---|
