source: cmedia/trunk/Sblive/8010.h@ 354

Last change on this file since 354 was 354, checked in by stevenhl, 17 years ago

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1/* $Id: 8010.h,v 1.1 2000/04/23 14:55:41 ktk Exp $ */
2
3/*
4 **********************************************************************
5 * 8010.h
6 * Copyright 1999, 2000 Creative Labs, Inc.
7 *
8 **********************************************************************
9 *
10 * Date Author Summary of changes
11 * ---- ------ ------------------
12 * October 20, 1999 Bertrand Lee base code release
13 * November 2, 1999 Alan Cox Cleaned of 8bit chars, DOS
14 * line endings
15 * December 8, 1999 Jon Taylor Added lots of new register info
16 *
17 **********************************************************************
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public
30 * License along with this program; if not, write to the Free
31 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
32 * USA.
33 *
34 *
35 **********************************************************************
36 */
37
38
39#ifndef _8010_H
40#define _8010_H
41
42/* ------------------- DEFINES -------------------- */
43
44#define EMUPAGESIZE 4096 /* don't change */
45#define RESERVED 0
46#define NUM_G 64 /* use all channels */
47#define NUM_FXSENDS 4 /* don't change */
48#define MAXPAGES (32768 * NUM_G / EMUPAGESIZE) /* WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE */
49
50#define TMEMSIZE 256*1024
51#define TMEMSIZEREG 4
52
53#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
54
55/************************************************************************************************/
56/* PCI function 0 registers, address = <val> + PCIBASE0 */
57/************************************************************************************************/
58
59#define PTR 0x00 /* Indexed register set pointer register */
60 /* NOTE: The CHANNELNUM and ADDRESS words can */
61 /* be modified independently of each other. */
62#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
63 /* channel number of the register to be */
64 /* accessed. For non per-channel registers the */
65 /* value should be set to zero. */
66#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
67
68#define DATA 0x04 /* Indexed register set data register */
69
70#define IPR 0x08 /* Global interrupt pending register */
71 /* Clear pending interrupts by writing a 1 to */
72 /* the relevant bits and zero to the other bits */
73#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
74#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
75#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
76#define IPR_PCIERROR 0x00200000 /* PCI bus error */
77#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
78#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
79#define IPR_MUTE 0x00040000 /* Mute button pressed */
80#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
81#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
82#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
83#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
84#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
85#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
86#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
87#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
88#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
89#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
90#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
91#define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */
92#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
93 /* Highest set channel in CLIPL or CLIPH. When */
94 /* IP is written with CL set, the bit in CLIPL */
95 /* or CLIPH corresponding to the CIN value */
96 /* written will be cleared. */
97
98#define INTE 0x0c /* Interrupt enable register */
99#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
100#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
101#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
102#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
103#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
104#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
105#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
106#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
107#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
108#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
109#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
110#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
111#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
112#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
113#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
114#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
115#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
116#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
117
118#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
119 /* NOTE: There is no reason to use this under */
120 /* Linux, and it will cause odd hardware */
121 /* behavior and possibly random segfaults and */
122 /* lockups if enabled. */
123
124#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
125 /* NOTE: This bit must always be enabled */
126#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
127#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
128#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
129#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
130#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
131#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
132#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
133#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
134#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
135#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
136#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
137#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
138#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
139
140#define WC 0x10 /* Wall Clock register */
141#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
142#define WC_SAMPLECOUNTER 0x14060010
143#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
144 /* NOTE: Each channel takes 1/64th of a sample */
145 /* period to be serviced. */
146
147#define HCFG 0x14 /* Hardware config register */
148 /* NOTE: There is no reason to use the legacy */
149 /* SoundBlaster emulation stuff described below */
150 /* under Linux, and all kinds of weird hardware */
151 /* behavior can result if you try. Don't. */
152#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
153#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
154#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
155#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
156#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
157#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
158#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
159#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
160#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
161#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
162#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
163#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
164 /* NOTE: The rest of the bits in this register */
165 /* _are_ relevant under Linux. */
166#define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
167#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
168#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
169#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
170#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
171#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
172#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
173#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
174 /* 1 = Force all 3 async digital inputs to use */
175 /* the same async sample rate tracker (ZVIDEO) */
176#define HCFG_AC3ENABLE_MASK 0x0x0000e0 /* AC3 async input control - Not implemented */
177#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
178#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
179#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
180 /* will automatically mute their output when */
181 /* they are not rate-locked to the external */
182 /* async audio source */
183#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
184 /* NOTE: This should generally never be used. */
185#define HCFG_LOCKTANKCACHE 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
186 /* NOTE: This should generally never be used. */
187#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
188 /* NOTE: This is a 'cheap' way to implement a */
189 /* master mute function on the mute button, and */
190 /* in general should not be used unless a more */
191 /* sophisticated master mute function has not */
192 /* been written. */
193#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
194 /* Should be set to 1 when the EMU10K1 is */
195 /* completely initialized. */
196
197#define MUDATA 0x18 /* MPU401 data register (8 bits) */
198
199#define MUCMD 0x19 /* MPU401 command register (8 bits) */
200#define MUCMD_RESET 0xff /* RESET command */
201#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
202 /* NOTE: All other commands are ignored */
203
204#define MUSTAT MUCMD /* MPU401 status register (8 bits) */
205#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
206#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
207
208#define TIMER 0x1a /* Timer terminal count register */
209 /* NOTE: After the rate is changed, a maximum */
210 /* of 1024 sample periods should be allowed */
211 /* before the new rate is guaranteed accurate. */
212#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
213 /* 0 == 1024 periods, [1..4] are not useful */
214#define TIMER_RATE 0x0a00001a
215
216#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
217
218#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
219#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
220#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
221
222/************************************************************************************************/
223/* PCI function 1 registers, address = <val> + PCIBASE1 */
224/************************************************************************************************/
225
226#define JOYSTICK1 0x00 /* Analog joystick port register */
227#define JOYSTICK2 0x01 /* Analog joystick port register */
228#define JOYSTICK3 0x02 /* Analog joystick port register */
229#define JOYSTICK4 0x03 /* Analog joystick port register */
230#define JOYSTICK5 0x04 /* Analog joystick port register */
231#define JOYSTICK6 0x05 /* Analog joystick port register */
232#define JOYSTICK7 0x06 /* Analog joystick port register */
233#define JOYSTICK8 0x07 /* Analog joystick port register */
234
235/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
236/* When reading, use these bitfields: */
237#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
238#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
239
240
241/********************************************************************************************************/
242/* AC97 pointer-offset register set, accessed through the AC97ADDRESS and AC97DATA registers */
243/********************************************************************************************************/
244
245#define AC97_RESET 0x00
246#define AC97_MASTERVOLUME 0x02 /* Master volume */
247#define AC97_HEADPHONEVOLUME 0x04 /* Headphone volume */
248#define AC97_MASTERVOLUMEMONO 0x06 /* Mast volume mono */
249#define AC97_MASTERTONE 0x08
250#define AC97_PCBEEPVOLUME 0x0a /* PC speaker system beep volume */
251#define AC97_PHONEVOLUME 0x0c
252#define AC97_MICVOLUME 0x0e
253#define AC97_LINEINVOLUME 0x10
254#define AC97_CDVOLUME 0x12
255#define AC97_VIDEOVOLUME 0x14
256#define AC97_AUXVOLUME 0x16
257#define AC97_PCMOUTVOLUME 0x18
258#define AC97_RECORDSELECT 0x1a
259#define AC97_RECORDGAIN 0x1c
260#define AC97_RECORDGAINMIC 0x1e
261#define AC97_GENERALPUPOSE 0x20
262#define AC97_3DCONTROL 0x22
263#define AC97_MODEMRATE 0x24
264#define AC97_POWERDOWN 0x26
265#define AC97_VENDORID1 0x7c
266#define AC97_VENDORID2 0x7e
267#define AC97_ZVIDEOVOLUME 0xec
268#define AC97_AC3VOLUME 0xed
269
270/********************************************************************************************************/
271/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
272/********************************************************************************************************/
273
274#define CPF 0x00 /* Current pitch and fraction register */
275#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
276#define CPF_CURRENTPITCH 0x10100000
277#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
278#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
279#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
280
281#define PTRX 0x01 /* Pitch target and send A/B amounts register */
282#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
283#define PTRX_PITCHTARGET 0x10100001
284#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
285#define PTRX_FXSENDAMOUNT_A 0x08080001
286#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
287#define PTRX_FXSENDAMOUNT_B 0x08000001
288
289#define CVCF 0x02 /* Current volume and filter cutoff register */
290#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
291#define CVCF_CURRENTVOL 0x10100002
292#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
293#define CVCF_CURRENTFILTER 0x10000002
294
295#define VTFT 0x03 /* Volume target and filter cutoff target register */
296#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
297#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
298
299#define Z1 0x05 /* Filter delay memory 1 register */
300
301#define Z2 0x04 /* Filter delay memory 2 register */
302
303#define PSST 0x06 /* Send C amount and loop start address register */
304#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
305
306#define PSST_FXSENDAMOUNT_C 0x08180006
307
308#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
309#define PSST_LOOPSTARTADDR 0x18000006
310
311#define DSL 0x07 /* Send D amount and loop start address register */
312#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
313
314#define DSL_FXSENDAMOUNT_D 0x08180007
315
316#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
317#define DSL_LOOPENDADDR 0x18000007
318
319#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
320#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
321#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
322 /* 1 == full band, 7 == lowpass */
323 /* ROM 0 is used when pitch shifting downward or less */
324 /* then 3 semitones upward. Increasingly higher ROM */
325 /* numbers are used, typically in steps of 3 semitones, */
326 /* as upward pitch shifting is performed. */
327#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
328#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
329#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
330#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
331#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
332#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
333#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
334#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
335#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
336#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
337#define CCCA_CURRADDR 0x18000008
338
339#define CCR 0x09 /* Cache control register */
340#define CCR_CACHEINVALIDSIZE 0xfe000000 /* Number of invalid samples cache for this channel */
341#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
342#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
343#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
344#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
345#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
346 /* NOTE: This is valid only if CACHELOOPFLAG is set */
347#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
348#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
349
350#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
351 /* NOTE: This register is normally not used */
352#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
353
354#define FXRT 0x0b /* Effects send routing register */
355 /* NOTE: It is illegal to assign the same routing to */
356 /* two effects sends. */
357#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
358#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
359#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
360#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
361
362#define MAPA 0x0c /* Cache map A */
363
364#define MAPB 0x0d /* Cache map B */
365
366#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
367#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
368
369#define ENVVOL 0x10 /* Volume envelope register */
370#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
371 /* 0x8000-n == 666*n usec delay */
372
373#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
374#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
375#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
376#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
377 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
378
379#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
380#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
381#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
382#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
383 /* this channel and from writing to pitch, filter and */
384 /* volume targets. */
385#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
386 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
387
388#define LFOVAL1 0x13 /* Modulation LFO value */
389#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
390 /* 0x8000-n == 666*n usec delay */
391
392#define ENVVAL 0x14 /* Modulation envelope register */
393#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
394 /* 0x8000-n == 666*n usec delay */
395
396#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
397#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
398#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
399#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
400 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
401
402#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
403#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
404#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
405#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
406 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
407
408#define LFOVAL2 0x17 /* Vibrato LFO register */
409#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
410 /* 0x8000-n == 666*n usec delay */
411
412#define IP 0x18 /* Initial pitch register */
413#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
414 /* 4 bits of octave, 12 bits of fractional octave */
415#define IP_UNITY 0x0000e000 /* Unity pitch shift */
416
417#define IFATN 0x19 /* Initial filter cutoff and attenuation register */
418#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
419 /* 6 most significant bits are semitones */
420 /* 2 least significant bits are fractions */
421#define IFATN_FILTERCUTOFF 0x08080019
422#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
423#define IFATN_ATTENUATION 0x08000019
424
425
426#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
427#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
428 /* Signed 2's complement, +/- one octave peak extremes */
429#define PEFE_PITCHAMOUNT 0x0808001a
430#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
431 /* Signed 2's complement, +/- six octaves peak extremes */
432#define PEFE_FILTERAMOUNT 0x0800001a
433#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
434#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
435 /* Signed 2's complement, +/- one octave extremes */
436#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
437 /* Signed 2's complement, +/- three octave extremes */
438
439
440#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
441#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
442 /* Signed 2's complement, with +/- 12dB extremes */
443
444#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
445#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
446 /* Signed 2's complement, +/- one octave extremes */
447#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
448 /* 0.039Hz steps, maximum of 9.85 Hz. */
449
450#define TEMPENV 0x1e /* Tempory envelope register */
451#define TEMPENV_MASK 0x0000ffff /* 16-bit value */
452 /* NOTE: All channels contain internal variables; do */
453 /* not write to these locations. */
454
455#define CD0 0x20 /* Cache data 0 register */
456#define CD1 0x21 /* Cache data 1 register */
457#define CD2 0x22 /* Cache data 2 register */
458#define CD3 0x23 /* Cache data 3 register */
459#define CD4 0x24 /* Cache data 4 register */
460#define CD5 0x25 /* Cache data 5 register */
461#define CD6 0x26 /* Cache data 6 register */
462#define CD7 0x27 /* Cache data 7 register */
463#define CD8 0x28 /* Cache data 8 register */
464#define CD9 0x29 /* Cache data 9 register */
465#define CDA 0x2a /* Cache data A register */
466#define CDB 0x2b /* Cache data B register */
467#define CDC 0x2c /* Cache data C register */
468#define CDD 0x2d /* Cache data D register */
469#define CDE 0x2e /* Cache data E register */
470#define CDF 0x2f /* Cache data F register */
471
472#define PTB 0x40 /* Page table base register */
473#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
474
475#define TCB 0x41 /* Tank cache base register */
476#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
477
478#define ADCCR 0x42 /* ADC sample rate/stereo control register */
479#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
480#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
481 /* NOTE: To guarantee phase coherency, both channels */
482 /* must be disabled prior to enabling both channels. */
483#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
484#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
485#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
486#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
487#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
488#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
489#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
490#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
491#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
492
493#define FXWC 0x43 /* FX output write channels register */
494 /* When set, each bit enables the writing of the */
495 /* corresponding FX output channel into host memory */
496
497#define TCBS 0x44 /* Tank cache buffer size register */
498#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
499#define TCBS_BUFFSIZE_16K 0x00000000
500#define TCBS_BUFFSIZE_32K 0x00000001
501#define TCBS_BUFFSIZE_64K 0x00000002
502#define TCBS_BUFFSIZE_128K 0x00000003
503#define TCBS_BUFFSIZE_256K 0x00000004
504#define TCBS_BUFFSIZE_512K 0x00000005
505#define TCBS_BUFFSIZE_1024K 0x00000006
506#define TCBS_BUFFSIZE_2048K 0x00000007
507
508#define MICBA 0x45 /* AC97 microphone buffer address register */
509#define MICBA_MASK 0xfffff000 /* 20 bit base address */
510
511#define ADCBA 0x46 /* ADC buffer address register */
512#define ADCBA_MASK 0xfffff000 /* 20 bit base address */
513
514#define FXBA 0x47 /* FX Buffer Address */
515#define FXBA_MASK 0xfffff000 /* 20 bit base address */
516
517#define MICBS 0x49 /* Microphone buffer size register */
518
519#define ADCBS 0x4a /* ADC buffer size register */
520
521#define FXBS 0x4b /* FX buffer size register */
522
523/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
524#define ADCBS_BUFSIZE_NONE 0x00000000
525#define ADCBS_BUFSIZE_384 0x00000001
526#define ADCBS_BUFSIZE_448 0x00000002
527#define ADCBS_BUFSIZE_512 0x00000003
528#define ADCBS_BUFSIZE_640 0x00000004
529#define ADCBS_BUFSIZE_768 0x00000005
530#define ADCBS_BUFSIZE_896 0x00000006
531#define ADCBS_BUFSIZE_1024 0x00000007
532#define ADCBS_BUFSIZE_1280 0x00000008
533#define ADCBS_BUFSIZE_1536 0x00000009
534#define ADCBS_BUFSIZE_1792 0x0000000a
535#define ADCBS_BUFSIZE_2048 0x0000000b
536#define ADCBS_BUFSIZE_2560 0x0000000c
537#define ADCBS_BUFSIZE_3072 0x0000000d
538#define ADCBS_BUFSIZE_3584 0x0000000e
539#define ADCBS_BUFSIZE_4096 0x0000000f
540#define ADCBS_BUFSIZE_5120 0x00000010
541#define ADCBS_BUFSIZE_6144 0x00000011
542#define ADCBS_BUFSIZE_7168 0x00000012
543#define ADCBS_BUFSIZE_8192 0x00000013
544#define ADCBS_BUFSIZE_10240 0x00000014
545#define ADCBS_BUFSIZE_12288 0x00000015
546#define ADCBS_BUFSIZE_14366 0x00000016
547#define ADCBS_BUFSIZE_16384 0x00000017
548#define ADCBS_BUFSIZE_20480 0x00000018
549#define ADCBS_BUFSIZE_24576 0x00000019
550#define ADCBS_BUFSIZE_28672 0x0000001a
551#define ADCBS_BUFSIZE_32768 0x0000001b
552#define ADCBS_BUFSIZE_40960 0x0000001c
553#define ADCBS_BUFSIZE_49152 0x0000001d
554#define ADCBS_BUFSIZE_57344 0x0000001e
555#define ADCBS_BUFSIZE_65536 0x0000001f
556
557
558#define CDCS 0x50 /* CD-ROM digital channel status register */
559
560#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
561
562#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
563
564#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
565
566#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
567
568#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
569
570#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
571
572#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
573#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
574#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
575#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
576#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
577#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
578#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
579#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
580#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
581#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
582#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
583#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
584#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
585#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
586#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
587#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
588#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
589#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
590#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
591#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
592#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
593#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
594#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
595
596/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
597#define CLIEL 0x58 /* Channel loop interrupt enable low register */
598
599#define CLIEH 0x59 /* Channel loop interrupt enable high register */
600
601#define CLIPL 0x5a /* Channel loop interrupt pending low register */
602
603#define CLIPH 0x5b /* Channel loop interrupt pending high register */
604
605#define SOLEL 0x5c /* Stop on loop enable low register */
606
607#define SOLEH 0x5d /* Stop on loop enable high register */
608
609#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
610#define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */
611
612#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
613
614#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
615
616#define ZVSRCS 0x62 /* ZVideo sample rate converter status */
617 /* NOTE: This one has no SPDIFLOCKED field */
618 /* Assumes sample lock */
619
620/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
621#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
622#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
623#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
624
625#define MICIDX 0x63 /* Microphone recording buffer index register */
626#define MICIDX_MASK 0x0000ffff /* 16-bit value */
627#define MICIDX_IDX 0x10000063
628
629#define ADCIDX 0x64 /* ADC recording buffer index register */
630#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
631#define ADCIDX_IDX 0x10000064
632
633#define FXIDX 0x65 /* FX recording buffer index register */
634#define FXIDX_MASK 0x0000ffff /* 16-bit value */
635#define FXIDX_IDX 0x10000065
636
637/* Each FX general purpose register is 32 bits in length, all bits are used */
638#define FXGPREGBASE 0x100 /* FX general purpose registers base */
639
640/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
641/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
642/* locations are for external TRAM. */
643#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
644#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
645
646/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
647#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
648#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
649#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
650#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
651#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
652#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
653
654#define MICROCODEBASE 0x400 /* Microcode data base address */
655
656/* Each DSP microcode instruction is mapped into 2 doublewords */
657/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
658#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
659#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
660#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
661#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
662#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
663
664#endif /* _8010_H */
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