source: cmedia/trunk/Include/Linux/pci.h@ 354

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1/*
2 * $Id: pci.h,v 1.1 2000/04/23 14:55:32 ktk Exp $
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20/*
21 * Under PCI, each device has 256 bytes of configuration address space,
22 * of which the first 64 bytes are standardized as follows:
23 */
24#define PCI_VENDOR_ID 0x00 /* 16 bits */
25#define PCI_DEVICE_ID 0x02 /* 16 bits */
26#define PCI_COMMAND 0x04 /* 16 bits */
27#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
28#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
29#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
30#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
31#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
32#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
33#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
34#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
35#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
36#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
37
38#define PCI_STATUS 0x06 /* 16 bits */
39#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
40#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
41#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
42#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
43#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
44#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
45#define PCI_STATUS_DEVSEL_FAST 0x000
46#define PCI_STATUS_DEVSEL_MEDIUM 0x200
47#define PCI_STATUS_DEVSEL_SLOW 0x400
48#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
49#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
50#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
51#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
52#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
53
54#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
55 revision */
56#define PCI_REVISION_ID 0x08 /* Revision ID */
57#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
58#define PCI_CLASS_DEVICE 0x0a /* Device class */
59
60#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
61#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
62#define PCI_HEADER_TYPE 0x0e /* 8 bits */
63#define PCI_HEADER_TYPE_NORMAL 0
64#define PCI_HEADER_TYPE_BRIDGE 1
65#define PCI_HEADER_TYPE_CARDBUS 2
66
67#define PCI_BIST 0x0f /* 8 bits */
68#define PCI_BIST_CODE_MASK 0x0f /* Return result */
69#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
70#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
71
72/*
73 * Base addresses specify locations in memory or I/O space.
74 * Decoded size can be determined by writing a value of
75 * 0xffffffff to the register, and reading it back. Only
76 * 1 bits are decoded.
77 */
78#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
79#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
80#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
81#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
82#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
83#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
84#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
85#define PCI_BASE_ADDRESS_SPACE_IO 0x01
86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
92#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
93#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
94/* bit 1 is reserved if address_space = 1 */
95
96/* Header type 0 (normal devices) */
97#define PCI_CARDBUS_CIS 0x28
98#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
99#define PCI_SUBSYSTEM_ID 0x2e
100#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
101#define PCI_ROM_ADDRESS_ENABLE 0x01
102#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
103
104#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
105
106/* 0x35-0x3b are reserved */
107#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109#define PCI_MIN_GNT 0x3e /* 8 bits */
110#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112/* Header type 1 (PCI-to-PCI bridges) */
113#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
114#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
115#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
116#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
117#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
118#define PCI_IO_LIMIT 0x1d
119#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
120#define PCI_IO_RANGE_TYPE_16 0x00
121#define PCI_IO_RANGE_TYPE_32 0x01
122#define PCI_IO_RANGE_MASK ~0x0f
123#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
124#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
125#define PCI_MEMORY_LIMIT 0x22
126#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
127#define PCI_MEMORY_RANGE_MASK ~0x0f
128#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
129#define PCI_PREF_MEMORY_LIMIT 0x26
130#define PCI_PREF_RANGE_TYPE_MASK 0x0f
131#define PCI_PREF_RANGE_TYPE_32 0x00
132#define PCI_PREF_RANGE_TYPE_64 0x01
133#define PCI_PREF_RANGE_MASK ~0x0f
134#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
135#define PCI_PREF_LIMIT_UPPER32 0x2c
136#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
137#define PCI_IO_LIMIT_UPPER16 0x32
138/* 0x34 same as for htype 0 */
139/* 0x35-0x3b is reserved */
140#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
141/* 0x3c-0x3d are same as for htype 0 */
142#define PCI_BRIDGE_CONTROL 0x3e
143#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
144#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
145#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
146#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
147#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
148#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
149#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
150
151/* Header type 2 (CardBus bridges) */
152/* 0x14-0x15 reserved */
153#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
154#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
155#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
156#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
157#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
158#define PCI_CB_MEMORY_BASE_0 0x1c
159#define PCI_CB_MEMORY_LIMIT_0 0x20
160#define PCI_CB_MEMORY_BASE_1 0x24
161#define PCI_CB_MEMORY_LIMIT_1 0x28
162#define PCI_CB_IO_BASE_0 0x2c
163#define PCI_CB_IO_BASE_0_HI 0x2e
164#define PCI_CB_IO_LIMIT_0 0x30
165#define PCI_CB_IO_LIMIT_0_HI 0x32
166#define PCI_CB_IO_BASE_1 0x34
167#define PCI_CB_IO_BASE_1_HI 0x36
168#define PCI_CB_IO_LIMIT_1 0x38
169#define PCI_CB_IO_LIMIT_1_HI 0x3a
170#define PCI_CB_IO_RANGE_MASK ~0x03
171/* 0x3c-0x3d are same as for htype 0 */
172#define PCI_CB_BRIDGE_CONTROL 0x3e
173#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
174#define PCI_CB_BRIDGE_CTL_SERR 0x02
175#define PCI_CB_BRIDGE_CTL_ISA 0x04
176#define PCI_CB_BRIDGE_CTL_VGA 0x08
177#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
178#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
179#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
180#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
181#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
182#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
183#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
184#define PCI_CB_SUBSYSTEM_ID 0x42
185#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
186/* 0x48-0x7f reserved */
187
188/* Capability lists */
189
190#define PCI_CAP_LIST_ID 0 /* Capability ID */
191#define PCI_CAP_ID_PM 0x01 /* Power Management */
192#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
193#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
194#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
195#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
196#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
197#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
198#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
199#define PCI_CAP_SIZEOF 4
200
201/* Power Management Registers */
202
203#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
204#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
205#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
206#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
207#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
208#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
209#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
210#define PCI_PM_CTRL 4 /* PM control and status register */
211#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
212#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
213#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
214#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
215#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
216#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
217#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
218#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
219#define PCI_PM_DATA_REGISTER 7 /* (??) */
220#define PCI_PM_SIZEOF 8
221
222/* AGP registers */
223
224#define PCI_AGP_VERSION 2 /* BCD version number */
225#define PCI_AGP_RFU 3 /* Rest of capability flags */
226#define PCI_AGP_STATUS 4 /* Status register */
227#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
228#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
229#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
230#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
231#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
232#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
233#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
234#define PCI_AGP_COMMAND 8 /* Control register */
235#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
236#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
237#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
238#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
239#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
240#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
241#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
242#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
243#define PCI_AGP_SIZEOF 12
244
245/* Slot Identification */
246
247#define PCI_SID_ESR 2 /* Expansion Slot Register */
248#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
249#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
250#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
251
252/* Message Signalled Interrupts registers */
253
254#define PCI_MSI_FLAGS 2 /* Various flags */
255#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
256#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
257#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
258#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
259#define PCI_MSI_RFU 3 /* Rest of capability flags */
260#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
261#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
262#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
263#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
264
265/* Include the ID list */
266
267#include <linux/pci_ids.h>
268
269/*
270 * The PCI interface treats multi-function devices as independent
271 * devices. The slot/function address of each device is encoded
272 * in a single byte as follows:
273 *
274 * 7:3 = slot
275 * 2:0 = function
276 */
277#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
278#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
279#define PCI_FUNC(devfn) ((devfn) & 0x07)
280
281#ifdef __KERNEL__
282
283#include <linux/types.h>
284#include <linux/ioport.h>
285
286#include <asm/pci.h>
287
288#define DEVICE_COUNT_COMPATIBLE 4
289#define DEVICE_COUNT_IRQ 2
290#define DEVICE_COUNT_DMA 2
291#define DEVICE_COUNT_RESOURCE 12
292
293/*
294 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
295 */
296struct pci_dev {
297 int active; /* device is active */
298 int ro; /* Read/Only */
299
300 struct pci_bus *bus; /* bus this device is on */
301 struct pci_dev *sibling; /* next device on this bus */
302 struct pci_dev *next; /* chain of all devices */
303
304 void *sysdata; /* hook for sys-specific extension */
305 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
306
307 unsigned int devfn; /* encoded device & function index */
308 unsigned short vendor;
309 unsigned short device;
310 unsigned short subsystem_vendor;
311 unsigned short subsystem_device;
312 unsigned int _class; /* 3 bytes: (base,sub,prog-if) */
313 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
314 u8 rom_base_reg; /* Which config register controls the ROM */
315
316 unsigned short regs;
317
318 /* device is compatible with these IDs */
319 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
320 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
321
322 /*
323 * Instead of touching interrupt line and base address registers
324 * directly, use the values stored here. They might be different!
325 */
326 unsigned int irq;
327 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
328 struct resource dma_resource[DEVICE_COUNT_DMA];
329 struct resource irq_resource[DEVICE_COUNT_IRQ];
330
331 char name[48]; /* Device name */
332 char slot_name[8]; /* Slot name */
333
334 void *driver_data;
335 unsigned long dma_mask;
336
337 int (*prepare)(struct pci_dev *dev);
338 int (*activate)(struct pci_dev *dev);
339 int (*deactivate)(struct pci_dev *dev);
340};
341
342/*
343 * For PCI devices, the region numbers are assigned this way:
344 *
345 * 0-5 standard PCI regions
346 * 6 expansion ROM
347 * 7-10 bridges: address space assigned to buses behind the bridge
348 */
349
350#define PCI_ROM_RESOURCE 6
351#define PCI_BRIDGE_RESOURCES 7
352#define PCI_NUM_RESOURCES 11
353
354#define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
355
356struct pci_bus {
357 struct pci_bus *parent; /* parent bus this bridge is on */
358 struct pci_bus *children; /* chain of P2P bridges on this bus */
359 struct pci_bus *next; /* chain of all PCI buses */
360 struct pci_ops *ops; /* configuration access functions */
361
362 struct pci_dev *self; /* bridge device as seen by parent */
363 struct pci_dev *devices; /* devices behind this bridge */
364 struct resource *resource[4]; /* address space routed to this bus */
365
366 void *sysdata; /* hook for sys-specific extension */
367 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
368
369 unsigned char number; /* bus number */
370 unsigned char primary; /* number of primary bridge */
371 unsigned char secondary; /* number of secondary bridge */
372 unsigned char subordinate; /* max number of subordinate buses */
373
374 char name[48];
375 unsigned short vendor;
376 unsigned short device;
377 unsigned int serial; /* serial number */
378 unsigned char pnpver; /* Plug & Play version */
379 unsigned char productver; /* product version */
380 unsigned char checksum; /* if zero - checksum passed */
381 unsigned char pad1;
382};
383
384//extern struct pci_bus *pci_root; /* root bus */
385//extern struct pci_dev *pci_devices; /* list of all devices */
386
387/*
388 * Error values that may be returned by PCI functions.
389 */
390#define PCIBIOS_SUCCESSFUL 0x00
391#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
392#define PCIBIOS_BAD_VENDOR_ID 0x83
393#define PCIBIOS_DEVICE_NOT_FOUND 0x86
394#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
395#define PCIBIOS_SET_FAILED 0x88
396#define PCIBIOS_BUFFER_TOO_SMALL 0x89
397
398/* Low-level architecture-dependent routines */
399
400struct pci_ops {
401 int (*read_byte)(struct pci_dev *, int where, u8 *val);
402 int (*read_word)(struct pci_dev *, int where, u16 *val);
403 int (*read_dword)(struct pci_dev *, int where, u32 *val);
404 int (*write_byte)(struct pci_dev *, int where, u8 val);
405 int (*write_word)(struct pci_dev *, int where, u16 val);
406 int (*write_dword)(struct pci_dev *, int where, u32 val);
407};
408
409void pcibios_init(void);
410void pcibios_fixup_bus(struct pci_bus *);
411int pcibios_enable_device(struct pci_dev *);
412char *pcibios_setup (char *str);
413
414void pcibios_update_resource(struct pci_dev *, struct resource *,
415 struct resource *, int);
416void pcibios_update_irq(struct pci_dev *, int irq);
417
418/* Backward compatibility, don't use in new code! */
419
420int pcibios_present(void);
421#define pci_present pcibios_present
422int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
423 unsigned char where, unsigned char *val);
424int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
425 unsigned char where, unsigned short *val);
426int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
427 unsigned char where, unsigned int *val);
428int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
429 unsigned char where, unsigned char val);
430int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
431 unsigned char where, unsigned short val);
432int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
433 unsigned char where, unsigned int val);
434int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
435int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
436 unsigned short index, unsigned char *bus,
437 unsigned char *dev_fn);
438
439/* Generic PCI interface functions */
440
441void pci_init(void);
442struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
443int pci_proc_attach_device(struct pci_dev *dev);
444int pci_proc_detach_device(struct pci_dev *dev);
445void pci_name_device(struct pci_dev *dev);
446void pci_read_bridge_bases(struct pci_bus *child);
447struct resource *pci_find_parent_resource(struct pci_dev *dev, struct resource *res);
448
449struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
450struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
451 unsigned int ss_vendor, unsigned int ss_device,
452 struct pci_dev *from);
453struct pci_dev *pci_find_class (unsigned int _class, struct pci_dev *from);
454struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
455int pci_find_capability (struct pci_dev *dev, int cap);
456int pci_dma_supported(struct pci_dev *dev, unsigned long mask);
457
458#define PCI_ANY_ID (~0)
459
460int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
461int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
462int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
463int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
464int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
465int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
466int pci_enable_device(struct pci_dev *dev);
467void pci_set_master(struct pci_dev *dev);
468int pci_set_power_state(struct pci_dev *dev, int state);
469
470/* Helper functions for low-level code (drivers/pci/setup.c) */
471
472int pci_claim_resource(struct pci_dev *, int);
473void pci_assign_unassigned_resources(u32 min_io, u32 min_mem);
474void pci_set_bus_ranges(void);
475void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
476 int (*)(struct pci_dev *, u8, u8));
477
478/*
479 * simple PCI probing for drivers (drivers/pci/helper.c)
480 */
481
482struct pci_simple_probe_entry;
483typedef int (*pci_simple_probe_callback) (struct pci_dev *dev, int match_num,
484 const struct pci_simple_probe_entry *ent,
485 void *drvr_data);
486
487struct pci_simple_probe_entry {
488 unsigned short vendor; /* vendor id, PCI_ANY_ID, or 0 for last entry */
489 unsigned short device; /* device id, PCI_ANY_ID, or 0 for last entry */
490 unsigned short subsys_vendor; /* subsystem vendor id, 0 for don't care */
491 unsigned short subsys_device; /* subsystem device id, 0 for don't care */
492 void *dev_data; /* driver-private, entry-specific data */
493};
494
495int pci_simple_probe (const struct pci_simple_probe_entry *list,
496 size_t match_limit, pci_simple_probe_callback cb,
497 void *drvr_data);
498
499
500
501/*
502 * If the system does not have PCI, clearly these return errors. Define
503 * these as simple inline functions to avoid hair in drivers.
504 */
505
506/*
507 * The world is not perfect and supplies us with broken PCI devices.
508 * For at least a part of these bugs we need a work-around, so both
509 * generic (drivers/pci/quirks.c) and per-architecture code can define
510 * fixup hooks to be called for particular buggy devices.
511 */
512
513struct pci_fixup {
514 int pass;
515 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
516 void (*hook)(struct pci_dev *dev);
517};
518
519extern struct pci_fixup pcibios_fixups[];
520
521#define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
522#define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
523
524void pci_fixup_device(int pass, struct pci_dev *dev);
525
526extern int pci_pci_problems;
527#define PCIPCI_FAIL 1
528#define PCIPCI_TRITON 2
529#define PCIPCI_NATOMA 4
530
531
532struct pci_device_id {
533 unsigned int vendor, device;
534 unsigned int subvendor, subdevice;
535 unsigned int class, class_mask;
536 unsigned long driver_data;
537};
538
539struct pci_driver {
540 struct list_head node;
541 char *name;
542 const struct pci_device_id *id_table;
543 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
544 void (*remove)(struct pci_dev *dev);
545 void (*suspend)(struct pci_dev *dev);
546 void (*resume)(struct pci_dev *dev);
547};
548
549int pci_register_driver(struct pci_driver *driver);
550#define pci_module_init pci_register_driver
551
552int pci_unregister_driver(struct pci_driver *driver);
553
554#endif /* __KERNEL__ */
555#endif /* LINUX_PCI_H */
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