| 1 | /* SCCSID = %W% %E% */
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| 2 | /****************************************************************************
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| 3 | * *
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| 4 | * Copyright (c) IBM Corporation 1994 - 1997. *
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| 5 | * (c) Copyright Media Vision Corporation 1993. *
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| 6 | * *
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| 7 | * The following IBM OS/2 source code is provided to you solely for the *
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| 8 | * the purpose of assisting you in your development of OS/2 device drivers. *
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| 9 | * You may use this code in accordance with the IBM License Agreement *
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| 10 | * provided in the IBM Device Driver Source Kit for OS/2. *
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| 11 | * *
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| 12 | ****************************************************************************/
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| 13 | /**@internal %W%
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| 14 | * Provides lowest level IO routines for FMSYNTH operation.
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| 15 | * @version %I%
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| 16 | * @context
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| 17 | * Unless otherwise noted, all interfaces are Ring-0, 16-bit, kernel stack.
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| 18 | * @notes
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| 19 | * @history
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| 20 | */
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| 21 |
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| 22 | extern "C" {
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| 23 | #define INCL_DOSINFOSEG
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| 24 | #define INCL_BASE
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| 25 | #include <os2.h>
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| 26 | #include <conio.h> // outp()
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| 27 | #include "iodelay.h" // iodelay()
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| 28 | #include <devhelp.h>
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| 29 | }
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| 30 | #include "fmsynth.hpp"
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| 31 |
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| 32 | #define WAIT_OPL3_ADDR_LATCH 7 // 3.5 æs
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| 33 | #define WAIT_OPL3_DATA_LATCH 7 // 3.5 æs
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| 34 |
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| 35 |
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| 36 | #if 0
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| 37 | /* -------------------------- SndOutput1 -
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| 38 | ** Set the register at internal chip address 'addr' to the value 'data'.
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| 39 | ** Also perform 'data register-to-data register' write delay.
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| 40 | */
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| 41 | void FMSYNTH::SndOutput1 (USHORT addr, USHORT data)
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| 42 | {
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| 43 | outp( _port, addr );
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| 44 | iodelay( WAIT_OPL3_ADDR_LATCH );
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| 45 | outp( _port+1, data );
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| 46 | iodelay( WAIT_OPL3_DATA_LATCH );
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| 47 | }
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| 48 |
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| 49 | /* ------------------------- SndOpl3_2_1 -
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| 50 | ** Set the register at internal chip address 'addr' to the value 'data'.
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| 51 | ** Also perform 'data register-to-data register' write delay.
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| 52 | ** This function set the other half of the OPL-3 chip
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| 53 | */
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| 54 | void FMSYNTH::SndOpl3_2_1 ( USHORT addr, USHORT data)
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| 55 | {
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| 56 | outp( _port+2, addr );
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| 57 | iodelay( WAIT_OPL3_ADDR_LATCH );
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| 58 | outp( _port+3, data );
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| 59 | iodelay( WAIT_OPL3_DATA_LATCH );
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| 60 | }
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| 61 | #endif
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| 62 |
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| 63 |
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| 64 | /*
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| 65 | ** Rudi: Write data to chip with neccessary delays.
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| 66 | ** Port address is calculated by the caller.
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| 67 | */
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| 68 | void FMSYNTH::OplWrite(USHORT usPort, UCHAR uchOffset, UCHAR uchData)
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| 69 | {
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| 70 | #if 0
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| 71 | ULONG ulTemp = usPort | ((ULONG)uchOffset << 16) | ((ULONG)uchData << 24);
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| 72 | DevHelp_RAS(240, 240, sizeof(ulTemp), (PBYTE)&ulTemp);
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| 73 | #endif
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| 74 |
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| 75 | outp( usPort++, uchOffset );
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| 76 | iodelay( WAIT_OPL3_ADDR_LATCH );
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| 77 | outp( usPort, uchData );
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| 78 | iodelay( WAIT_OPL3_DATA_LATCH );
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| 79 | }
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| 80 |
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| 81 |
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