source: GPL/trunk/include/linux/pci.h@ 604

Last change on this file since 604 was 604, checked in by David Azarewicz, 8 years ago

Incorporated changes from Andy.
Added limited MSI support.
File size: 28.7 KB
Line 
1/*
2 * PCI defines and function prototypes
3 * Copyright 1994, Drew Eckhardt
4 * Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
5 *
6 * For more information, please consult the following manuals (look at
7 * http://www.pcisig.com/ for how to get them):
8 *
9 * PCI BIOS Specification
10 * PCI Local Bus Specification
11 * PCI to PCI Bridge Specification
12 * PCI System Design Guide
13 */
14
15#ifndef LINUX_PCI_H
16#define LINUX_PCI_H
17
18#include <linux/types.h>
19#include <linux/list.h>
20#pragma pack(1) //!!! by vladest
21/*
22 * Under PCI, each device has 256 bytes of configuration address space,
23 * of which the first 64 bytes are standardized as follows:
24 */
25#define PCI_VENDOR_ID 0x00 /* 16 bits */
26#define PCI_DEVICE_ID 0x02 /* 16 bits */
27#define PCI_COMMAND 0x04 /* 16 bits */
28#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
29#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
30#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
31#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
32#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
33#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
34#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
35#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
36#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
37#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
38
39#define PCI_STATUS 0x06 /* 16 bits */
40#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
41#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
42#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
43#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
44#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
45#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
46#define PCI_STATUS_DEVSEL_FAST 0x000
47#define PCI_STATUS_DEVSEL_MEDIUM 0x200
48#define PCI_STATUS_DEVSEL_SLOW 0x400
49#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
50#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
51#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
52#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
53#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
54
55#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
56 revision */
57#define PCI_REVISION_ID 0x08 /* Revision ID */
58#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
59#define PCI_CLASS_DEVICE 0x0a /* Device class */
60
61#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
62#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
63#define PCI_HEADER_TYPE 0x0e /* 8 bits */
64#define PCI_HEADER_TYPE_NORMAL 0
65#define PCI_HEADER_TYPE_BRIDGE 1
66#define PCI_HEADER_TYPE_CARDBUS 2
67
68#define PCI_BIST 0x0f /* 8 bits */
69#define PCI_BIST_CODE_MASK 0x0f /* Return result */
70#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
71#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
72
73/*
74 * Base addresses specify locations in memory or I/O space.
75 * Decoded size can be determined by writing a value of
76 * 0xffffffff to the register, and reading it back. Only
77 * 1 bits are decoded.
78 */
79#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
80#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
81#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
82#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
83#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
84#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
85#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
86#define PCI_BASE_ADDRESS_SPACE_IO 0x01
87#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
88#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
89#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
90#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
91#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
92#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
93#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
94#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
95/* bit 1 is reserved if address_space = 1 */
96
97/* Header type 0 (normal devices) */
98#define PCI_CARDBUS_CIS 0x28
99#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
100#define PCI_SUBSYSTEM_ID 0x2e
101#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
102#define PCI_ROM_ADDRESS_ENABLE 0x01
103#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
104
105#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
106
107/* 0x35-0x3b are reserved */
108#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
109#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
110#define PCI_MIN_GNT 0x3e /* 8 bits */
111#define PCI_MAX_LAT 0x3f /* 8 bits */
112
113/* Header type 1 (PCI-to-PCI bridges) */
114#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
115#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
116#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
117#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
118#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
119#define PCI_IO_LIMIT 0x1d
120#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
121#define PCI_IO_RANGE_TYPE_16 0x00
122#define PCI_IO_RANGE_TYPE_32 0x01
123#define PCI_IO_RANGE_MASK ~0x0f
124#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
125#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
126#define PCI_MEMORY_LIMIT 0x22
127#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
128#define PCI_MEMORY_RANGE_MASK ~0x0f
129#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
130#define PCI_PREF_MEMORY_LIMIT 0x26
131#define PCI_PREF_RANGE_TYPE_MASK 0x0f
132#define PCI_PREF_RANGE_TYPE_32 0x00
133#define PCI_PREF_RANGE_TYPE_64 0x01
134#define PCI_PREF_RANGE_MASK ~0x0f
135#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
136#define PCI_PREF_LIMIT_UPPER32 0x2c
137#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
138#define PCI_IO_LIMIT_UPPER16 0x32
139/* 0x34 same as for htype 0 */
140/* 0x35-0x3b is reserved */
141#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
142/* 0x3c-0x3d are same as for htype 0 */
143#define PCI_BRIDGE_CONTROL 0x3e
144#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
145#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
146#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
147#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
148#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
149#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
150#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
151
152/* Header type 2 (CardBus bridges) */
153/* 0x14-0x15 reserved */
154#define PCI_CB_CAPABILITY_LIST 0x14
155#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
156#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
157#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
158#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
159#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
160#define PCI_CB_MEMORY_BASE_0 0x1c
161#define PCI_CB_MEMORY_LIMIT_0 0x20
162#define PCI_CB_MEMORY_BASE_1 0x24
163#define PCI_CB_MEMORY_LIMIT_1 0x28
164#define PCI_CB_IO_BASE_0 0x2c
165#define PCI_CB_IO_BASE_0_HI 0x2e
166#define PCI_CB_IO_LIMIT_0 0x30
167#define PCI_CB_IO_LIMIT_0_HI 0x32
168#define PCI_CB_IO_BASE_1 0x34
169#define PCI_CB_IO_BASE_1_HI 0x36
170#define PCI_CB_IO_LIMIT_1 0x38
171#define PCI_CB_IO_LIMIT_1_HI 0x3a
172#define PCI_CB_IO_RANGE_MASK ~0x03
173/* 0x3c-0x3d are same as for htype 0 */
174#define PCI_CB_BRIDGE_CONTROL 0x3e
175#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
176#define PCI_CB_BRIDGE_CTL_SERR 0x02
177#define PCI_CB_BRIDGE_CTL_ISA 0x04
178#define PCI_CB_BRIDGE_CTL_VGA 0x08
179#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
180#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
181#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
182#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
183#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
184#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
185#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
186#define PCI_CB_SUBSYSTEM_ID 0x42
187#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
188/* 0x48-0x7f reserved */
189
190/* Capability lists */
191
192#define PCI_CAP_LIST_ID 0 /* Capability ID */
193#define PCI_CAP_ID_PM 0x01 /* Power Management */
194#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
195#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
196#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
197#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
198#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
199#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
200#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
201#define PCI_CAP_SIZEOF 4
202
203/* Power Management Registers */
204#define PCI_PM_PMC 2 /* PM Capabilities Register */
205#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
206#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
207#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
208#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
209#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
210#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
211#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
212#define PCI_PM_CTRL 4 /* PM control and status register */
213#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
214#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
215#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
216#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
217#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
218#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
219#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
220#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
221#define PCI_PM_DATA_REGISTER 7 /* (??) */
222#define PCI_PM_SIZEOF 8
223
224/* AGP registers */
225
226#define PCI_AGP_VERSION 2 /* BCD version number */
227#define PCI_AGP_RFU 3 /* Rest of capability flags */
228#define PCI_AGP_STATUS 4 /* Status register */
229#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
230#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
231#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
232#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
233#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
234#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
235#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
236#define PCI_AGP_COMMAND 8 /* Control register */
237#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
238#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
239#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
240#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
241#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
242#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
243#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
244#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
245#define PCI_AGP_SIZEOF 12
246
247/* Slot Identification */
248
249#define PCI_SID_ESR 2 /* Expansion Slot Register */
250#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
251#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
252#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
253
254/* Message Signalled Interrupts registers */
255
256#define PCI_MSI_FLAGS 2 /* Various flags */
257#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
258#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
259#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
260#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
261#define PCI_MSI_RFU 3 /* Rest of capability flags */
262#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
263#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
264#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
265#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
266
267/* Include the ID list */
268
269#include <linux/pci_ids.h>
270
271/*
272 * The PCI interface treats multi-function devices as independent
273 * devices. The slot/function address of each device is encoded
274 * in a single byte as follows:
275 *
276 * 7:3 = slot
277 * 2:0 = function
278 */
279#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
280#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
281#define PCI_FUNC(devfn) ((devfn) & 0x07)
282
283#ifdef __KERNEL__
284
285#include <linux/types.h>
286#include <linux/ioport.h>
287
288#include <asm/pci.h>
289#define BUS_ID_SIZE 20
290#define DEVICE_COUNT_COMPATIBLE 4
291#define DEVICE_COUNT_IRQ 2
292#define DEVICE_COUNT_DMA 2
293#define DEVICE_COUNT_RESOURCE 12
294
295typedef struct pci_dev;
296
297#define PCI_D0 0
298#define PCI_D1 1
299#define PCI_D2 2
300#define PCI_D3hot 3
301#define PCI_D3cold 4
302#define pci_choose_state(pci,state) ((state) ? PCI_D3hot : PCI_D0)
303
304typedef struct device {
305 struct pci_dev *pci; /* for PCI and PCI-SG types */
306 struct device * parent;
307 struct bus_type * bus; /* type of bus device is on */
308 char bus_id[BUS_ID_SIZE]; /* position on parent bus */
309 void (*release)(struct device * dev);
310 unsigned int flags; /* GFP_XXX for continous and ISA types */
311#ifdef CONFIG_SBUS
312 struct sbus_dev *sbus; /* for SBUS type */
313#endif
314 void *private_data;
315 void *platform_data;
316
317 struct device_driver *driver;
318 struct pm_dev *pm_dev;
319 char bus_id[20];
320} device;
321
322/*
323 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
324 */
325struct pci_dev {
326 int active; /* device is active */
327 int ro; /* Read/Only */
328
329 struct pci_bus *bus; /* bus this device is on */
330 struct pci_dev *sibling; /* next device on this bus */
331 struct pci_dev *next; /* chain of all devices */
332
333 void *sysdata; /* hook for sys-specific extension */
334 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
335
336 struct device dev;
337
338 unsigned int devfn; /* encoded device & function index */
339 unsigned short vendor;
340 unsigned short device;
341 unsigned short subsystem_vendor;
342 unsigned short subsystem_device;
343 unsigned int _class; /* 3 bytes: (base,sub,prog-if) */
344 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
345 u8 rom_base_reg; /* Which config register controls the ROM */
346
347 unsigned short regs;
348
349 u32 current_state; /* Current operating state. In ACPI-speak,
350 this is D0-D3, D0 being fully functional,
351 and D3 being off. */
352
353 /* device is compatible with these IDs */
354 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
355 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
356
357 /*
358 * Instead of touching interrupt line and base address registers
359 * directly, use the values stored here. They might be different!
360 */
361 unsigned int irq;
362 unsigned char irq_pin;
363 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
364 struct resource dma_resource[DEVICE_COUNT_DMA];
365 struct resource irq_resource[DEVICE_COUNT_IRQ];
366
367 char name[48]; /* Device name */
368 char slot_name[8]; /* Slot name */
369
370 void *driver_data;
371 unsigned long dma_mask;
372
373 int (*prepare)(struct pci_dev *dev);
374 int (*activate)(struct pci_dev *dev);
375 int (*deactivate)(struct pci_dev *dev);
376#ifdef TARGET_OS2
377//DAZ unsigned int picirq;
378//DAZ unsigned int apicirq;
379 unsigned long hAdapter;
380 unsigned long hDevice;
381 void *pcidriver;
382#endif
383};
384
385/*
386 * For PCI devices, the region numbers are assigned this way:
387 *
388 * 0-5 standard PCI regions
389 * 6 expansion ROM
390 * 7-10 bridges: address space assigned to buses behind the bridge
391 */
392
393#define PCI_ROM_RESOURCE 6
394#define PCI_BRIDGE_RESOURCES 7
395#define PCI_NUM_RESOURCES 11
396
397#define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
398
399struct pci_bus {
400 struct pci_bus *parent; /* parent bus this bridge is on */
401 struct pci_bus *children; /* chain of P2P bridges on this bus */
402 struct pci_bus *next; /* chain of all PCI buses */
403 struct pci_ops *ops; /* configuration access functions */
404
405 struct pci_dev *self; /* bridge device as seen by parent */
406 struct pci_dev *devices; /* devices behind this bridge */
407 struct resource *resource[4]; /* address space routed to this bus */
408
409 void *sysdata; /* hook for sys-specific extension */
410 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
411
412 unsigned char number; /* bus number */
413 unsigned char primary; /* number of primary bridge */
414 unsigned char secondary; /* number of secondary bridge */
415 unsigned char subordinate; /* max number of subordinate buses */
416
417 char name[48];
418 unsigned short vendor;
419 unsigned short device;
420 unsigned int serial; /* serial number */
421 unsigned char pnpver; /* Plug & Play version */
422 unsigned char productver; /* product version */
423 unsigned char checksum; /* if zero - checksum passed */
424 unsigned char pad1;
425};
426
427//extern struct pci_bus *pci_root; /* root bus */
428//extern struct pci_dev *pci_devices; /* list of all devices */
429
430/*
431 * Error values that may be returned by PCI functions.
432 */
433#define PCIBIOS_SUCCESSFUL 0x00
434#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
435#define PCIBIOS_BAD_VENDOR_ID 0x83
436#define PCIBIOS_DEVICE_NOT_FOUND 0x86
437#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
438#define PCIBIOS_SET_FAILED 0x88
439#define PCIBIOS_BUFFER_TOO_SMALL 0x89
440
441/* Low-level architecture-dependent routines */
442
443struct pci_ops {
444 int (*read_byte)(struct pci_dev *, int where, u8 *val);
445 int (*read_word)(struct pci_dev *, int where, u16 *val);
446 int (*read_dword)(struct pci_dev *, int where, u32 *val);
447 int (*write_byte)(struct pci_dev *, int where, u8 val);
448 int (*write_word)(struct pci_dev *, int where, u16 val);
449 int (*write_dword)(struct pci_dev *, int where, u32 val);
450};
451
452void pcibios_init(void);
453void pcibios_fixup_bus(struct pci_bus *);
454int pcibios_enable_device(struct pci_dev *);
455char *pcibios_setup (char *str);
456
457void pcibios_update_resource(struct pci_dev *, struct resource *,
458 struct resource *, int);
459void pcibios_update_irq(struct pci_dev *, int irq);
460
461/* Backward compatibility, don't use in new code! */
462
463int pcibios_present(void);
464#define pci_present pcibios_present
465int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
466 unsigned char where, unsigned char *val);
467int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
468 unsigned char where, unsigned short *val);
469int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
470 unsigned char where, unsigned int *val);
471int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
472 unsigned char where, unsigned char val);
473int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
474 unsigned char where, unsigned short val);
475int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
476 unsigned char where, unsigned int val);
477int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
478int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
479 unsigned short index, unsigned char *bus,
480 unsigned char *dev_fn);
481
482/* Generic PCI interface functions */
483
484void pci_init(void);
485struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
486int pci_proc_attach_device(struct pci_dev *dev);
487int pci_proc_detach_device(struct pci_dev *dev);
488void pci_name_device(struct pci_dev *dev);
489void pci_read_bridge_bases(struct pci_bus *child);
490struct resource *pci_find_parent_resource(struct pci_dev *dev, struct resource *res);
491
492struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
493struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
494 unsigned int ss_vendor, unsigned int ss_device,
495 struct pci_dev *from);
496struct pci_dev *pci_find_class (unsigned int _class, struct pci_dev *from);
497struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
498int pci_find_capability (struct pci_dev *dev, int cap);
499int pci_dma_supported(struct pci_dev *dev, unsigned long mask);
500
501#define PCI_ANY_ID (~0)
502
503int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
504int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
505int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
506int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
507int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
508int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
509int pci_enable_device(struct pci_dev *dev);
510void pci_set_master(struct pci_dev *dev);
511int pci_set_power_state(struct pci_dev *dev, int state);
512
513/* Helper functions for low-level code (drivers/pci/setup.c) */
514
515int pci_claim_resource(struct pci_dev *, int);
516void pci_assign_unassigned_resources(u32 min_io, u32 min_mem);
517void pci_set_bus_ranges(void);
518void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
519 int (*)(struct pci_dev *, u8, u8));
520
521/*
522 * simple PCI probing for drivers (drivers/pci/helper.c)
523 */
524
525struct pci_simple_probe_entry;
526typedef int (*pci_simple_probe_callback) (struct pci_dev *dev, int match_num,
527 const struct pci_simple_probe_entry *ent,
528 void *drvr_data);
529
530struct pci_simple_probe_entry {
531 unsigned short vendor; /* vendor id, PCI_ANY_ID, or 0 for last entry */
532 unsigned short device; /* device id, PCI_ANY_ID, or 0 for last entry */
533 unsigned short subsys_vendor; /* subsystem vendor id, 0 for don't care */
534 unsigned short subsys_device; /* subsystem device id, 0 for don't care */
535 void *dev_data; /* driver-private, entry-specific data */
536};
537
538int pci_simple_probe (const struct pci_simple_probe_entry *list,
539 size_t match_limit, pci_simple_probe_callback cb,
540 void *drvr_data);
541
542
543
544/*
545 * If the system does not have PCI, clearly these return errors. Define
546 * these as simple inline functions to avoid hair in drivers.
547 */
548
549/*
550 * The world is not perfect and supplies us with broken PCI devices.
551 * For at least a part of these bugs we need a work-around, so both
552 * generic (drivers/pci/quirks.c) and per-architecture code can define
553 * fixup hooks to be called for particular buggy devices.
554 */
555
556struct pci_fixup {
557 int pass;
558 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
559 void (*hook)(struct pci_dev *dev);
560};
561
562extern struct pci_fixup pcibios_fixups[];
563
564#define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
565#define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
566
567void pci_fixup_device(int pass, struct pci_dev *dev);
568
569extern int pci_pci_problems;
570#define PCIPCI_FAIL 1
571#define PCIPCI_TRITON 2
572#define PCIPCI_NATOMA 4
573
574
575struct pci_device_id {
576 unsigned int vendor, device;
577 unsigned int subvendor, subdevice;
578 unsigned int class, class_mask;
579 unsigned long driver_data;
580};
581#if 0
582struct pci_driver {
583 struct list_head node;
584 char *name;
585 const struct pci_device_id *id_table;
586 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
587 void (*remove)(struct pci_dev *dev);
588 void (*suspend)(struct pci_dev *dev, u32 state);
589 void (*resume)(struct pci_dev *dev);
590};
591#else
592struct pci_driver {
593 struct list_head node;
594 struct pci_dev *dev;
595 char *name;
596 const struct pci_device_id *id_table; /* NULL if wants all devices */
597 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
598 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
599 int (*suspend)(struct pci_dev *dev, u32 stgate); /* Device suspended */
600 int (*resume)(struct pci_dev *dev); /* Device woken up */
601};
602#endif
603
604/*
605 * Device identifier
606 */
607#define PM_PCI_ID(dev) ((dev)->bus->number << 16 | (dev)->devfn)
608
609#define PCI_GET_DRIVER_DATA pci_get_driver_data
610#define PCI_SET_DRIVER_DATA pci_set_driver_data
611
612int pci_register_driver(struct pci_driver *driver);
613int pci_module_init(struct pci_driver *drv);
614
615int pci_unregister_driver(struct pci_driver *driver);
616
617
618#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
619#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
620
621#define pci_for_each_dev(dev) \
622 for(dev = pci_devices; dev; dev = dev->next)
623
624#define pci_resource_start(dev,bar) \
625 (((dev)->resource[(bar)].flags & PCI_BASE_ADDRESS_SPACE) ? \
626 ((dev)->resource[(bar)].start & PCI_BASE_ADDRESS_IO_MASK) : \
627 ((dev)->resource[(bar)].start & PCI_BASE_ADDRESS_MEM_MASK))
628
629#define pci_resource_end(dev,bar) \
630 (((dev)->resource[(bar)].flags & PCI_BASE_ADDRESS_SPACE) ? \
631 ((dev)->resource[(bar)].end & PCI_BASE_ADDRESS_IO_MASK) : \
632 ((dev)->resource[(bar)].end & PCI_BASE_ADDRESS_MEM_MASK))
633
634/*
635 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
636 */
637#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
638
639#define pci_resource_len(dev,bar) \
640 ((pci_resource_start((dev),(bar)) == 0 && \
641 pci_resource_end((dev),(bar)) == \
642 pci_resource_start((dev),(bar))) ? 0 : \
643 \
644 (pci_resource_end((dev),(bar)) - \
645 pci_resource_start((dev),(bar))))
646
647extern struct pci_dev pci_devices[];
648extern struct pci_bus pci_busses[];
649
650/*
651 *
652 */
653const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, struct pci_dev *dev);
654unsigned long pci_get_size (struct pci_dev *dev, int n_base);
655
656int pci_get_flags (struct pci_dev *dev, int n_base);
657int pci_set_power_state(struct pci_dev *dev, int new_state);
658int pci_enable_device(struct pci_dev *dev);
659int pci_find_capability(struct pci_dev *dev, int cap);
660
661void *pci_alloc_consistent(struct pci_dev *, long, dma_addr_t *);
662void pci_free_consistent(struct pci_dev *, long, void *, dma_addr_t);
663
664int pci_dma_supported(struct pci_dev *, dma_addr_t mask);
665void pci_release_regions(struct pci_dev *pdev);
666int pci_request_regions(struct pci_dev *pdev, char *res_name);
667
668void pci_disable_device(struct pci_dev *dev);
669
670int pci_save_state(struct pci_dev *dev);
671int pci_restore_state(struct pci_dev *dev);
672
673unsigned long pci_get_dma_mask(struct pci_dev *);
674#define pci_set_dma_mask(pci, mask) (pci->dma_mask = mask, 0)
675
676void *pci_get_driver_data (struct pci_dev *dev);
677void pci_set_driver_data (struct pci_dev *dev, void *driver_data);
678
679#define pci_get_drvdata(a) pci_get_driver_data(a)
680#define pci_set_drvdata(a,b) pci_set_driver_data(a, b)
681
682#define PCI_DEVICE(vend,dev) \
683 .vendor = (vend), .device = (dev), \
684 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
685
686#define pci_get_device pci_find_device
687#define pci_dev_put(x)
688
689#pragma pack() //!!! by vladest
690
691#endif /* __KERNEL__ */
692
693static inline unsigned char snd_pci_revision(struct pci_dev *pci)
694{
695 unsigned char rev;
696 pci_read_config_byte(pci, PCI_REVISION_ID, &rev);
697 return rev;
698}
699
700/* pci_intx() wrapper */
701#define pci_intx(pci,x)
702
703/* MSI */
704extern int snd_pci_enable_msi(struct pci_dev *dev);
705#undef pci_enable_msi
706#define pci_enable_msi(dev) snd_pci_enable_msi(dev)
707#undef pci_disable_msi
708#define pci_disable_msi(dev)
709extern int snd_pci_dev_present(const struct pci_device_id *ids);
710#define pci_dev_present(x) snd_pci_dev_present(x)
711extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
712static inline void *pci_ioremap_bar(struct pci_dev *pdev, int bar)
713{
714 return __ioremap(pci_resource_start(pdev, bar),
715 pci_resource_len(pdev, bar),0x010);
716}
717
718#define PCI_VDEVICE(vendor, device) \
719 PCI_VENDOR_ID_##vendor, (device), \
720 PCI_ANY_ID, PCI_ANY_ID, 0, 0
721
722#define pci_clear_master(x)
723
724/* originally it's __devinitconst but we use __devinitdata to be compatible
725 * with older kernels
726 */
727#define DEFINE_PCI_DEVICE_TABLE(_table) \
728 const struct pci_device_id _table[] __devinitdata
729
730#endif /* LINUX_PCI_H */
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