source: GPL/trunk/include/asm/pgtable.h@ 596

Last change on this file since 596 was 416, checked in by Paul Smedley, 17 years ago

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1#ifndef _I386_PGTABLE_H
2#define _I386_PGTABLE_H
3
4#include <linux/config.h>
5
6/*
7 * The Linux memory management assumes a three-level page table setup. On
8 * the i386, we use that, but "fold" the mid level into the top-level page
9 * table, so that we physically have the same two-level page table as the
10 * i386 mmu expects.
11 *
12 * This file contains the functions and defines necessary to modify and use
13 * the i386 page table tree.
14 */
15#ifndef __ASSEMBLY__
16#include <asm/processor.h>
17#include <asm/fixmap.h>
18#include <linux/threads.h>
19
20extern pgd_t swapper_pg_dir[1024];
21
22/* Caches aren't brain-dead on the intel. */
23#define flush_cache_all() do { } while (0)
24#define flush_cache_mm(mm) do { } while (0)
25#define flush_cache_range(mm, start, end) do { } while (0)
26#define flush_cache_page(vma, vmaddr) do { } while (0)
27#define flush_page_to_ram(page) do { } while (0)
28#define flush_icache_range(start, end) do { } while (0)
29
30/*
31 * TLB flushing:
32 *
33 * - flush_tlb() flushes the current mm struct TLBs
34 * - flush_tlb_all() flushes all processes TLBs
35 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
36 * - flush_tlb_page(vma, vmaddr) flushes one page
37 * - flush_tlb_range(mm, start, end) flushes a range of pages
38 *
39 * ..but the i386 has somewhat limited tlb flushing capabilities,
40 * and page-granular flushes are available only on i486 and up.
41 */
42
43#define __flush_tlb() \
44do { unsigned long tmpreg; __asm__ __volatile__("movl %%cr3,%0\n\tmovl %0,%%cr3":"=r" (tmpreg) : :"memory"); } while (0)
45
46
47#endif /* !__ASSEMBLY__ */
48
49#define pgd_quicklist (current_cpu_data.pgd_quick)
50#define pmd_quicklist (current_cpu_data.pmd_quick)
51#define pte_quicklist (current_cpu_data.pte_quick)
52#define pgtable_cache_size (current_cpu_data.pgtable_cache_sz)
53
54/*
55 * The Linux x86 paging architecture is 'compile-time dual-mode', it
56 * implements both the traditional 2-level x86 page tables and the
57 * newer 3-level PAE-mode page tables.
58 */
59#ifndef __ASSEMBLY__
60#endif
61
62/*
63 * Certain architectures need to do special things when PTEs
64 * within a page table are directly modified. Thus, the following
65 * hook is made available.
66 */
67#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
68
69#define __beep() asm("movb $0x3,%al; outb %al,$0x61")
70
71/* PMD_SHIFT determines the size of the area a second-level page table can map */
72#define PMD_SHIFT 22
73#define PMD_SIZE (1UL << PMD_SHIFT)
74#define PMD_MASK (~(PMD_SIZE-1))
75
76/* PGDIR_SHIFT determines what a third-level page table entry can map */
77#define PGDIR_SHIFT 22
78#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
79#define PGDIR_MASK (~(PGDIR_SIZE-1))
80
81/*
82 * entries per page directory level: the i386 is two-level, so
83 * we don't really have any PMD directory physically.
84 */
85#define PTRS_PER_PTE 1024
86#define PTRS_PER_PMD 1
87#define PTRS_PER_PGD 1024
88#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
89
90
91#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
92#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
93
94#define TWOLEVEL_PGDIR_SHIFT 22
95#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
96#define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
97
98
99#ifndef __ASSEMBLY__
100/* Just any arbitrary offset to the start of the vmalloc VM area: the
101 * current 8MB value just means that there will be a 8MB "hole" after the
102 * physical memory until the kernel virtual memory starts. That means that
103 * any out-of-bounds memory accesses will hopefully be caught.
104 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
105 * area for the same reason. ;)
106 */
107#define VMALLOC_OFFSET (8*1024*1024)
108#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
109#define VMALLOC_VMADDR(x) ((unsigned long)(x))
110#define VMALLOC_END (FIXADDR_START)
111
112/*
113 * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
114 * of the Pentium details, but assuming intel did the straightforward
115 * thing, this bit set in the page directory entry just means that
116 * the page directory entry points directly to a 4MB-aligned block of
117 * memory.
118 */
119#define _PAGE_PRESENT 0x001
120#define _PAGE_RW 0x002
121#define _PAGE_USER 0x004
122#define _PAGE_PWT 0x008
123#define _PAGE_PCD 0x010
124#define _PAGE_ACCESSED 0x020
125#define _PAGE_DIRTY 0x040
126#define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
127#define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
128
129#define _PAGE_PROTNONE 0x080 /* If not present */
130
131#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
132#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
133#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
134
135#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
136#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
137#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
138#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
139#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
140#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED)
141
142/*
143 * The i386 can't do page protection for execute, and considers that the same are read.
144 * Also, write permissions imply read permissions. This is the closest we can get..
145 */
146#define __P000 PAGE_NONE
147#define __P001 PAGE_READONLY
148#define __P010 PAGE_COPY
149#define __P011 PAGE_COPY
150#define __P100 PAGE_READONLY
151#define __P101 PAGE_READONLY
152#define __P110 PAGE_COPY
153#define __P111 PAGE_COPY
154
155#define __S000 PAGE_NONE
156#define __S001 PAGE_READONLY
157#define __S010 PAGE_SHARED
158#define __S011 PAGE_SHARED
159#define __S100 PAGE_READONLY
160#define __S101 PAGE_READONLY
161#define __S110 PAGE_SHARED
162#define __S111 PAGE_SHARED
163
164/*
165 * Define this if things work differently on an i386 and an i486:
166 * it will (on an i486) warn about kernel memory accesses that are
167 * done without a 'verify_area(VERIFY_WRITE,..)'
168 */
169#undef TEST_VERIFY_AREA
170
171/* page table for 0-4MB for everybody */
172extern unsigned long pg0[1024];
173
174/*
175 * ZERO_PAGE is a global shared page that is always zero: used
176 * for zero-mapped memory areas etc..
177 */
178extern unsigned long empty_zero_page[1024];
179#define ZERO_PAGE(vaddr) (mem_map + MAP_NR(empty_zero_page))
180
181/*
182 * Handling allocation failures during page table setup.
183 */
184extern void __handle_bad_pmd(pmd_t * pmd);
185extern void __handle_bad_pmd_kernel(pmd_t * pmd);
186
187#define pte_none(x) (!pte_val(x))
188#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
189#define pte_clear(xp) do { pte_val(*(xp)) = 0; } while (0)
190#define pte_pagenr(x) ((unsigned long)((pte_val(x) >> PAGE_SHIFT)))
191
192#define pmd_none(x) (!pmd_val(x))
193#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
194#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
195#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
196
197/*
198 * Permanent address of a page. Obviously must never be
199 * called on a highmem page.
200 */
201#define page_address(page) page
202#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
203#define pte_page(x) (mem_map+pte_pagenr(x))
204
205/* Find an entry in the second-level page table.. */
206extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
207{
208 return (pmd_t *) dir;
209}
210
211/*
212 * The following only work if pte_present() is true.
213 * Undefined behaviour if not..
214 */
215#if 0
216#define pte_read(pte) (pte_val(pte) & _PAGE_USER)
217#define pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
218extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
219extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
220extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
221
222extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_USER; return pte; }
223extern inline pte_t pte_exprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_USER; return pte; }
224extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
225extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
226extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_RW; return pte; }
227extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) |= _PAGE_USER; return pte; }
228extern inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) |= _PAGE_USER; return pte; }
229extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
230extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
231extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pte; }
232#endif
233
234/*
235 * Conversion functions: convert a page and protection to a page entry,
236 * and a page entry and page directory to the page they refer to.
237 */
238
239
240/* This takes a physical page address that is used by the remapping functions */
241#define mk_pte_phys(physpage, pgprot) \
242({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
243
244//extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
245//{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
246
247#define page_pte(page) page_pte_prot(page, __pgprot(0))
248
249#define pmd_page(pmd) \
250((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
251
252/* to find an entry in a page-table-directory. */
253#define __pgd_offset(address) \
254 ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
255
256#define pgd_offset(mm, address) ((mm)->pgd+__pgd_offset(address))
257
258/* to find an entry in a kernel page-table-directory */
259#define pgd_offset_k(address) pgd_offset(&init_mm, address)
260
261#define __pmd_offset(address) \
262 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
263
264/* Find an entry in the third-level page table.. */
265#define __pte_offset(address) \
266 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
267#define pte_offset(dir, address) ((pte_t *) pmd_page(*(dir)) + \
268 __pte_offset(address))
269
270
271#if 0
272/*
273 * The i386 doesn't have any external MMU info: the kernel page
274 * tables contain all the necessary information.
275 */
276extern inline void update_mmu_cache(struct vm_area_struct * vma,
277 unsigned long address, pte_t pte)
278{
279}
280#endif
281
282/* Encode and de-code a swap entry */
283#define SWP_TYPE(x) (((x).val >> 1) & 0x3f)
284#define SWP_OFFSET(x) ((x).val >> 8)
285#define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
286#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
287#define swp_entry_to_pte(x) ((pte_t) { (x).val })
288
289#define module_map vmalloc
290#define module_unmap vfree
291
292#endif /* !__ASSEMBLY__ */
293
294/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
295#define PageSkip(page) (0)
296#define kern_addr_valid(addr) (1)
297
298#define io_remap_page_range remap_page_range
299
300#endif /* _I386_PGTABLE_H */
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