source: GPL/trunk/alsa-kernel/pci/maestro3.c@ 657

Last change on this file since 657 was 598, checked in by David Azarewicz, 9 years ago

Merged/reintegrated v2 branch into trunk. Trunk is now v2
File size: 88.3 KB
Line 
1/*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32#define DRIVER_NAME "Maestro3"
33
34#include <asm/io.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/init.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
41#include <linux/vmalloc.h>
42#include <linux/moduleparam.h>
43#include <linux/firmware.h>
44#include <linux/input.h>
45#include <sound/core.h>
46#include <sound/info.h>
47#include <sound/control.h>
48#include <sound/pcm.h>
49#include <sound/mpu401.h>
50#include <sound/ac97_codec.h>
51#include <sound/initval.h>
52#include <asm/byteorder.h>
53
54MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
55MODULE_DESCRIPTION("ESS Maestro3 PCI");
56MODULE_LICENSE("GPL");
57MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
58 "{ESS,ES1988},"
59 "{ESS,Allegro PCI},"
60 "{ESS,Allegro-1 PCI},"
61 "{ESS,Canyon3D-2/LE PCI}}");
62MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
63MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
64
65static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
66static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
67static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
68#ifndef TARGET_OS2
69static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
70static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
71#else
72static int external_amp[SNDRV_CARDS] = {REPEAT_SNDRV(1)};
73static int amp_gpio[SNDRV_CARDS] = {REPEAT_SNDRV(-1)};
74#endif
75module_param_array(index, int, NULL, 0444);
76MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
77module_param_array(id, charp, NULL, 0444);
78MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
79module_param_array(enable, bool, NULL, 0444);
80MODULE_PARM_DESC(enable, "Enable this soundcard.");
81module_param_array(external_amp, bool, NULL, 0444);
82MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
83module_param_array(amp_gpio, int, NULL, 0444);
84MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
85
86#define MAX_PLAYBACKS 2
87#define MAX_CAPTURES 1
88#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
89
90
91/*
92 * maestro3 registers
93 */
94
95/* Allegro PCI configuration registers */
96#define PCI_LEGACY_AUDIO_CTRL 0x40
97#define SOUND_BLASTER_ENABLE 0x00000001
98#define FM_SYNTHESIS_ENABLE 0x00000002
99#define GAME_PORT_ENABLE 0x00000004
100#define MPU401_IO_ENABLE 0x00000008
101#define MPU401_IRQ_ENABLE 0x00000010
102#define ALIAS_10BIT_IO 0x00000020
103#define SB_DMA_MASK 0x000000C0
104#define SB_DMA_0 0x00000040
105#define SB_DMA_1 0x00000040
106#define SB_DMA_R 0x00000080
107#define SB_DMA_3 0x000000C0
108#define SB_IRQ_MASK 0x00000700
109#define SB_IRQ_5 0x00000000
110#define SB_IRQ_7 0x00000100
111#define SB_IRQ_9 0x00000200
112#define SB_IRQ_10 0x00000300
113#define MIDI_IRQ_MASK 0x00003800
114#define SERIAL_IRQ_ENABLE 0x00004000
115#define DISABLE_LEGACY 0x00008000
116
117#define PCI_ALLEGRO_CONFIG 0x50
118#define SB_ADDR_240 0x00000004
119#define MPU_ADDR_MASK 0x00000018
120#define MPU_ADDR_330 0x00000000
121#define MPU_ADDR_300 0x00000008
122#define MPU_ADDR_320 0x00000010
123#define MPU_ADDR_340 0x00000018
124#define USE_PCI_TIMING 0x00000040
125#define POSTED_WRITE_ENABLE 0x00000080
126#define DMA_POLICY_MASK 0x00000700
127#define DMA_DDMA 0x00000000
128#define DMA_TDMA 0x00000100
129#define DMA_PCPCI 0x00000200
130#define DMA_WBDMA16 0x00000400
131#define DMA_WBDMA4 0x00000500
132#define DMA_WBDMA2 0x00000600
133#define DMA_WBDMA1 0x00000700
134#define DMA_SAFE_GUARD 0x00000800
135#define HI_PERF_GP_ENABLE 0x00001000
136#define PIC_SNOOP_MODE_0 0x00002000
137#define PIC_SNOOP_MODE_1 0x00004000
138#define SOUNDBLASTER_IRQ_MASK 0x00008000
139#define RING_IN_ENABLE 0x00010000
140#define SPDIF_TEST_MODE 0x00020000
141#define CLK_MULT_MODE_SELECT_2 0x00040000
142#define EEPROM_WRITE_ENABLE 0x00080000
143#define CODEC_DIR_IN 0x00100000
144#define HV_BUTTON_FROM_GD 0x00200000
145#define REDUCED_DEBOUNCE 0x00400000
146#define HV_CTRL_ENABLE 0x00800000
147#define SPDIF_ENABLE 0x01000000
148#define CLK_DIV_SELECT 0x06000000
149#define CLK_DIV_BY_48 0x00000000
150#define CLK_DIV_BY_49 0x02000000
151#define CLK_DIV_BY_50 0x04000000
152#define CLK_DIV_RESERVED 0x06000000
153#define PM_CTRL_ENABLE 0x08000000
154#define CLK_MULT_MODE_SELECT 0x30000000
155#define CLK_MULT_MODE_SHIFT 28
156#define CLK_MULT_MODE_0 0x00000000
157#define CLK_MULT_MODE_1 0x10000000
158#define CLK_MULT_MODE_2 0x20000000
159#define CLK_MULT_MODE_3 0x30000000
160#define INT_CLK_SELECT 0x40000000
161#define INT_CLK_MULT_RESET 0x80000000
162
163/* M3 */
164#define INT_CLK_SRC_NOT_PCI 0x00100000
165#define INT_CLK_MULT_ENABLE 0x80000000
166
167#define PCI_ACPI_CONTROL 0x54
168#define PCI_ACPI_D0 0x00000000
169#define PCI_ACPI_D1 0xB4F70000
170#define PCI_ACPI_D2 0xB4F7B4F7
171
172#define PCI_USER_CONFIG 0x58
173#define EXT_PCI_MASTER_ENABLE 0x00000001
174#define SPDIF_OUT_SELECT 0x00000002
175#define TEST_PIN_DIR_CTRL 0x00000004
176#define AC97_CODEC_TEST 0x00000020
177#define TRI_STATE_BUFFER 0x00000080
178#define IN_CLK_12MHZ_SELECT 0x00000100
179#define MULTI_FUNC_DISABLE 0x00000200
180#define EXT_MASTER_PAIR_SEL 0x00000400
181#define PCI_MASTER_SUPPORT 0x00000800
182#define STOP_CLOCK_ENABLE 0x00001000
183#define EAPD_DRIVE_ENABLE 0x00002000
184#define REQ_TRI_STATE_ENABLE 0x00004000
185#define REQ_LOW_ENABLE 0x00008000
186#define MIDI_1_ENABLE 0x00010000
187#define MIDI_2_ENABLE 0x00020000
188#define SB_AUDIO_SYNC 0x00040000
189#define HV_CTRL_TEST 0x00100000
190#define SOUNDBLASTER_TEST 0x00400000
191
192#define PCI_USER_CONFIG_C 0x5C
193
194#define PCI_DDMA_CTRL 0x60
195#define DDMA_ENABLE 0x00000001
196
197
198/* Allegro registers */
199#define HOST_INT_CTRL 0x18
200#define SB_INT_ENABLE 0x0001
201#define MPU401_INT_ENABLE 0x0002
202#define ASSP_INT_ENABLE 0x0010
203#define RING_INT_ENABLE 0x0020
204#define HV_INT_ENABLE 0x0040
205#define CLKRUN_GEN_ENABLE 0x0100
206#define HV_CTRL_TO_PME 0x0400
207#define SOFTWARE_RESET_ENABLE 0x8000
208
209/*
210 * should be using the above defines, probably.
211 */
212#define REGB_ENABLE_RESET 0x01
213#define REGB_STOP_CLOCK 0x10
214
215#define HOST_INT_STATUS 0x1A
216#define SB_INT_PENDING 0x01
217#define MPU401_INT_PENDING 0x02
218#define ASSP_INT_PENDING 0x10
219#define RING_INT_PENDING 0x20
220#define HV_INT_PENDING 0x40
221
222#define HARDWARE_VOL_CTRL 0x1B
223#define SHADOW_MIX_REG_VOICE 0x1C
224#define HW_VOL_COUNTER_VOICE 0x1D
225#define SHADOW_MIX_REG_MASTER 0x1E
226#define HW_VOL_COUNTER_MASTER 0x1F
227
228#define CODEC_COMMAND 0x30
229#define CODEC_READ_B 0x80
230
231#define CODEC_STATUS 0x30
232#define CODEC_BUSY_B 0x01
233
234#define CODEC_DATA 0x32
235
236#define RING_BUS_CTRL_A 0x36
237#define RAC_PME_ENABLE 0x0100
238#define RAC_SDFS_ENABLE 0x0200
239#define LAC_PME_ENABLE 0x0400
240#define LAC_SDFS_ENABLE 0x0800
241#define SERIAL_AC_LINK_ENABLE 0x1000
242#define IO_SRAM_ENABLE 0x2000
243#define IIS_INPUT_ENABLE 0x8000
244
245#define RING_BUS_CTRL_B 0x38
246#define SECOND_CODEC_ID_MASK 0x0003
247#define SPDIF_FUNC_ENABLE 0x0010
248#define SECOND_AC_ENABLE 0x0020
249#define SB_MODULE_INTF_ENABLE 0x0040
250#define SSPE_ENABLE 0x0040
251#define M3I_DOCK_ENABLE 0x0080
252
253#define SDO_OUT_DEST_CTRL 0x3A
254#define COMMAND_ADDR_OUT 0x0003
255#define PCM_LR_OUT_LOCAL 0x0000
256#define PCM_LR_OUT_REMOTE 0x0004
257#define PCM_LR_OUT_MUTE 0x0008
258#define PCM_LR_OUT_BOTH 0x000C
259#define LINE1_DAC_OUT_LOCAL 0x0000
260#define LINE1_DAC_OUT_REMOTE 0x0010
261#define LINE1_DAC_OUT_MUTE 0x0020
262#define LINE1_DAC_OUT_BOTH 0x0030
263#define PCM_CLS_OUT_LOCAL 0x0000
264#define PCM_CLS_OUT_REMOTE 0x0040
265#define PCM_CLS_OUT_MUTE 0x0080
266#define PCM_CLS_OUT_BOTH 0x00C0
267#define PCM_RLF_OUT_LOCAL 0x0000
268#define PCM_RLF_OUT_REMOTE 0x0100
269#define PCM_RLF_OUT_MUTE 0x0200
270#define PCM_RLF_OUT_BOTH 0x0300
271#define LINE2_DAC_OUT_LOCAL 0x0000
272#define LINE2_DAC_OUT_REMOTE 0x0400
273#define LINE2_DAC_OUT_MUTE 0x0800
274#define LINE2_DAC_OUT_BOTH 0x0C00
275#define HANDSET_OUT_LOCAL 0x0000
276#define HANDSET_OUT_REMOTE 0x1000
277#define HANDSET_OUT_MUTE 0x2000
278#define HANDSET_OUT_BOTH 0x3000
279#define IO_CTRL_OUT_LOCAL 0x0000
280#define IO_CTRL_OUT_REMOTE 0x4000
281#define IO_CTRL_OUT_MUTE 0x8000
282#define IO_CTRL_OUT_BOTH 0xC000
283
284#define SDO_IN_DEST_CTRL 0x3C
285#define STATUS_ADDR_IN 0x0003
286#define PCM_LR_IN_LOCAL 0x0000
287#define PCM_LR_IN_REMOTE 0x0004
288#define PCM_LR_RESERVED 0x0008
289#define PCM_LR_IN_BOTH 0x000C
290#define LINE1_ADC_IN_LOCAL 0x0000
291#define LINE1_ADC_IN_REMOTE 0x0010
292#define LINE1_ADC_IN_MUTE 0x0020
293#define MIC_ADC_IN_LOCAL 0x0000
294#define MIC_ADC_IN_REMOTE 0x0040
295#define MIC_ADC_IN_MUTE 0x0080
296#define LINE2_DAC_IN_LOCAL 0x0000
297#define LINE2_DAC_IN_REMOTE 0x0400
298#define LINE2_DAC_IN_MUTE 0x0800
299#define HANDSET_IN_LOCAL 0x0000
300#define HANDSET_IN_REMOTE 0x1000
301#define HANDSET_IN_MUTE 0x2000
302#define IO_STATUS_IN_LOCAL 0x0000
303#define IO_STATUS_IN_REMOTE 0x4000
304
305#define SPDIF_IN_CTRL 0x3E
306#define SPDIF_IN_ENABLE 0x0001
307
308#define GPIO_DATA 0x60
309#define GPIO_DATA_MASK 0x0FFF
310#define GPIO_HV_STATUS 0x3000
311#define GPIO_PME_STATUS 0x4000
312
313#define GPIO_MASK 0x64
314#define GPIO_DIRECTION 0x68
315#define GPO_PRIMARY_AC97 0x0001
316#define GPI_LINEOUT_SENSE 0x0004
317#define GPO_SECONDARY_AC97 0x0008
318#define GPI_VOL_DOWN 0x0010
319#define GPI_VOL_UP 0x0020
320#define GPI_IIS_CLK 0x0040
321#define GPI_IIS_LRCLK 0x0080
322#define GPI_IIS_DATA 0x0100
323#define GPI_DOCKING_STATUS 0x0100
324#define GPI_HEADPHONE_SENSE 0x0200
325#define GPO_EXT_AMP_SHUTDOWN 0x1000
326
327#define GPO_EXT_AMP_M3 1 /* default m3 amp */
328#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
329
330/* M3 */
331#define GPO_M3_EXT_AMP_SHUTDN 0x0002
332
333#define ASSP_INDEX_PORT 0x80
334#define ASSP_MEMORY_PORT 0x82
335#define ASSP_DATA_PORT 0x84
336
337#define MPU401_DATA_PORT 0x98
338#define MPU401_STATUS_PORT 0x99
339
340#define CLK_MULT_DATA_PORT 0x9C
341
342#define ASSP_CONTROL_A 0xA2
343#define ASSP_0_WS_ENABLE 0x01
344#define ASSP_CTRL_A_RESERVED1 0x02
345#define ASSP_CTRL_A_RESERVED2 0x04
346#define ASSP_CLK_49MHZ_SELECT 0x08
347#define FAST_PLU_ENABLE 0x10
348#define ASSP_CTRL_A_RESERVED3 0x20
349#define DSP_CLK_36MHZ_SELECT 0x40
350
351#define ASSP_CONTROL_B 0xA4
352#define RESET_ASSP 0x00
353#define RUN_ASSP 0x01
354#define ENABLE_ASSP_CLOCK 0x00
355#define STOP_ASSP_CLOCK 0x10
356#define RESET_TOGGLE 0x40
357
358#define ASSP_CONTROL_C 0xA6
359#define ASSP_HOST_INT_ENABLE 0x01
360#define FM_ADDR_REMAP_DISABLE 0x02
361#define HOST_WRITE_PORT_ENABLE 0x08
362
363#define ASSP_HOST_INT_STATUS 0xAC
364#define DSP2HOST_REQ_PIORECORD 0x01
365#define DSP2HOST_REQ_I2SRATE 0x02
366#define DSP2HOST_REQ_TIMER 0x04
367
368/* AC97 registers */
369/* XXX fix this crap up */
370/*#define AC97_RESET 0x00*/
371
372#define AC97_VOL_MUTE_B 0x8000
373#define AC97_VOL_M 0x1F
374#define AC97_LEFT_VOL_S 8
375
376#define AC97_MASTER_VOL 0x02
377#define AC97_LINE_LEVEL_VOL 0x04
378#define AC97_MASTER_MONO_VOL 0x06
379#define AC97_PC_BEEP_VOL 0x0A
380#define AC97_PC_BEEP_VOL_M 0x0F
381#define AC97_SROUND_MASTER_VOL 0x38
382#define AC97_PC_BEEP_VOL_S 1
383
384/*#define AC97_PHONE_VOL 0x0C
385#define AC97_MIC_VOL 0x0E*/
386#define AC97_MIC_20DB_ENABLE 0x40
387
388/*#define AC97_LINEIN_VOL 0x10
389#define AC97_CD_VOL 0x12
390#define AC97_VIDEO_VOL 0x14
391#define AC97_AUX_VOL 0x16*/
392#define AC97_PCM_OUT_VOL 0x18
393/*#define AC97_RECORD_SELECT 0x1A*/
394#define AC97_RECORD_MIC 0x00
395#define AC97_RECORD_CD 0x01
396#define AC97_RECORD_VIDEO 0x02
397#define AC97_RECORD_AUX 0x03
398#define AC97_RECORD_MONO_MUX 0x02
399#define AC97_RECORD_DIGITAL 0x03
400#define AC97_RECORD_LINE 0x04
401#define AC97_RECORD_STEREO 0x05
402#define AC97_RECORD_MONO 0x06
403#define AC97_RECORD_PHONE 0x07
404
405/*#define AC97_RECORD_GAIN 0x1C*/
406#define AC97_RECORD_VOL_M 0x0F
407
408/*#define AC97_GENERAL_PURPOSE 0x20*/
409#define AC97_POWER_DOWN_CTRL 0x26
410#define AC97_ADC_READY 0x0001
411#define AC97_DAC_READY 0x0002
412#define AC97_ANALOG_READY 0x0004
413#define AC97_VREF_ON 0x0008
414#define AC97_PR0 0x0100
415#define AC97_PR1 0x0200
416#define AC97_PR2 0x0400
417#define AC97_PR3 0x0800
418#define AC97_PR4 0x1000
419
420#define AC97_RESERVED1 0x28
421
422#define AC97_VENDOR_TEST 0x5A
423
424#define AC97_CLOCK_DELAY 0x5C
425#define AC97_LINEOUT_MUX_SEL 0x0001
426#define AC97_MONO_MUX_SEL 0x0002
427#define AC97_CLOCK_DELAY_SEL 0x1F
428#define AC97_DAC_CDS_SHIFT 6
429#define AC97_ADC_CDS_SHIFT 11
430
431#define AC97_MULTI_CHANNEL_SEL 0x74
432
433/*#define AC97_VENDOR_ID1 0x7C
434#define AC97_VENDOR_ID2 0x7E*/
435
436/*
437 * ASSP control regs
438 */
439#define DSP_PORT_TIMER_COUNT 0x06
440
441#define DSP_PORT_MEMORY_INDEX 0x80
442
443#define DSP_PORT_MEMORY_TYPE 0x82
444#define MEMTYPE_INTERNAL_CODE 0x0002
445#define MEMTYPE_INTERNAL_DATA 0x0003
446#define MEMTYPE_MASK 0x0003
447
448#define DSP_PORT_MEMORY_DATA 0x84
449
450#define DSP_PORT_CONTROL_REG_A 0xA2
451#define DSP_PORT_CONTROL_REG_B 0xA4
452#define DSP_PORT_CONTROL_REG_C 0xA6
453
454#define REV_A_CODE_MEMORY_BEGIN 0x0000
455#define REV_A_CODE_MEMORY_END 0x0FFF
456#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
457#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
458
459#define REV_B_CODE_MEMORY_BEGIN 0x0000
460#define REV_B_CODE_MEMORY_END 0x0BFF
461#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
462#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
463
464#define REV_A_DATA_MEMORY_BEGIN 0x1000
465#define REV_A_DATA_MEMORY_END 0x2FFF
466#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
467#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
468
469#define REV_B_DATA_MEMORY_BEGIN 0x1000
470#define REV_B_DATA_MEMORY_END 0x2BFF
471#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
472#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
473
474
475#define NUM_UNITS_KERNEL_CODE 16
476#define NUM_UNITS_KERNEL_DATA 2
477
478#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
479#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
480
481/*
482 * Kernel data layout
483 */
484
485#define DP_SHIFT_COUNT 7
486
487#define KDATA_BASE_ADDR 0x1000
488#define KDATA_BASE_ADDR2 0x1080
489
490#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
491#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
492#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
493#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
494#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
495#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
496#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
497#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
498#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
499
500#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
501#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
502
503#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
504#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
505#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
506#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
507#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
508#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
509#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
510#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
511#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
512#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
513
514#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
515#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
516
517#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
518#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
519
520#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
521#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
522
523#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
524#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
525#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
526
527#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
528#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
529#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
530#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
531#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
532
533#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
534#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
535#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
536
537#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
538#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
539#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
540
541#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
542#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
543#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
544#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
545#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
546#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
547#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
548#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
549#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
550#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
551
552#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
553#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
554#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
555
556#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
557#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
558
559#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
560#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
561#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
562
563#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
564#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
565#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
566#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
567#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
568#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
569
570#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
571#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
572#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
573#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
574#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
575#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
576
577#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
578#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
579#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
580#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
581#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
582#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
583
584#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
585#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
586#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
587#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
588
589#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
590#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
591
592#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
593#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
594
595#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
596#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
597#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
598#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
599#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
600
601#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
602#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
603
604#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
605#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
606#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
607
608#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
609#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
610
611#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
612
613#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
614#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
615#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
616#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
617#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
618#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
619#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
620#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
621#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
622#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
623#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
624#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
625
626#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
627#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
628#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
629#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
630
631#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
632#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
633
634#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
635#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
636#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
637#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
638
639#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
640#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
641#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
642#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
643#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
644
645/*
646 * second 'segment' (?) reserved for mixer
647 * buffers..
648 */
649
650#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
651#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
652#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
653#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
654#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
655#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
656#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
657#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
658#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
659#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
660#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
661#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
662#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
663#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
664#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
665#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
666
667#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
668#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
669#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
670#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
671#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
672#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
673#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
674#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
675#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
676#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
677#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
678
679#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
680#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
681#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
682#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
683#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
684#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
685
686#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
687#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
688#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
689#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
690
691/*
692 * client data area offsets
693 */
694#define CDATA_INSTANCE_READY 0x00
695
696#define CDATA_HOST_SRC_ADDRL 0x01
697#define CDATA_HOST_SRC_ADDRH 0x02
698#define CDATA_HOST_SRC_END_PLUS_1L 0x03
699#define CDATA_HOST_SRC_END_PLUS_1H 0x04
700#define CDATA_HOST_SRC_CURRENTL 0x05
701#define CDATA_HOST_SRC_CURRENTH 0x06
702
703#define CDATA_IN_BUF_CONNECT 0x07
704#define CDATA_OUT_BUF_CONNECT 0x08
705
706#define CDATA_IN_BUF_BEGIN 0x09
707#define CDATA_IN_BUF_END_PLUS_1 0x0A
708#define CDATA_IN_BUF_HEAD 0x0B
709#define CDATA_IN_BUF_TAIL 0x0C
710#define CDATA_OUT_BUF_BEGIN 0x0D
711#define CDATA_OUT_BUF_END_PLUS_1 0x0E
712#define CDATA_OUT_BUF_HEAD 0x0F
713#define CDATA_OUT_BUF_TAIL 0x10
714
715#define CDATA_DMA_CONTROL 0x11
716#define CDATA_RESERVED 0x12
717
718#define CDATA_FREQUENCY 0x13
719#define CDATA_LEFT_VOLUME 0x14
720#define CDATA_RIGHT_VOLUME 0x15
721#define CDATA_LEFT_SUR_VOL 0x16
722#define CDATA_RIGHT_SUR_VOL 0x17
723
724#define CDATA_HEADER_LEN 0x18
725
726#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
727#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
728#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
729#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
730#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
731#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
732#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
733#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
734
735#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
736#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
737#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
738#define MINISRC_BIQUAD_STAGE 2
739#define MINISRC_COEF_LOC 0x175
740
741#define DMACONTROL_BLOCK_MASK 0x000F
742#define DMAC_BLOCK0_SELECTOR 0x0000
743#define DMAC_BLOCK1_SELECTOR 0x0001
744#define DMAC_BLOCK2_SELECTOR 0x0002
745#define DMAC_BLOCK3_SELECTOR 0x0003
746#define DMAC_BLOCK4_SELECTOR 0x0004
747#define DMAC_BLOCK5_SELECTOR 0x0005
748#define DMAC_BLOCK6_SELECTOR 0x0006
749#define DMAC_BLOCK7_SELECTOR 0x0007
750#define DMAC_BLOCK8_SELECTOR 0x0008
751#define DMAC_BLOCK9_SELECTOR 0x0009
752#define DMAC_BLOCKA_SELECTOR 0x000A
753#define DMAC_BLOCKB_SELECTOR 0x000B
754#define DMAC_BLOCKC_SELECTOR 0x000C
755#define DMAC_BLOCKD_SELECTOR 0x000D
756#define DMAC_BLOCKE_SELECTOR 0x000E
757#define DMAC_BLOCKF_SELECTOR 0x000F
758#define DMACONTROL_PAGE_MASK 0x00F0
759#define DMAC_PAGE0_SELECTOR 0x0030
760#define DMAC_PAGE1_SELECTOR 0x0020
761#define DMAC_PAGE2_SELECTOR 0x0010
762#define DMAC_PAGE3_SELECTOR 0x0000
763#define DMACONTROL_AUTOREPEAT 0x1000
764#define DMACONTROL_STOPPED 0x2000
765#define DMACONTROL_DIRECTION 0x0100
766
767/*
768 * an arbitrary volume we set the internal
769 * volume settings to so that the ac97 volume
770 * range is a little less insane. 0x7fff is
771 * max.
772 */
773#define ARB_VOLUME ( 0x6800 )
774
775/*
776 */
777
778struct m3_list {
779 int curlen;
780 int mem_addr;
781 int max;
782};
783
784struct m3_dma {
785
786 int number;
787 struct snd_pcm_substream *substream;
788
789 struct assp_instance {
790 unsigned short code, data;
791 } inst;
792
793 int running;
794 int opened;
795
796 unsigned long buffer_addr;
797 int dma_size;
798 int period_size;
799 unsigned int hwptr;
800 int count;
801
802 int index[3];
803 struct m3_list *index_list[3];
804
805 int in_lists;
806
807 struct list_head list;
808
809};
810
811struct snd_m3 {
812
813 struct snd_card *card;
814
815 unsigned long iobase;
816
817 int irq;
818 unsigned int allegro_flag : 1;
819
820 struct snd_ac97 *ac97;
821
822 struct snd_pcm *pcm;
823
824 struct pci_dev *pci;
825
826 int dacs_active;
827 int timer_users;
828
829 struct m3_list msrc_list;
830 struct m3_list mixer_list;
831 struct m3_list adc1_list;
832 struct m3_list dma_list;
833
834 /* for storing reset state..*/
835 u8 reset_state;
836
837 int external_amp;
838 int amp_gpio; /* gpio pin # for external amp, -1 = default */
839 unsigned int hv_config; /* hardware-volume config bits */
840 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
841 (e.g. for IrDA on Dell Inspirons) */
842 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
843
844 /* midi */
845 struct snd_rawmidi *rmidi;
846
847 /* pcm streams */
848 int num_substreams;
849 struct m3_dma *substreams;
850
851 spinlock_t reg_lock;
852
853#ifdef CONFIG_SND_MAESTRO3_INPUT
854 struct input_dev *input_dev;
855 char phys[64]; /* physical device path */
856#else
857 spinlock_t ac97_lock;
858 struct snd_kcontrol *master_switch;
859 struct snd_kcontrol *master_volume;
860 struct tasklet_struct hwvol_tq;
861#endif
862
863 unsigned int in_suspend;
864
865#ifdef CONFIG_PM
866 u16 *suspend_mem;
867#endif
868
869 const struct firmware *assp_kernel_image;
870 const struct firmware *assp_minisrc_image;
871};
872
873/*
874 * pci ids
875 */
876static DEFINE_PCI_DEVICE_TABLE(snd_m3_ids) = {
877 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
878 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
880 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
882 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
883 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
884 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
885 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
886 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
887 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
888 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
889 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
890 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
891 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
892 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
893 {0,},
894};
895
896MODULE_DEVICE_TABLE(pci, snd_m3_ids);
897
898static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
899 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
900 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
901 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
902 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
903 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
904 {0} /* END */
905};
906
907static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
908 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
909 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
910 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
911 {0} /* END */
912};
913
914/* hardware volume quirks */
915static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
916 /* Allegro chips */
917 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
932 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
933 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
934 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
935 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
936 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
937 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
938 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
939 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
940 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
941 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
942 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
943 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
944 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
945 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
946 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
947 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
948 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
949 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
950 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
951 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
952 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
953 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
954 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
955 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
956 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
957 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
958 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
959 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
960 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
961 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
962 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
963 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
964 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
965 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
966 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
971 /* Maestro3 chips */
972 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
975 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
976 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
977 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
978 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
979 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
980 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
981 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
982 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
983 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
984 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
985 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
986 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
987 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
988 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
989 {0} /* END */
990};
991
992/* HP Omnibook quirks */
993static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
994 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
995 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
996 {0} /* END */
997};
998
999/*
1000 * lowlevel functions
1001 */
1002
1003static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
1004{
1005 outw(value, chip->iobase + reg);
1006}
1007
1008static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1009{
1010 return inw(chip->iobase + reg);
1011}
1012
1013static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1014{
1015 outb(value, chip->iobase + reg);
1016}
1017
1018static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1019{
1020 return inb(chip->iobase + reg);
1021}
1022
1023/*
1024 * access 16bit words to the code or data regions of the dsp's memory.
1025 * index addresses 16bit words.
1026 */
1027static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1028{
1029 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1030 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1031 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1032}
1033
1034static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1035{
1036 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1037 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1038 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1039}
1040
1041static void snd_m3_assp_halt(struct snd_m3 *chip)
1042{
1043 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1044 msleep(10);
1045 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1046}
1047
1048static void snd_m3_assp_continue(struct snd_m3 *chip)
1049{
1050 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1051}
1052
1053
1054/*
1055 * This makes me sad. the maestro3 has lists
1056 * internally that must be packed.. 0 terminates,
1057 * apparently, or maybe all unused entries have
1058 * to be 0, the lists have static lengths set
1059 * by the binary code images.
1060 */
1061
1062static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1063{
1064 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1065 list->mem_addr + list->curlen,
1066 val);
1067 return list->curlen++;
1068}
1069
1070static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1071{
1072 u16 val;
1073 int lastindex = list->curlen - 1;
1074
1075 if (index != lastindex) {
1076 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1077 list->mem_addr + lastindex);
1078 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1079 list->mem_addr + index,
1080 val);
1081 }
1082
1083 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084 list->mem_addr + lastindex,
1085 0);
1086
1087 list->curlen--;
1088}
1089
1090static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1091{
1092 chip->timer_users++;
1093 if (chip->timer_users != 1)
1094 return;
1095
1096 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1097 KDATA_TIMER_COUNT_RELOAD,
1098 240);
1099
1100 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1101 KDATA_TIMER_COUNT_CURRENT,
1102 240);
1103
1104 snd_m3_outw(chip,
1105 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1106 HOST_INT_CTRL);
1107}
1108
1109static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1110{
1111 chip->timer_users--;
1112 if (chip->timer_users > 0)
1113 return;
1114
1115 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1116 KDATA_TIMER_COUNT_RELOAD,
1117 0);
1118
1119 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1120 KDATA_TIMER_COUNT_CURRENT,
1121 0);
1122
1123 snd_m3_outw(chip,
1124 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1125 HOST_INT_CTRL);
1126}
1127
1128/*
1129 * start/stop
1130 */
1131
1132/* spinlock held! */
1133static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1134 struct snd_pcm_substream *subs)
1135{
1136 if (! s || ! subs)
1137 return -EINVAL;
1138
1139 snd_m3_inc_timer_users(chip);
1140 switch (subs->stream) {
1141 case SNDRV_PCM_STREAM_PLAYBACK:
1142 chip->dacs_active++;
1143 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1144 s->inst.data + CDATA_INSTANCE_READY, 1);
1145 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1146 KDATA_MIXER_TASK_NUMBER,
1147 chip->dacs_active);
1148 break;
1149 case SNDRV_PCM_STREAM_CAPTURE:
1150 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1151 KDATA_ADC1_REQUEST, 1);
1152 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1153 s->inst.data + CDATA_INSTANCE_READY, 1);
1154 break;
1155 }
1156 return 0;
1157}
1158
1159/* spinlock held! */
1160static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1161 struct snd_pcm_substream *subs)
1162{
1163 if (! s || ! subs)
1164 return -EINVAL;
1165
1166 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167 s->inst.data + CDATA_INSTANCE_READY, 0);
1168 snd_m3_dec_timer_users(chip);
1169 switch (subs->stream) {
1170 case SNDRV_PCM_STREAM_PLAYBACK:
1171 chip->dacs_active--;
1172 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1173 KDATA_MIXER_TASK_NUMBER,
1174 chip->dacs_active);
1175 break;
1176 case SNDRV_PCM_STREAM_CAPTURE:
1177 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1178 KDATA_ADC1_REQUEST, 0);
1179 break;
1180 }
1181 return 0;
1182}
1183
1184static int
1185snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1186{
1187 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1188 struct m3_dma *s = subs->runtime->private_data;
1189 int err = -EINVAL;
1190
1191 if (snd_BUG_ON(!s))
1192 return -ENXIO;
1193
1194 spin_lock(&chip->reg_lock);
1195 switch (cmd) {
1196 case SNDRV_PCM_TRIGGER_START:
1197 case SNDRV_PCM_TRIGGER_RESUME:
1198 if (s->running)
1199 err = -EBUSY;
1200 else {
1201 s->running = 1;
1202 err = snd_m3_pcm_start(chip, s, subs);
1203 }
1204 break;
1205 case SNDRV_PCM_TRIGGER_STOP:
1206 case SNDRV_PCM_TRIGGER_SUSPEND:
1207 if (! s->running)
1208 err = 0; /* should return error? */
1209 else {
1210 s->running = 0;
1211 err = snd_m3_pcm_stop(chip, s, subs);
1212 }
1213 break;
1214 }
1215 spin_unlock(&chip->reg_lock);
1216 return err;
1217}
1218
1219/*
1220 * setup
1221 */
1222static void
1223snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1224{
1225 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1226 struct snd_pcm_runtime *runtime = subs->runtime;
1227
1228 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1229 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1230 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1231 } else {
1232 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1233 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1234 }
1235 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1236 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1237
1238 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1239 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1240 s->hwptr = 0;
1241 s->count = 0;
1242
1243#define LO(x) ((x) & 0xffff)
1244#define HI(x) LO((x) >> 16)
1245
1246 /* host dma buffer pointers */
1247 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1248 s->inst.data + CDATA_HOST_SRC_ADDRL,
1249 LO(s->buffer_addr));
1250
1251 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1252 s->inst.data + CDATA_HOST_SRC_ADDRH,
1253 HI(s->buffer_addr));
1254
1255 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1256 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1257 LO(s->buffer_addr + s->dma_size));
1258
1259 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1260 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1261 HI(s->buffer_addr + s->dma_size));
1262
1263 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1264 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1265 LO(s->buffer_addr));
1266
1267 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1268 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1269 HI(s->buffer_addr));
1270#undef LO
1271#undef HI
1272
1273 /* dsp buffers */
1274
1275 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1276 s->inst.data + CDATA_IN_BUF_BEGIN,
1277 dsp_in_buffer);
1278
1279 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1280 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1281 dsp_in_buffer + (dsp_in_size / 2));
1282
1283 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1284 s->inst.data + CDATA_IN_BUF_HEAD,
1285 dsp_in_buffer);
1286
1287 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1288 s->inst.data + CDATA_IN_BUF_TAIL,
1289 dsp_in_buffer);
1290
1291 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1292 s->inst.data + CDATA_OUT_BUF_BEGIN,
1293 dsp_out_buffer);
1294
1295 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1296 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1297 dsp_out_buffer + (dsp_out_size / 2));
1298
1299 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1300 s->inst.data + CDATA_OUT_BUF_HEAD,
1301 dsp_out_buffer);
1302
1303 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1304 s->inst.data + CDATA_OUT_BUF_TAIL,
1305 dsp_out_buffer);
1306}
1307
1308static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1309 struct snd_pcm_runtime *runtime)
1310{
1311 u32 freq;
1312
1313 /*
1314 * put us in the lists if we're not already there
1315 */
1316 if (! s->in_lists) {
1317 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1318 s->inst.data >> DP_SHIFT_COUNT);
1319 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1320 s->inst.data >> DP_SHIFT_COUNT);
1321 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1322 s->inst.data >> DP_SHIFT_COUNT);
1323 s->in_lists = 1;
1324 }
1325
1326 /* write to 'mono' word */
1327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1328 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1329 runtime->channels == 2 ? 0 : 1);
1330 /* write to '8bit' word */
1331 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1332 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1333 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1334
1335 /* set up dac/adc rate */
1336 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1337 if (freq)
1338 freq--;
1339
1340 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1341 s->inst.data + CDATA_FREQUENCY,
1342 freq);
1343}
1344
1345
1346static const struct play_vals {
1347 u16 addr, val;
1348} pv[] = {
1349 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1350 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1351 {SRC3_DIRECTION_OFFSET, 0} ,
1352 /* +1, +2 are stereo/16 bit */
1353 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1354 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1355 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1356 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1357 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1358 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1359 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1360 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1361 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1362 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1363 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1364 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1365 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1366 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1367 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1368 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1369 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1370};
1371
1372
1373/* the mode passed should be already shifted and masked */
1374static void
1375snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1376 struct snd_pcm_substream *subs)
1377{
1378 unsigned int i;
1379
1380 /*
1381 * some per client initializers
1382 */
1383
1384 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1385 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1386 s->inst.data + 40 + 8);
1387
1388 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1389 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1390 s->inst.code + MINISRC_COEF_LOC);
1391
1392 /* enable or disable low pass filter? */
1393 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1394 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1395 subs->runtime->rate > 45000 ? 0xff : 0);
1396
1397 /* tell it which way dma is going? */
1398 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1399 s->inst.data + CDATA_DMA_CONTROL,
1400 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1401
1402 /*
1403 * set an armload of static initializers
1404 */
1405 for (i = 0; i < ARRAY_SIZE(pv); i++)
1406 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1407 s->inst.data + pv[i].addr, pv[i].val);
1408}
1409
1410/*
1411 * Native record driver
1412 */
1413static const struct rec_vals {
1414 u16 addr, val;
1415} rv[] = {
1416 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1417 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1418 {SRC3_DIRECTION_OFFSET, 1} ,
1419 /* +1, +2 are stereo/16 bit */
1420 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1421 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1422 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1423 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1424 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1425 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1426 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1427 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1428 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1429 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1430 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1431 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1432 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1433 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1434 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1435 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1436 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1437 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1438 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1439};
1440
1441static void
1442snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1443{
1444 unsigned int i;
1445
1446 /*
1447 * some per client initializers
1448 */
1449
1450 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1451 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1452 s->inst.data + 40 + 8);
1453
1454 /* tell it which way dma is going? */
1455 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1456 s->inst.data + CDATA_DMA_CONTROL,
1457 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1458 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1459
1460 /*
1461 * set an armload of static initializers
1462 */
1463 for (i = 0; i < ARRAY_SIZE(rv); i++)
1464 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1465 s->inst.data + rv[i].addr, rv[i].val);
1466}
1467
1468static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1469 struct snd_pcm_hw_params *hw_params)
1470{
1471 struct m3_dma *s = substream->runtime->private_data;
1472 int err;
1473
1474 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1475 return err;
1476 /* set buffer address */
1477 s->buffer_addr = substream->runtime->dma_addr;
1478 if (s->buffer_addr & 0x3) {
1479 snd_printk(KERN_ERR "oh my, not aligned\n");
1480 s->buffer_addr = s->buffer_addr & ~0x3;
1481 }
1482 return 0;
1483}
1484
1485static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1486{
1487 struct m3_dma *s;
1488
1489 if (substream->runtime->private_data == NULL)
1490 return 0;
1491 s = substream->runtime->private_data;
1492 snd_pcm_lib_free_pages(substream);
1493 s->buffer_addr = 0;
1494 return 0;
1495}
1496
1497static int
1498snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1499{
1500 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1501 struct snd_pcm_runtime *runtime = subs->runtime;
1502 struct m3_dma *s = runtime->private_data;
1503
1504 if (snd_BUG_ON(!s))
1505 return -ENXIO;
1506
1507 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1508 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1509 return -EINVAL;
1510 if (runtime->rate > 48000 ||
1511 runtime->rate < 8000)
1512 return -EINVAL;
1513
1514 spin_lock_irq(&chip->reg_lock);
1515
1516 snd_m3_pcm_setup1(chip, s, subs);
1517
1518 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1519 snd_m3_playback_setup(chip, s, subs);
1520 else
1521 snd_m3_capture_setup(chip, s, subs);
1522
1523 snd_m3_pcm_setup2(chip, s, runtime);
1524
1525 spin_unlock_irq(&chip->reg_lock);
1526
1527 return 0;
1528}
1529
1530/*
1531 * get current pointer
1532 */
1533static unsigned int
1534snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1535{
1536 u16 hi = 0, lo = 0;
1537 int retry = 10;
1538 u32 addr;
1539
1540 /*
1541 * try and get a valid answer
1542 */
1543 while (retry--) {
1544 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1545 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1546
1547 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1548 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1549
1550 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1551 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1552 break;
1553 }
1554 addr = lo | ((u32)hi<<16);
1555 return (unsigned int)(addr - s->buffer_addr);
1556}
1557
1558static snd_pcm_uframes_t
1559snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1560{
1561 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1562 unsigned int ptr;
1563 struct m3_dma *s = subs->runtime->private_data;
1564
1565 if (snd_BUG_ON(!s))
1566 return 0;
1567
1568 spin_lock(&chip->reg_lock);
1569 ptr = snd_m3_get_pointer(chip, s, subs);
1570 spin_unlock(&chip->reg_lock);
1571 return bytes_to_frames(subs->runtime, ptr);
1572}
1573
1574
1575/* update pointer */
1576/* spinlock held! */
1577static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1578{
1579 struct snd_pcm_substream *subs = s->substream;
1580 unsigned int hwptr;
1581 int diff;
1582
1583 if (! s->running)
1584 return;
1585
1586 hwptr = snd_m3_get_pointer(chip, s, subs);
1587
1588 /* try to avoid expensive modulo divisions */
1589 if (hwptr >= s->dma_size)
1590 hwptr %= s->dma_size;
1591
1592 diff = s->dma_size + hwptr - s->hwptr;
1593 if (diff >= s->dma_size)
1594 diff %= s->dma_size;
1595
1596 s->hwptr = hwptr;
1597 s->count += diff;
1598
1599 if (s->count >= (signed)s->period_size) {
1600
1601 if (s->count < 2 * (signed)s->period_size)
1602 s->count -= (signed)s->period_size;
1603 else
1604 s->count %= s->period_size;
1605
1606 spin_unlock(&chip->reg_lock);
1607 snd_pcm_period_elapsed(subs);
1608 spin_lock(&chip->reg_lock);
1609 }
1610}
1611
1612/* The m3's hardware volume works by incrementing / decrementing 2 counters
1613 (without wrap around) in response to volume button presses and then
1614 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1615 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1616static void snd_m3_update_hw_volume(unsigned long private_data)
1617{
1618 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1619 int x, val;
1620#ifndef CONFIG_SND_MAESTRO3_INPUT
1621 unsigned long flags;
1622#endif
1623
1624 /* Figure out which volume control button was pushed,
1625 based on differences from the default register
1626 values. */
1627 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1628
1629 /* Reset the volume counters to 4. Tests on the allegro integrated
1630 into a Compaq N600C laptop, have revealed that:
1631 1) Writing any value will result in the 2 counters being reset to
1632 4 so writing 0x88 is not strictly necessary
1633 2) Writing to any of the 4 involved registers will reset all 4
1634 of them (and reading them always returns the same value for all
1635 of them)
1636 It could be that a maestro deviates from this, so leave the code
1637 as is. */
1638 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1639 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1640 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1641 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1642
1643 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1644 mistaking them for a mute button press. */
1645 if (chip->in_suspend)
1646 return;
1647
1648#ifndef CONFIG_SND_MAESTRO3_INPUT
1649 if (!chip->master_switch || !chip->master_volume)
1650 return;
1651
1652 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1653 spin_lock_irqsave(&chip->ac97_lock, flags);
1654
1655 val = chip->ac97->regs[AC97_MASTER_VOL];
1656 switch (x) {
1657 case 0x88:
1658 /* The counters have not changed, yet we've received a HV
1659 interrupt. According to tests run by various people this
1660 happens when pressing the mute button. */
1661 val ^= 0x8000;
1662 chip->ac97->regs[AC97_MASTER_VOL] = val;
1663 outw(val, chip->iobase + CODEC_DATA);
1664 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1665 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1666 &chip->master_switch->id);
1667 break;
1668 case 0xaa:
1669 /* counters increased by 1 -> volume up */
1670 if ((val & 0x7f) > 0)
1671 val--;
1672 if ((val & 0x7f00) > 0)
1673 val -= 0x0100;
1674 chip->ac97->regs[AC97_MASTER_VOL] = val;
1675 outw(val, chip->iobase + CODEC_DATA);
1676 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1677 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1678 &chip->master_volume->id);
1679 break;
1680 case 0x66:
1681 /* counters decreased by 1 -> volume down */
1682 if ((val & 0x7f) < 0x1f)
1683 val++;
1684 if ((val & 0x7f00) < 0x1f00)
1685 val += 0x0100;
1686 chip->ac97->regs[AC97_MASTER_VOL] = val;
1687 outw(val, chip->iobase + CODEC_DATA);
1688 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1689 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1690 &chip->master_volume->id);
1691 break;
1692 }
1693 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1694#else
1695 if (!chip->input_dev)
1696 return;
1697
1698 val = 0;
1699 switch (x) {
1700 case 0x88:
1701 /* The counters have not changed, yet we've received a HV
1702 interrupt. According to tests run by various people this
1703 happens when pressing the mute button. */
1704 val = KEY_MUTE;
1705 break;
1706 case 0xaa:
1707 /* counters increased by 1 -> volume up */
1708 val = KEY_VOLUMEUP;
1709 break;
1710 case 0x66:
1711 /* counters decreased by 1 -> volume down */
1712 val = KEY_VOLUMEDOWN;
1713 break;
1714 }
1715
1716 if (val) {
1717 input_report_key(chip->input_dev, val, 1);
1718 input_sync(chip->input_dev);
1719 input_report_key(chip->input_dev, val, 0);
1720 input_sync(chip->input_dev);
1721 }
1722#endif
1723}
1724
1725static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1726{
1727 struct snd_m3 *chip = dev_id;
1728 u8 status;
1729 int i;
1730
1731 status = inb(chip->iobase + HOST_INT_STATUS);
1732
1733 if (status == 0xff)
1734 return IRQ_NONE;
1735
1736 if (status & HV_INT_PENDING)
1737#ifdef CONFIG_SND_MAESTRO3_INPUT
1738 snd_m3_update_hw_volume((unsigned long)chip);
1739#else
1740 tasklet_schedule(&chip->hwvol_tq);
1741#endif
1742
1743 /*
1744 * ack an assp int if its running
1745 * and has an int pending
1746 */
1747 if (status & ASSP_INT_PENDING) {
1748 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1749 if (!(ctl & STOP_ASSP_CLOCK)) {
1750 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1751 if (ctl & DSP2HOST_REQ_TIMER) {
1752 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1753 /* update adc/dac info if it was a timer int */
1754 spin_lock(&chip->reg_lock);
1755 for (i = 0; i < chip->num_substreams; i++) {
1756 struct m3_dma *s = &chip->substreams[i];
1757 if (s->running)
1758 snd_m3_update_ptr(chip, s);
1759 }
1760 spin_unlock(&chip->reg_lock);
1761 }
1762 }
1763 }
1764
1765#if 0 /* TODO: not supported yet */
1766 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1767 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1768#endif
1769
1770 /* ack ints */
1771 outb(status, chip->iobase + HOST_INT_STATUS);
1772
1773 return IRQ_HANDLED;
1774}
1775
1776
1777/*
1778 */
1779
1780static struct snd_pcm_hardware snd_m3_playback =
1781{
1782 .info = (SNDRV_PCM_INFO_MMAP |
1783 SNDRV_PCM_INFO_INTERLEAVED |
1784 SNDRV_PCM_INFO_MMAP_VALID |
1785 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1786 /*SNDRV_PCM_INFO_PAUSE |*/
1787 SNDRV_PCM_INFO_RESUME),
1788 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1789 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1790 .rate_min = 8000,
1791 .rate_max = 48000,
1792 .channels_min = 1,
1793 .channels_max = 2,
1794 .buffer_bytes_max = (512*1024),
1795 .period_bytes_min = 64,
1796 .period_bytes_max = (512*1024),
1797 .periods_min = 1,
1798 .periods_max = 1024,
1799};
1800
1801static struct snd_pcm_hardware snd_m3_capture =
1802{
1803 .info = (SNDRV_PCM_INFO_MMAP |
1804 SNDRV_PCM_INFO_INTERLEAVED |
1805 SNDRV_PCM_INFO_MMAP_VALID |
1806 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1807 /*SNDRV_PCM_INFO_PAUSE |*/
1808 SNDRV_PCM_INFO_RESUME),
1809 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1810 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1811 .rate_min = 8000,
1812 .rate_max = 48000,
1813 .channels_min = 1,
1814 .channels_max = 2,
1815 .buffer_bytes_max = (512*1024),
1816 .period_bytes_min = 64,
1817 .period_bytes_max = (512*1024),
1818 .periods_min = 1,
1819 .periods_max = 1024,
1820};
1821
1822
1823/*
1824 */
1825
1826static int
1827snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1828{
1829 int i;
1830 struct m3_dma *s;
1831
1832 spin_lock_irq(&chip->reg_lock);
1833 for (i = 0; i < chip->num_substreams; i++) {
1834 s = &chip->substreams[i];
1835 if (! s->opened)
1836 goto __found;
1837 }
1838 spin_unlock_irq(&chip->reg_lock);
1839 return -ENOMEM;
1840__found:
1841 s->opened = 1;
1842 s->running = 0;
1843 spin_unlock_irq(&chip->reg_lock);
1844
1845 subs->runtime->private_data = s;
1846 s->substream = subs;
1847
1848 /* set list owners */
1849 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1850 s->index_list[0] = &chip->mixer_list;
1851 } else
1852 s->index_list[0] = &chip->adc1_list;
1853 s->index_list[1] = &chip->msrc_list;
1854 s->index_list[2] = &chip->dma_list;
1855
1856 return 0;
1857}
1858
1859static void
1860snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1861{
1862 struct m3_dma *s = subs->runtime->private_data;
1863
1864 if (s == NULL)
1865 return; /* not opened properly */
1866
1867 spin_lock_irq(&chip->reg_lock);
1868 if (s->substream && s->running)
1869 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1870 if (s->in_lists) {
1871 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1872 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1873 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1874 s->in_lists = 0;
1875 }
1876 s->running = 0;
1877 s->opened = 0;
1878 spin_unlock_irq(&chip->reg_lock);
1879}
1880
1881static int
1882snd_m3_playback_open(struct snd_pcm_substream *subs)
1883{
1884 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1885 struct snd_pcm_runtime *runtime = subs->runtime;
1886 int err;
1887
1888 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1889 return err;
1890
1891 runtime->hw = snd_m3_playback;
1892
1893 return 0;
1894}
1895
1896static int
1897snd_m3_playback_close(struct snd_pcm_substream *subs)
1898{
1899 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1900
1901 snd_m3_substream_close(chip, subs);
1902 return 0;
1903}
1904
1905static int
1906snd_m3_capture_open(struct snd_pcm_substream *subs)
1907{
1908 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1909 struct snd_pcm_runtime *runtime = subs->runtime;
1910 int err;
1911
1912 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1913 return err;
1914
1915 runtime->hw = snd_m3_capture;
1916
1917 return 0;
1918}
1919
1920static int
1921snd_m3_capture_close(struct snd_pcm_substream *subs)
1922{
1923 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1924
1925 snd_m3_substream_close(chip, subs);
1926 return 0;
1927}
1928
1929/*
1930 * create pcm instance
1931 */
1932
1933static struct snd_pcm_ops snd_m3_playback_ops = {
1934 .open = snd_m3_playback_open,
1935 .close = snd_m3_playback_close,
1936 .ioctl = snd_pcm_lib_ioctl,
1937 .hw_params = snd_m3_pcm_hw_params,
1938 .hw_free = snd_m3_pcm_hw_free,
1939 .prepare = snd_m3_pcm_prepare,
1940 .trigger = snd_m3_pcm_trigger,
1941 .pointer = snd_m3_pcm_pointer,
1942};
1943
1944static struct snd_pcm_ops snd_m3_capture_ops = {
1945 .open = snd_m3_capture_open,
1946 .close = snd_m3_capture_close,
1947 .ioctl = snd_pcm_lib_ioctl,
1948 .hw_params = snd_m3_pcm_hw_params,
1949 .hw_free = snd_m3_pcm_hw_free,
1950 .prepare = snd_m3_pcm_prepare,
1951 .trigger = snd_m3_pcm_trigger,
1952 .pointer = snd_m3_pcm_pointer,
1953};
1954
1955static int __devinit
1956snd_m3_pcm(struct snd_m3 * chip, int device)
1957{
1958 struct snd_pcm *pcm;
1959 int err;
1960
1961 err = snd_pcm_new(chip->card, chip->card->driver, device,
1962 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1963 if (err < 0)
1964 return err;
1965
1966 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1967 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1968
1969 pcm->private_data = chip;
1970 pcm->info_flags = 0;
1971 strcpy(pcm->name, chip->card->driver);
1972 chip->pcm = pcm;
1973
1974 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1975 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1976
1977 return 0;
1978}
1979
1980
1981/*
1982 * ac97 interface
1983 */
1984
1985/*
1986 * Wait for the ac97 serial bus to be free.
1987 * return nonzero if the bus is still busy.
1988 */
1989static int snd_m3_ac97_wait(struct snd_m3 *chip)
1990{
1991 int i = 10000;
1992
1993 do {
1994 if (! (snd_m3_inb(chip, 0x30) & 1))
1995 return 0;
1996 cpu_relax();
1997 } while (i-- > 0);
1998
1999 snd_printk(KERN_ERR "ac97 serial bus busy\n");
2000 return 1;
2001}
2002
2003static unsigned short
2004snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
2005{
2006 struct snd_m3 *chip = ac97->private_data;
2007#ifndef CONFIG_SND_MAESTRO3_INPUT
2008 unsigned long flags;
2009#endif
2010 unsigned short data = 0xffff;
2011
2012 if (snd_m3_ac97_wait(chip))
2013 goto fail;
2014#ifndef CONFIG_SND_MAESTRO3_INPUT
2015 spin_lock_irqsave(&chip->ac97_lock, flags);
2016#endif
2017 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
2018 if (snd_m3_ac97_wait(chip))
2019 goto fail_unlock;
2020 data = snd_m3_inw(chip, CODEC_DATA);
2021fail_unlock:
2022#ifndef CONFIG_SND_MAESTRO3_INPUT
2023 spin_unlock_irqrestore(&chip->ac97_lock, flags);
2024#endif
2025fail:
2026 return data;
2027}
2028
2029static void
2030snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
2031{
2032 struct snd_m3 *chip = ac97->private_data;
2033#ifndef CONFIG_SND_MAESTRO3_INPUT
2034 unsigned long flags;
2035#endif
2036
2037 if (snd_m3_ac97_wait(chip))
2038 return;
2039#ifndef CONFIG_SND_MAESTRO3_INPUT
2040 spin_lock_irqsave(&chip->ac97_lock, flags);
2041#endif
2042 snd_m3_outw(chip, val, CODEC_DATA);
2043 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
2044#ifndef CONFIG_SND_MAESTRO3_INPUT
2045 spin_unlock_irqrestore(&chip->ac97_lock, flags);
2046#endif
2047}
2048
2049
2050static void snd_m3_remote_codec_config(int io, int isremote)
2051{
2052 isremote = isremote ? 1 : 0;
2053
2054 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2055 io + RING_BUS_CTRL_B);
2056 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2057 io + SDO_OUT_DEST_CTRL);
2058 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2059 io + SDO_IN_DEST_CTRL);
2060}
2061
2062/*
2063 * hack, returns non zero on err
2064 */
2065static int snd_m3_try_read_vendor(struct snd_m3 *chip)
2066{
2067 u16 ret;
2068
2069 if (snd_m3_ac97_wait(chip))
2070 return 1;
2071
2072 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2073
2074 if (snd_m3_ac97_wait(chip))
2075 return 1;
2076
2077 ret = snd_m3_inw(chip, 0x32);
2078
2079 return (ret == 0) || (ret == 0xffff);
2080}
2081
2082static void snd_m3_ac97_reset(struct snd_m3 *chip)
2083{
2084 u16 dir;
2085 int delay1 = 0, delay2 = 0, i;
2086 int io = chip->iobase;
2087
2088 if (chip->allegro_flag) {
2089 /*
2090 * the onboard codec on the allegro seems
2091 * to want to wait a very long time before
2092 * coming back to life
2093 */
2094 delay1 = 50;
2095 delay2 = 800;
2096 } else {
2097 /* maestro3 */
2098 delay1 = 20;
2099 delay2 = 500;
2100 }
2101
2102 for (i = 0; i < 5; i++) {
2103 dir = inw(io + GPIO_DIRECTION);
2104 if (!chip->irda_workaround)
2105 dir |= 0x10; /* assuming pci bus master? */
2106
2107 snd_m3_remote_codec_config(io, 0);
2108
2109 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2110 udelay(20);
2111
2112 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2113 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2114 outw(0, io + GPIO_DATA);
2115 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2116
2117 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2118
2119 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2120 udelay(5);
2121 /* ok, bring back the ac-link */
2122 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2123 outw(~0, io + GPIO_MASK);
2124
2125 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2126
2127 if (! snd_m3_try_read_vendor(chip))
2128 break;
2129
2130 delay1 += 10;
2131 delay2 += 100;
2132
2133 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2134 delay1, delay2);
2135 }
2136
2137#if 0
2138 /* more gung-ho reset that doesn't
2139 * seem to work anywhere :)
2140 */
2141 tmp = inw(io + RING_BUS_CTRL_A);
2142 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2143 msleep(20);
2144 outw(tmp, io + RING_BUS_CTRL_A);
2145 msleep(50);
2146#endif
2147}
2148
2149static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2150{
2151 struct snd_ac97_bus *pbus;
2152 struct snd_ac97_template ac97;
2153#ifndef CONFIG_SND_MAESTRO3_INPUT
2154 struct snd_ctl_elem_id elem_id;
2155#endif
2156 int err;
2157 static struct snd_ac97_bus_ops ops = {
2158 .write = snd_m3_ac97_write,
2159 .read = snd_m3_ac97_read,
2160 };
2161
2162 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2163 return err;
2164
2165 memset(&ac97, 0, sizeof(ac97));
2166 ac97.private_data = chip;
2167 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2168 return err;
2169
2170 /* seems ac97 PCM needs initialization.. hack hack.. */
2171 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2172 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2173 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2174
2175#ifndef CONFIG_SND_MAESTRO3_INPUT
2176 memset(&elem_id, 0, sizeof(elem_id));
2177 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2178 strcpy(elem_id.name, "Master Playback Switch");
2179 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2180 memset(&elem_id, 0, sizeof(elem_id));
2181 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2182 strcpy(elem_id.name, "Master Playback Volume");
2183 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2184#endif
2185
2186 return 0;
2187}
2188
2189
2190/*
2191 * initialize ASSP
2192 */
2193
2194#define MINISRC_LPF_LEN 10
2195static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2196 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2197 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2198};
2199
2200static void snd_m3_assp_init(struct snd_m3 *chip)
2201{
2202 unsigned int i;
2203 const u16 *data;
2204
2205 /* zero kernel data */
2206 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2207 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2208 KDATA_BASE_ADDR + i, 0);
2209
2210 /* zero mixer data? */
2211 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2212 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2213 KDATA_BASE_ADDR2 + i, 0);
2214
2215 /* init dma pointer */
2216 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2217 KDATA_CURRENT_DMA,
2218 KDATA_DMA_XFER0);
2219
2220 /* write kernel into code memory.. */
2221 data = (const u16 *)chip->assp_kernel_image->data;
2222 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2223 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2224 REV_B_CODE_MEMORY_BEGIN + i,
2225 le16_to_cpu(data[i]));
2226 }
2227
2228 /*
2229 * We only have this one client and we know that 0x400
2230 * is free in our kernel's mem map, so lets just
2231 * drop it there. It seems that the minisrc doesn't
2232 * need vectors, so we won't bother with them..
2233 */
2234 data = (const u16 *)chip->assp_minisrc_image->data;
2235 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2236 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2237 0x400 + i, le16_to_cpu(data[i]));
2238 }
2239
2240 /*
2241 * write the coefficients for the low pass filter?
2242 */
2243 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2244 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2245 0x400 + MINISRC_COEF_LOC + i,
2246 minisrc_lpf[i]);
2247 }
2248
2249 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2250 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2251 0x8000);
2252
2253 /*
2254 * the minisrc is the only thing on
2255 * our task list..
2256 */
2257 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2258 KDATA_TASK0,
2259 0x400);
2260
2261 /*
2262 * init the mixer number..
2263 */
2264
2265 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2266 KDATA_MIXER_TASK_NUMBER,0);
2267
2268 /*
2269 * EXTREME KERNEL MASTER VOLUME
2270 */
2271 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2272 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2273 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2274 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2275
2276 chip->mixer_list.curlen = 0;
2277 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2278 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2279 chip->adc1_list.curlen = 0;
2280 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2281 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2282 chip->dma_list.curlen = 0;
2283 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2284 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2285 chip->msrc_list.curlen = 0;
2286 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2287 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2288}
2289
2290
2291static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2292{
2293 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2294 MINISRC_IN_BUFFER_SIZE / 2 +
2295 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2296 int address, i;
2297
2298 /*
2299 * the revb memory map has 0x1100 through 0x1c00
2300 * free.
2301 */
2302
2303 /*
2304 * align instance address to 256 bytes so that its
2305 * shifted list address is aligned.
2306 * list address = (mem address >> 1) >> 7;
2307 */
2308 data_bytes = ALIGN(data_bytes, 256);
2309 address = 0x1100 + ((data_bytes/2) * index);
2310
2311 if ((address + (data_bytes/2)) >= 0x1c00) {
2312 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2313 data_bytes, index, address);
2314 return -ENOMEM;
2315 }
2316
2317 s->number = index;
2318 s->inst.code = 0x400;
2319 s->inst.data = address;
2320
2321 for (i = data_bytes / 2; i > 0; address++, i--) {
2322 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2323 address, 0);
2324 }
2325
2326 return 0;
2327}
2328
2329
2330/*
2331 * this works for the reference board, have to find
2332 * out about others
2333 *
2334 * this needs more magic for 4 speaker, but..
2335 */
2336static void
2337snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2338{
2339 int io = chip->iobase;
2340 u16 gpo, polarity;
2341
2342 if (! chip->external_amp)
2343 return;
2344
2345 polarity = enable ? 0 : 1;
2346 polarity = polarity << chip->amp_gpio;
2347 gpo = 1 << chip->amp_gpio;
2348
2349 outw(~gpo, io + GPIO_MASK);
2350
2351 outw(inw(io + GPIO_DIRECTION) | gpo,
2352 io + GPIO_DIRECTION);
2353
2354 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2355 io + GPIO_DATA);
2356
2357 outw(0xffff, io + GPIO_MASK);
2358}
2359
2360static void
2361snd_m3_hv_init(struct snd_m3 *chip)
2362{
2363 unsigned long io = chip->iobase;
2364 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2365
2366 if (!chip->is_omnibook)
2367 return;
2368
2369 /*
2370 * Volume buttons on some HP OmniBook laptops
2371 * require some GPIO magic to work correctly.
2372 */
2373 outw(0xffff, io + GPIO_MASK);
2374 outw(0x0000, io + GPIO_DATA);
2375
2376 outw(~val, io + GPIO_MASK);
2377 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2378 outw(val, io + GPIO_MASK);
2379
2380 outw(0xffff, io + GPIO_MASK);
2381}
2382
2383static int
2384snd_m3_chip_init(struct snd_m3 *chip)
2385{
2386 struct pci_dev *pcidev = chip->pci;
2387 unsigned long io = chip->iobase;
2388 u32 n;
2389 u16 w;
2390 u8 t; /* makes as much sense as 'n', no? */
2391
2392 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2393 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2394 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2395 DISABLE_LEGACY);
2396 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2397
2398 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2399 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2400 n |= chip->hv_config;
2401 /* For some reason we must always use reduced debounce. */
2402 n |= REDUCED_DEBOUNCE;
2403 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2404 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2405
2406 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2407 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2408 n &= ~INT_CLK_SELECT;
2409 if (!chip->allegro_flag) {
2410 n &= ~INT_CLK_MULT_ENABLE;
2411 n |= INT_CLK_SRC_NOT_PCI;
2412 }
2413 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2414 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2415
2416 if (chip->allegro_flag) {
2417 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2418 n |= IN_CLK_12MHZ_SELECT;
2419 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2420 }
2421
2422 t = inb(chip->iobase + ASSP_CONTROL_A);
2423 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2424 t |= ASSP_CLK_49MHZ_SELECT;
2425 t |= ASSP_0_WS_ENABLE;
2426 outb(t, chip->iobase + ASSP_CONTROL_A);
2427
2428 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2429 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2430
2431 outb(0x00, io + HARDWARE_VOL_CTRL);
2432 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2433 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2434 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2435 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2436
2437 return 0;
2438}
2439
2440static void
2441snd_m3_enable_ints(struct snd_m3 *chip)
2442{
2443 unsigned long io = chip->iobase;
2444 unsigned short val;
2445
2446 /* TODO: MPU401 not supported yet */
2447 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2448 if (chip->hv_config & HV_CTRL_ENABLE)
2449 val |= HV_INT_ENABLE;
2450 outb(val, chip->iobase + HOST_INT_STATUS);
2451 outw(val, io + HOST_INT_CTRL);
2452 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2453 io + ASSP_CONTROL_C);
2454}
2455
2456
2457/*
2458 */
2459
2460static int snd_m3_free(struct snd_m3 *chip)
2461{
2462 struct m3_dma *s;
2463 int i;
2464
2465#ifdef CONFIG_SND_MAESTRO3_INPUT
2466 if (chip->input_dev)
2467 input_unregister_device(chip->input_dev);
2468#endif
2469
2470 if (chip->substreams) {
2471 spin_lock_irq(&chip->reg_lock);
2472 for (i = 0; i < chip->num_substreams; i++) {
2473 s = &chip->substreams[i];
2474 /* check surviving pcms; this should not happen though.. */
2475 if (s->substream && s->running)
2476 snd_m3_pcm_stop(chip, s, s->substream);
2477 }
2478 spin_unlock_irq(&chip->reg_lock);
2479 kfree(chip->substreams);
2480 }
2481 if (chip->iobase) {
2482 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2483 }
2484
2485#ifdef CONFIG_PM
2486 vfree(chip->suspend_mem);
2487#endif
2488
2489 if (chip->irq >= 0)
2490 free_irq(chip->irq, chip);
2491
2492 if (chip->iobase)
2493 pci_release_regions(chip->pci);
2494
2495 release_firmware(chip->assp_kernel_image);
2496 release_firmware(chip->assp_minisrc_image);
2497
2498 pci_disable_device(chip->pci);
2499 kfree(chip);
2500 return 0;
2501}
2502
2503
2504/*
2505 * APM support
2506 */
2507#ifdef CONFIG_PM
2508static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2509{
2510 struct snd_card *card = pci_get_drvdata(pci);
2511 struct snd_m3 *chip = card->private_data;
2512 int i, dsp_index;
2513
2514 if (chip->suspend_mem == NULL)
2515 return 0;
2516
2517 chip->in_suspend = 1;
2518 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2519 snd_pcm_suspend_all(chip->pcm);
2520 snd_ac97_suspend(chip->ac97);
2521
2522 msleep(10); /* give the assp a chance to idle.. */
2523
2524 snd_m3_assp_halt(chip);
2525
2526 /* save dsp image */
2527 dsp_index = 0;
2528 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2529 chip->suspend_mem[dsp_index++] =
2530 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2531 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2532 chip->suspend_mem[dsp_index++] =
2533 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2534
2535 pci_disable_device(pci);
2536 pci_save_state(pci);
2537 pci_set_power_state(pci, pci_choose_state(pci, state));
2538 return 0;
2539}
2540
2541static int m3_resume(struct pci_dev *pci)
2542{
2543 struct snd_card *card = pci_get_drvdata(pci);
2544 struct snd_m3 *chip = card->private_data;
2545 int i, dsp_index;
2546
2547 if (chip->suspend_mem == NULL)
2548 return 0;
2549
2550 pci_set_power_state(pci, PCI_D0);
2551 pci_restore_state(pci);
2552 if (pci_enable_device(pci) < 0) {
2553 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2554 "disabling device\n");
2555 snd_card_disconnect(card);
2556 return -EIO;
2557 }
2558 pci_set_master(pci);
2559
2560 /* first lets just bring everything back. .*/
2561 snd_m3_outw(chip, 0, 0x54);
2562 snd_m3_outw(chip, 0, 0x56);
2563
2564 snd_m3_chip_init(chip);
2565 snd_m3_assp_halt(chip);
2566 snd_m3_ac97_reset(chip);
2567
2568 /* restore dsp image */
2569 dsp_index = 0;
2570 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2571 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2572 chip->suspend_mem[dsp_index++]);
2573 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2574 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2575 chip->suspend_mem[dsp_index++]);
2576
2577 /* tell the dma engine to restart itself */
2578 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2579 KDATA_DMA_ACTIVE, 0);
2580
2581 /* restore ac97 registers */
2582 snd_ac97_resume(chip->ac97);
2583
2584 snd_m3_assp_continue(chip);
2585 snd_m3_enable_ints(chip);
2586 snd_m3_amp_enable(chip, 1);
2587
2588 snd_m3_hv_init(chip);
2589
2590 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2591 chip->in_suspend = 0;
2592 return 0;
2593}
2594#endif /* CONFIG_PM */
2595
2596#ifdef CONFIG_SND_MAESTRO3_INPUT
2597static int __devinit snd_m3_input_register(struct snd_m3 *chip)
2598{
2599 struct input_dev *input_dev;
2600 int err;
2601
2602 input_dev = input_allocate_device();
2603 if (!input_dev)
2604 return -ENOMEM;
2605
2606 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2607 pci_name(chip->pci));
2608
2609 input_dev->name = chip->card->driver;
2610 input_dev->phys = chip->phys;
2611 input_dev->id.bustype = BUS_PCI;
2612 input_dev->id.vendor = chip->pci->vendor;
2613 input_dev->id.product = chip->pci->device;
2614 input_dev->dev.parent = &chip->pci->dev;
2615
2616 __set_bit(EV_KEY, input_dev->evbit);
2617 __set_bit(KEY_MUTE, input_dev->keybit);
2618 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2619 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2620
2621 err = input_register_device(input_dev);
2622 if (err) {
2623 input_free_device(input_dev);
2624 return err;
2625 }
2626
2627 chip->input_dev = input_dev;
2628 return 0;
2629}
2630#endif /* CONFIG_INPUT */
2631
2632/*
2633 */
2634
2635static int snd_m3_dev_free(struct snd_device *device)
2636{
2637 struct snd_m3 *chip = device->device_data;
2638 return snd_m3_free(chip);
2639}
2640
2641static int __devinit
2642snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2643 int enable_amp,
2644 int amp_gpio,
2645 struct snd_m3 **chip_ret)
2646{
2647 struct snd_m3 *chip;
2648 int i, err;
2649 const struct snd_pci_quirk *quirk;
2650 static struct snd_device_ops ops = {
2651 .dev_free = snd_m3_dev_free,
2652 };
2653
2654 *chip_ret = NULL;
2655
2656 if (pci_enable_device(pci))
2657 return -EIO;
2658
2659 /* check, if we can restrict PCI DMA transfers to 28 bits */
2660 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2661 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
2662 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2663 pci_disable_device(pci);
2664 return -ENXIO;
2665 }
2666
2667 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2668 if (chip == NULL) {
2669 pci_disable_device(pci);
2670 return -ENOMEM;
2671 }
2672
2673 spin_lock_init(&chip->reg_lock);
2674#ifndef CONFIG_SND_MAESTRO3_INPUT
2675 spin_lock_init(&chip->ac97_lock);
2676#endif
2677
2678 switch (pci->device) {
2679 case PCI_DEVICE_ID_ESS_ALLEGRO:
2680 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2681 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2682 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2683 chip->allegro_flag = 1;
2684 break;
2685 }
2686
2687 chip->card = card;
2688 chip->pci = pci;
2689 chip->irq = -1;
2690
2691 chip->external_amp = enable_amp;
2692 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2693 chip->amp_gpio = amp_gpio;
2694 else {
2695 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2696 if (quirk) {
2697#ifndef TARGET_OS2
2698 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2699 "for '%s'\n", quirk->name);
2700#endif
2701 chip->amp_gpio = quirk->value;
2702 } else if (chip->allegro_flag)
2703 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2704 else /* presumably this is for all 'maestro3's.. */
2705 chip->amp_gpio = GPO_EXT_AMP_M3;
2706 }
2707
2708 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2709 if (quirk) {
2710#ifndef TARGET_OS2
2711 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2712 "for '%s'\n", quirk->name);
2713#endif
2714 chip->irda_workaround = 1;
2715 }
2716 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2717 if (quirk)
2718 chip->hv_config = quirk->value;
2719 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2720 chip->is_omnibook = 1;
2721
2722 chip->num_substreams = NR_DSPS;
2723 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2724 GFP_KERNEL);
2725 if (chip->substreams == NULL) {
2726 kfree(chip);
2727 pci_disable_device(pci);
2728 return -ENOMEM;
2729 }
2730
2731 err = request_firmware(&chip->assp_kernel_image,
2732 "ess/maestro3_assp_kernel.fw", &pci->dev);
2733 if (err < 0) {
2734 snd_m3_free(chip);
2735 return err;
2736 }
2737
2738 err = request_firmware(&chip->assp_minisrc_image,
2739 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2740 if (err < 0) {
2741 snd_m3_free(chip);
2742 return err;
2743 }
2744
2745 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2746 snd_m3_free(chip);
2747 return err;
2748 }
2749 chip->iobase = pci_resource_start(pci, 0);
2750
2751 /* just to be sure */
2752 pci_set_master(pci);
2753
2754 snd_m3_chip_init(chip);
2755 snd_m3_assp_halt(chip);
2756
2757 snd_m3_ac97_reset(chip);
2758
2759 snd_m3_amp_enable(chip, 1);
2760
2761 snd_m3_hv_init(chip);
2762
2763#ifndef CONFIG_SND_MAESTRO3_INPUT
2764 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2765#endif
2766
2767 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2768 card->driver, chip)) {
2769 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2770 snd_m3_free(chip);
2771 return -ENOMEM;
2772 }
2773 chip->irq = pci->irq;
2774
2775#ifdef CONFIG_PM
2776 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2777 if (chip->suspend_mem == NULL)
2778 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2779#endif
2780
2781 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2782 snd_m3_free(chip);
2783 return err;
2784 }
2785
2786 if ((err = snd_m3_mixer(chip)) < 0)
2787 return err;
2788
2789 for (i = 0; i < chip->num_substreams; i++) {
2790 struct m3_dma *s = &chip->substreams[i];
2791 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2792 return err;
2793 }
2794
2795 if ((err = snd_m3_pcm(chip, 0)) < 0)
2796 return err;
2797
2798#ifdef CONFIG_SND_MAESTRO3_INPUT
2799 if (chip->hv_config & HV_CTRL_ENABLE) {
2800 err = snd_m3_input_register(chip);
2801 if (err)
2802 snd_printk(KERN_WARNING "Input device registration "
2803 "failed with error %i", err);
2804 }
2805#endif
2806
2807 snd_m3_enable_ints(chip);
2808 snd_m3_assp_continue(chip);
2809
2810 snd_card_set_dev(card, &pci->dev);
2811
2812 *chip_ret = chip;
2813
2814 return 0;
2815}
2816
2817/*
2818 */
2819static int __devinit
2820snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2821{
2822 static int dev;
2823 struct snd_card *card;
2824 struct snd_m3 *chip;
2825 int err;
2826
2827#ifndef TARGET_OS2
2828 /* don't pick up modems */
2829 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2830 return -ENODEV;
2831#endif
2832 if (dev >= SNDRV_CARDS)
2833 return -ENODEV;
2834 if (!enable[dev]) {
2835 dev++;
2836 return -ENOENT;
2837 }
2838
2839 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2840 if (err < 0)
2841 return err;
2842
2843 switch (pci->device) {
2844 case PCI_DEVICE_ID_ESS_ALLEGRO:
2845 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2846 strcpy(card->driver, "Allegro");
2847 break;
2848 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2849 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2850 strcpy(card->driver, "Canyon3D-2");
2851 break;
2852 default:
2853 strcpy(card->driver, "Maestro3");
2854 break;
2855 }
2856
2857 if ((err = snd_m3_create(card, pci,
2858 external_amp[dev],
2859 amp_gpio[dev],
2860 &chip)) < 0) {
2861 snd_card_free(card);
2862 return err;
2863 }
2864 card->private_data = chip;
2865
2866 sprintf(card->shortname, "ESS %s PCI", card->driver);
2867 sprintf(card->longname, "%s at 0x%lx, irq %d",
2868 card->shortname, chip->iobase, chip->irq);
2869
2870 if ((err = snd_card_register(card)) < 0) {
2871 snd_card_free(card);
2872 return err;
2873 }
2874
2875#if 0 /* TODO: not supported yet */
2876 /* TODO enable MIDI IRQ and I/O */
2877 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2878 chip->iobase + MPU401_DATA_PORT,
2879 MPU401_INFO_INTEGRATED,
2880 chip->irq, 0, &chip->rmidi);
2881 if (err < 0)
2882 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2883#endif
2884
2885 pci_set_drvdata(pci, card);
2886 dev++;
2887 return 0;
2888}
2889
2890static void __devexit snd_m3_remove(struct pci_dev *pci)
2891{
2892 snd_card_free(pci_get_drvdata(pci));
2893 pci_set_drvdata(pci, NULL);
2894}
2895
2896static struct pci_driver driver = {
2897 .name = "Maestro3",
2898 .id_table = snd_m3_ids,
2899 .probe = snd_m3_probe,
2900 .remove = __devexit_p(snd_m3_remove),
2901#ifdef CONFIG_PM
2902 .suspend = m3_suspend,
2903 .resume = m3_resume,
2904#endif
2905};
2906
2907static int __init alsa_card_m3_init(void)
2908{
2909 return pci_register_driver(&driver);
2910}
2911
2912static void __exit alsa_card_m3_exit(void)
2913{
2914 pci_unregister_driver(&driver);
2915}
2916
2917module_init(alsa_card_m3_init)
2918module_exit(alsa_card_m3_exit)
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