source: GPL/trunk/alsa-kernel/pci/maestro3.c@ 433

Last change on this file since 433 was 426, checked in by Paul Smedley, 16 years ago

Update alsa-kernel to ALSA 1.0.20 level
File size: 84.4 KB
Line 
1/*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32#define DRIVER_NAME "Maestro3"
33
34#include <asm/io.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/init.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
41#include <linux/vmalloc.h>
42#include <linux/moduleparam.h>
43#include <linux/firmware.h>
44#include <sound/core.h>
45#include <sound/info.h>
46#include <sound/control.h>
47#include <sound/pcm.h>
48#include <sound/mpu401.h>
49#include <sound/ac97_codec.h>
50#include <sound/initval.h>
51#include <asm/byteorder.h>
52
53MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
54MODULE_DESCRIPTION("ESS Maestro3 PCI");
55MODULE_LICENSE("GPL");
56MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57 "{ESS,ES1988},"
58 "{ESS,Allegro PCI},"
59 "{ESS,Allegro-1 PCI},"
60 "{ESS,Canyon3D-2/LE PCI}}");
61MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
62MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
63
64static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
65static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
66static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
67#ifndef TARGET_OS2
68static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
69static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
70#else
71static int external_amp[SNDRV_CARDS] = {REPEAT_SNDRV(1)};
72static int amp_gpio[SNDRV_CARDS] = {REPEAT_SNDRV(-1)};
73#endif
74module_param_array(index, int, NULL, 0444);
75MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
76module_param_array(id, charp, NULL, 0444);
77MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
78module_param_array(enable, bool, NULL, 0444);
79MODULE_PARM_DESC(enable, "Enable this soundcard.");
80module_param_array(external_amp, bool, NULL, 0444);
81MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
82module_param_array(amp_gpio, int, NULL, 0444);
83MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
84
85#define MAX_PLAYBACKS 2
86#define MAX_CAPTURES 1
87#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
88
89
90/*
91 * maestro3 registers
92 */
93
94/* Allegro PCI configuration registers */
95#define PCI_LEGACY_AUDIO_CTRL 0x40
96#define SOUND_BLASTER_ENABLE 0x00000001
97#define FM_SYNTHESIS_ENABLE 0x00000002
98#define GAME_PORT_ENABLE 0x00000004
99#define MPU401_IO_ENABLE 0x00000008
100#define MPU401_IRQ_ENABLE 0x00000010
101#define ALIAS_10BIT_IO 0x00000020
102#define SB_DMA_MASK 0x000000C0
103#define SB_DMA_0 0x00000040
104#define SB_DMA_1 0x00000040
105#define SB_DMA_R 0x00000080
106#define SB_DMA_3 0x000000C0
107#define SB_IRQ_MASK 0x00000700
108#define SB_IRQ_5 0x00000000
109#define SB_IRQ_7 0x00000100
110#define SB_IRQ_9 0x00000200
111#define SB_IRQ_10 0x00000300
112#define MIDI_IRQ_MASK 0x00003800
113#define SERIAL_IRQ_ENABLE 0x00004000
114#define DISABLE_LEGACY 0x00008000
115
116#define PCI_ALLEGRO_CONFIG 0x50
117#define SB_ADDR_240 0x00000004
118#define MPU_ADDR_MASK 0x00000018
119#define MPU_ADDR_330 0x00000000
120#define MPU_ADDR_300 0x00000008
121#define MPU_ADDR_320 0x00000010
122#define MPU_ADDR_340 0x00000018
123#define USE_PCI_TIMING 0x00000040
124#define POSTED_WRITE_ENABLE 0x00000080
125#define DMA_POLICY_MASK 0x00000700
126#define DMA_DDMA 0x00000000
127#define DMA_TDMA 0x00000100
128#define DMA_PCPCI 0x00000200
129#define DMA_WBDMA16 0x00000400
130#define DMA_WBDMA4 0x00000500
131#define DMA_WBDMA2 0x00000600
132#define DMA_WBDMA1 0x00000700
133#define DMA_SAFE_GUARD 0x00000800
134#define HI_PERF_GP_ENABLE 0x00001000
135#define PIC_SNOOP_MODE_0 0x00002000
136#define PIC_SNOOP_MODE_1 0x00004000
137#define SOUNDBLASTER_IRQ_MASK 0x00008000
138#define RING_IN_ENABLE 0x00010000
139#define SPDIF_TEST_MODE 0x00020000
140#define CLK_MULT_MODE_SELECT_2 0x00040000
141#define EEPROM_WRITE_ENABLE 0x00080000
142#define CODEC_DIR_IN 0x00100000
143#define HV_BUTTON_FROM_GD 0x00200000
144#define REDUCED_DEBOUNCE 0x00400000
145#define HV_CTRL_ENABLE 0x00800000
146#define SPDIF_ENABLE 0x01000000
147#define CLK_DIV_SELECT 0x06000000
148#define CLK_DIV_BY_48 0x00000000
149#define CLK_DIV_BY_49 0x02000000
150#define CLK_DIV_BY_50 0x04000000
151#define CLK_DIV_RESERVED 0x06000000
152#define PM_CTRL_ENABLE 0x08000000
153#define CLK_MULT_MODE_SELECT 0x30000000
154#define CLK_MULT_MODE_SHIFT 28
155#define CLK_MULT_MODE_0 0x00000000
156#define CLK_MULT_MODE_1 0x10000000
157#define CLK_MULT_MODE_2 0x20000000
158#define CLK_MULT_MODE_3 0x30000000
159#define INT_CLK_SELECT 0x40000000
160#define INT_CLK_MULT_RESET 0x80000000
161
162/* M3 */
163#define INT_CLK_SRC_NOT_PCI 0x00100000
164#define INT_CLK_MULT_ENABLE 0x80000000
165
166#define PCI_ACPI_CONTROL 0x54
167#define PCI_ACPI_D0 0x00000000
168#define PCI_ACPI_D1 0xB4F70000
169#define PCI_ACPI_D2 0xB4F7B4F7
170
171#define PCI_USER_CONFIG 0x58
172#define EXT_PCI_MASTER_ENABLE 0x00000001
173#define SPDIF_OUT_SELECT 0x00000002
174#define TEST_PIN_DIR_CTRL 0x00000004
175#define AC97_CODEC_TEST 0x00000020
176#define TRI_STATE_BUFFER 0x00000080
177#define IN_CLK_12MHZ_SELECT 0x00000100
178#define MULTI_FUNC_DISABLE 0x00000200
179#define EXT_MASTER_PAIR_SEL 0x00000400
180#define PCI_MASTER_SUPPORT 0x00000800
181#define STOP_CLOCK_ENABLE 0x00001000
182#define EAPD_DRIVE_ENABLE 0x00002000
183#define REQ_TRI_STATE_ENABLE 0x00004000
184#define REQ_LOW_ENABLE 0x00008000
185#define MIDI_1_ENABLE 0x00010000
186#define MIDI_2_ENABLE 0x00020000
187#define SB_AUDIO_SYNC 0x00040000
188#define HV_CTRL_TEST 0x00100000
189#define SOUNDBLASTER_TEST 0x00400000
190
191#define PCI_USER_CONFIG_C 0x5C
192
193#define PCI_DDMA_CTRL 0x60
194#define DDMA_ENABLE 0x00000001
195
196
197/* Allegro registers */
198#define HOST_INT_CTRL 0x18
199#define SB_INT_ENABLE 0x0001
200#define MPU401_INT_ENABLE 0x0002
201#define ASSP_INT_ENABLE 0x0010
202#define RING_INT_ENABLE 0x0020
203#define HV_INT_ENABLE 0x0040
204#define CLKRUN_GEN_ENABLE 0x0100
205#define HV_CTRL_TO_PME 0x0400
206#define SOFTWARE_RESET_ENABLE 0x8000
207
208/*
209 * should be using the above defines, probably.
210 */
211#define REGB_ENABLE_RESET 0x01
212#define REGB_STOP_CLOCK 0x10
213
214#define HOST_INT_STATUS 0x1A
215#define SB_INT_PENDING 0x01
216#define MPU401_INT_PENDING 0x02
217#define ASSP_INT_PENDING 0x10
218#define RING_INT_PENDING 0x20
219#define HV_INT_PENDING 0x40
220
221#define HARDWARE_VOL_CTRL 0x1B
222#define SHADOW_MIX_REG_VOICE 0x1C
223#define HW_VOL_COUNTER_VOICE 0x1D
224#define SHADOW_MIX_REG_MASTER 0x1E
225#define HW_VOL_COUNTER_MASTER 0x1F
226
227#define CODEC_COMMAND 0x30
228#define CODEC_READ_B 0x80
229
230#define CODEC_STATUS 0x30
231#define CODEC_BUSY_B 0x01
232
233#define CODEC_DATA 0x32
234
235#define RING_BUS_CTRL_A 0x36
236#define RAC_PME_ENABLE 0x0100
237#define RAC_SDFS_ENABLE 0x0200
238#define LAC_PME_ENABLE 0x0400
239#define LAC_SDFS_ENABLE 0x0800
240#define SERIAL_AC_LINK_ENABLE 0x1000
241#define IO_SRAM_ENABLE 0x2000
242#define IIS_INPUT_ENABLE 0x8000
243
244#define RING_BUS_CTRL_B 0x38
245#define SECOND_CODEC_ID_MASK 0x0003
246#define SPDIF_FUNC_ENABLE 0x0010
247#define SECOND_AC_ENABLE 0x0020
248#define SB_MODULE_INTF_ENABLE 0x0040
249#define SSPE_ENABLE 0x0040
250#define M3I_DOCK_ENABLE 0x0080
251
252#define SDO_OUT_DEST_CTRL 0x3A
253#define COMMAND_ADDR_OUT 0x0003
254#define PCM_LR_OUT_LOCAL 0x0000
255#define PCM_LR_OUT_REMOTE 0x0004
256#define PCM_LR_OUT_MUTE 0x0008
257#define PCM_LR_OUT_BOTH 0x000C
258#define LINE1_DAC_OUT_LOCAL 0x0000
259#define LINE1_DAC_OUT_REMOTE 0x0010
260#define LINE1_DAC_OUT_MUTE 0x0020
261#define LINE1_DAC_OUT_BOTH 0x0030
262#define PCM_CLS_OUT_LOCAL 0x0000
263#define PCM_CLS_OUT_REMOTE 0x0040
264#define PCM_CLS_OUT_MUTE 0x0080
265#define PCM_CLS_OUT_BOTH 0x00C0
266#define PCM_RLF_OUT_LOCAL 0x0000
267#define PCM_RLF_OUT_REMOTE 0x0100
268#define PCM_RLF_OUT_MUTE 0x0200
269#define PCM_RLF_OUT_BOTH 0x0300
270#define LINE2_DAC_OUT_LOCAL 0x0000
271#define LINE2_DAC_OUT_REMOTE 0x0400
272#define LINE2_DAC_OUT_MUTE 0x0800
273#define LINE2_DAC_OUT_BOTH 0x0C00
274#define HANDSET_OUT_LOCAL 0x0000
275#define HANDSET_OUT_REMOTE 0x1000
276#define HANDSET_OUT_MUTE 0x2000
277#define HANDSET_OUT_BOTH 0x3000
278#define IO_CTRL_OUT_LOCAL 0x0000
279#define IO_CTRL_OUT_REMOTE 0x4000
280#define IO_CTRL_OUT_MUTE 0x8000
281#define IO_CTRL_OUT_BOTH 0xC000
282
283#define SDO_IN_DEST_CTRL 0x3C
284#define STATUS_ADDR_IN 0x0003
285#define PCM_LR_IN_LOCAL 0x0000
286#define PCM_LR_IN_REMOTE 0x0004
287#define PCM_LR_RESERVED 0x0008
288#define PCM_LR_IN_BOTH 0x000C
289#define LINE1_ADC_IN_LOCAL 0x0000
290#define LINE1_ADC_IN_REMOTE 0x0010
291#define LINE1_ADC_IN_MUTE 0x0020
292#define MIC_ADC_IN_LOCAL 0x0000
293#define MIC_ADC_IN_REMOTE 0x0040
294#define MIC_ADC_IN_MUTE 0x0080
295#define LINE2_DAC_IN_LOCAL 0x0000
296#define LINE2_DAC_IN_REMOTE 0x0400
297#define LINE2_DAC_IN_MUTE 0x0800
298#define HANDSET_IN_LOCAL 0x0000
299#define HANDSET_IN_REMOTE 0x1000
300#define HANDSET_IN_MUTE 0x2000
301#define IO_STATUS_IN_LOCAL 0x0000
302#define IO_STATUS_IN_REMOTE 0x4000
303
304#define SPDIF_IN_CTRL 0x3E
305#define SPDIF_IN_ENABLE 0x0001
306
307#define GPIO_DATA 0x60
308#define GPIO_DATA_MASK 0x0FFF
309#define GPIO_HV_STATUS 0x3000
310#define GPIO_PME_STATUS 0x4000
311
312#define GPIO_MASK 0x64
313#define GPIO_DIRECTION 0x68
314#define GPO_PRIMARY_AC97 0x0001
315#define GPI_LINEOUT_SENSE 0x0004
316#define GPO_SECONDARY_AC97 0x0008
317#define GPI_VOL_DOWN 0x0010
318#define GPI_VOL_UP 0x0020
319#define GPI_IIS_CLK 0x0040
320#define GPI_IIS_LRCLK 0x0080
321#define GPI_IIS_DATA 0x0100
322#define GPI_DOCKING_STATUS 0x0100
323#define GPI_HEADPHONE_SENSE 0x0200
324#define GPO_EXT_AMP_SHUTDOWN 0x1000
325
326#define GPO_EXT_AMP_M3 1 /* default m3 amp */
327#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
328
329/* M3 */
330#define GPO_M3_EXT_AMP_SHUTDN 0x0002
331
332#define ASSP_INDEX_PORT 0x80
333#define ASSP_MEMORY_PORT 0x82
334#define ASSP_DATA_PORT 0x84
335
336#define MPU401_DATA_PORT 0x98
337#define MPU401_STATUS_PORT 0x99
338
339#define CLK_MULT_DATA_PORT 0x9C
340
341#define ASSP_CONTROL_A 0xA2
342#define ASSP_0_WS_ENABLE 0x01
343#define ASSP_CTRL_A_RESERVED1 0x02
344#define ASSP_CTRL_A_RESERVED2 0x04
345#define ASSP_CLK_49MHZ_SELECT 0x08
346#define FAST_PLU_ENABLE 0x10
347#define ASSP_CTRL_A_RESERVED3 0x20
348#define DSP_CLK_36MHZ_SELECT 0x40
349
350#define ASSP_CONTROL_B 0xA4
351#define RESET_ASSP 0x00
352#define RUN_ASSP 0x01
353#define ENABLE_ASSP_CLOCK 0x00
354#define STOP_ASSP_CLOCK 0x10
355#define RESET_TOGGLE 0x40
356
357#define ASSP_CONTROL_C 0xA6
358#define ASSP_HOST_INT_ENABLE 0x01
359#define FM_ADDR_REMAP_DISABLE 0x02
360#define HOST_WRITE_PORT_ENABLE 0x08
361
362#define ASSP_HOST_INT_STATUS 0xAC
363#define DSP2HOST_REQ_PIORECORD 0x01
364#define DSP2HOST_REQ_I2SRATE 0x02
365#define DSP2HOST_REQ_TIMER 0x04
366
367/* AC97 registers */
368/* XXX fix this crap up */
369/*#define AC97_RESET 0x00*/
370
371#define AC97_VOL_MUTE_B 0x8000
372#define AC97_VOL_M 0x1F
373#define AC97_LEFT_VOL_S 8
374
375#define AC97_MASTER_VOL 0x02
376#define AC97_LINE_LEVEL_VOL 0x04
377#define AC97_MASTER_MONO_VOL 0x06
378#define AC97_PC_BEEP_VOL 0x0A
379#define AC97_PC_BEEP_VOL_M 0x0F
380#define AC97_SROUND_MASTER_VOL 0x38
381#define AC97_PC_BEEP_VOL_S 1
382
383/*#define AC97_PHONE_VOL 0x0C
384#define AC97_MIC_VOL 0x0E*/
385#define AC97_MIC_20DB_ENABLE 0x40
386
387/*#define AC97_LINEIN_VOL 0x10
388#define AC97_CD_VOL 0x12
389#define AC97_VIDEO_VOL 0x14
390#define AC97_AUX_VOL 0x16*/
391#define AC97_PCM_OUT_VOL 0x18
392/*#define AC97_RECORD_SELECT 0x1A*/
393#define AC97_RECORD_MIC 0x00
394#define AC97_RECORD_CD 0x01
395#define AC97_RECORD_VIDEO 0x02
396#define AC97_RECORD_AUX 0x03
397#define AC97_RECORD_MONO_MUX 0x02
398#define AC97_RECORD_DIGITAL 0x03
399#define AC97_RECORD_LINE 0x04
400#define AC97_RECORD_STEREO 0x05
401#define AC97_RECORD_MONO 0x06
402#define AC97_RECORD_PHONE 0x07
403
404/*#define AC97_RECORD_GAIN 0x1C*/
405#define AC97_RECORD_VOL_M 0x0F
406
407/*#define AC97_GENERAL_PURPOSE 0x20*/
408#define AC97_POWER_DOWN_CTRL 0x26
409#define AC97_ADC_READY 0x0001
410#define AC97_DAC_READY 0x0002
411#define AC97_ANALOG_READY 0x0004
412#define AC97_VREF_ON 0x0008
413#define AC97_PR0 0x0100
414#define AC97_PR1 0x0200
415#define AC97_PR2 0x0400
416#define AC97_PR3 0x0800
417#define AC97_PR4 0x1000
418
419#define AC97_RESERVED1 0x28
420
421#define AC97_VENDOR_TEST 0x5A
422
423#define AC97_CLOCK_DELAY 0x5C
424#define AC97_LINEOUT_MUX_SEL 0x0001
425#define AC97_MONO_MUX_SEL 0x0002
426#define AC97_CLOCK_DELAY_SEL 0x1F
427#define AC97_DAC_CDS_SHIFT 6
428#define AC97_ADC_CDS_SHIFT 11
429
430#define AC97_MULTI_CHANNEL_SEL 0x74
431
432/*#define AC97_VENDOR_ID1 0x7C
433#define AC97_VENDOR_ID2 0x7E*/
434
435/*
436 * ASSP control regs
437 */
438#define DSP_PORT_TIMER_COUNT 0x06
439
440#define DSP_PORT_MEMORY_INDEX 0x80
441
442#define DSP_PORT_MEMORY_TYPE 0x82
443#define MEMTYPE_INTERNAL_CODE 0x0002
444#define MEMTYPE_INTERNAL_DATA 0x0003
445#define MEMTYPE_MASK 0x0003
446
447#define DSP_PORT_MEMORY_DATA 0x84
448
449#define DSP_PORT_CONTROL_REG_A 0xA2
450#define DSP_PORT_CONTROL_REG_B 0xA4
451#define DSP_PORT_CONTROL_REG_C 0xA6
452
453#define REV_A_CODE_MEMORY_BEGIN 0x0000
454#define REV_A_CODE_MEMORY_END 0x0FFF
455#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
456#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
457
458#define REV_B_CODE_MEMORY_BEGIN 0x0000
459#define REV_B_CODE_MEMORY_END 0x0BFF
460#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
461#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
462
463#define REV_A_DATA_MEMORY_BEGIN 0x1000
464#define REV_A_DATA_MEMORY_END 0x2FFF
465#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
466#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
467
468#define REV_B_DATA_MEMORY_BEGIN 0x1000
469#define REV_B_DATA_MEMORY_END 0x2BFF
470#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
471#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
472
473
474#define NUM_UNITS_KERNEL_CODE 16
475#define NUM_UNITS_KERNEL_DATA 2
476
477#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
478#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
479
480/*
481 * Kernel data layout
482 */
483
484#define DP_SHIFT_COUNT 7
485
486#define KDATA_BASE_ADDR 0x1000
487#define KDATA_BASE_ADDR2 0x1080
488
489#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
490#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
491#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
492#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
493#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
494#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
495#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
496#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
497#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
498
499#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
500#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
501
502#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
503#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
504#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
505#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
506#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
507#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
508#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
509#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
510#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
511#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
512
513#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
514#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
515
516#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
517#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
518
519#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
520#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
521
522#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
523#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
524#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
525
526#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
527#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
528#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
529#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
530#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
531
532#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
533#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
534#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
535
536#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
537#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
538#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
539
540#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
541#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
542#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
543#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
544#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
545#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
546#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
547#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
548#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
549#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
550
551#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
552#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
553#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
554
555#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
556#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
557
558#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
559#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
560#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
561
562#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
563#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
564#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
565#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
566#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
567#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
568
569#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
570#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
571#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
572#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
573#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
574#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
575
576#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
577#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
578#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
579#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
580#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
581#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
582
583#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
584#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
585#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
586#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
587
588#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
589#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
590
591#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
592#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
593
594#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
595#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
596#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
597#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
598#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
599
600#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
601#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
602
603#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
604#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
605#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
606
607#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
608#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
609
610#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
611
612#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
613#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
614#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
615#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
616#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
617#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
618#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
619#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
620#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
621#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
622#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
623#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
624
625#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
626#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
627#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
628#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
629
630#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
631#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
632
633#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
634#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
635#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
636#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
637
638#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
639#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
640#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
641#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
642#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
643
644/*
645 * second 'segment' (?) reserved for mixer
646 * buffers..
647 */
648
649#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
650#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
651#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
652#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
653#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
654#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
655#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
656#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
657#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
658#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
659#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
660#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
661#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
662#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
663#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
664#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
665
666#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
667#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
668#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
669#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
670#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
671#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
672#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
673#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
674#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
675#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
676#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
677
678#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
679#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
680#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
681#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
682#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
683#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
684
685#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
686#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
687#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
688#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
689
690/*
691 * client data area offsets
692 */
693#define CDATA_INSTANCE_READY 0x00
694
695#define CDATA_HOST_SRC_ADDRL 0x01
696#define CDATA_HOST_SRC_ADDRH 0x02
697#define CDATA_HOST_SRC_END_PLUS_1L 0x03
698#define CDATA_HOST_SRC_END_PLUS_1H 0x04
699#define CDATA_HOST_SRC_CURRENTL 0x05
700#define CDATA_HOST_SRC_CURRENTH 0x06
701
702#define CDATA_IN_BUF_CONNECT 0x07
703#define CDATA_OUT_BUF_CONNECT 0x08
704
705#define CDATA_IN_BUF_BEGIN 0x09
706#define CDATA_IN_BUF_END_PLUS_1 0x0A
707#define CDATA_IN_BUF_HEAD 0x0B
708#define CDATA_IN_BUF_TAIL 0x0C
709#define CDATA_OUT_BUF_BEGIN 0x0D
710#define CDATA_OUT_BUF_END_PLUS_1 0x0E
711#define CDATA_OUT_BUF_HEAD 0x0F
712#define CDATA_OUT_BUF_TAIL 0x10
713
714#define CDATA_DMA_CONTROL 0x11
715#define CDATA_RESERVED 0x12
716
717#define CDATA_FREQUENCY 0x13
718#define CDATA_LEFT_VOLUME 0x14
719#define CDATA_RIGHT_VOLUME 0x15
720#define CDATA_LEFT_SUR_VOL 0x16
721#define CDATA_RIGHT_SUR_VOL 0x17
722
723#define CDATA_HEADER_LEN 0x18
724
725#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
726#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
727#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
728#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
729#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
730#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
731#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
732#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
733
734#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
735#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
736#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
737#define MINISRC_BIQUAD_STAGE 2
738#define MINISRC_COEF_LOC 0x175
739
740#define DMACONTROL_BLOCK_MASK 0x000F
741#define DMAC_BLOCK0_SELECTOR 0x0000
742#define DMAC_BLOCK1_SELECTOR 0x0001
743#define DMAC_BLOCK2_SELECTOR 0x0002
744#define DMAC_BLOCK3_SELECTOR 0x0003
745#define DMAC_BLOCK4_SELECTOR 0x0004
746#define DMAC_BLOCK5_SELECTOR 0x0005
747#define DMAC_BLOCK6_SELECTOR 0x0006
748#define DMAC_BLOCK7_SELECTOR 0x0007
749#define DMAC_BLOCK8_SELECTOR 0x0008
750#define DMAC_BLOCK9_SELECTOR 0x0009
751#define DMAC_BLOCKA_SELECTOR 0x000A
752#define DMAC_BLOCKB_SELECTOR 0x000B
753#define DMAC_BLOCKC_SELECTOR 0x000C
754#define DMAC_BLOCKD_SELECTOR 0x000D
755#define DMAC_BLOCKE_SELECTOR 0x000E
756#define DMAC_BLOCKF_SELECTOR 0x000F
757#define DMACONTROL_PAGE_MASK 0x00F0
758#define DMAC_PAGE0_SELECTOR 0x0030
759#define DMAC_PAGE1_SELECTOR 0x0020
760#define DMAC_PAGE2_SELECTOR 0x0010
761#define DMAC_PAGE3_SELECTOR 0x0000
762#define DMACONTROL_AUTOREPEAT 0x1000
763#define DMACONTROL_STOPPED 0x2000
764#define DMACONTROL_DIRECTION 0x0100
765
766/*
767 * an arbitrary volume we set the internal
768 * volume settings to so that the ac97 volume
769 * range is a little less insane. 0x7fff is
770 * max.
771 */
772#define ARB_VOLUME ( 0x6800 )
773
774/*
775 */
776
777struct m3_list {
778 int curlen;
779 int mem_addr;
780 int max;
781};
782
783struct m3_dma {
784
785 int number;
786 struct snd_pcm_substream *substream;
787
788 struct assp_instance {
789 unsigned short code, data;
790 } inst;
791
792 int running;
793 int opened;
794
795 unsigned long buffer_addr;
796 int dma_size;
797 int period_size;
798 unsigned int hwptr;
799 int count;
800
801 int index[3];
802 struct m3_list *index_list[3];
803
804 int in_lists;
805
806 struct list_head list;
807
808};
809
810struct snd_m3 {
811
812 struct snd_card *card;
813
814 unsigned long iobase;
815
816 int irq;
817 unsigned int allegro_flag : 1;
818
819 struct snd_ac97 *ac97;
820
821 struct snd_pcm *pcm;
822
823 struct pci_dev *pci;
824
825 int dacs_active;
826 int timer_users;
827
828 struct m3_list msrc_list;
829 struct m3_list mixer_list;
830 struct m3_list adc1_list;
831 struct m3_list dma_list;
832
833 /* for storing reset state..*/
834 u8 reset_state;
835
836 int external_amp;
837 int amp_gpio; /* gpio pin # for external amp, -1 = default */
838 unsigned int hv_config; /* hardware-volume config bits */
839 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
840 (e.g. for IrDA on Dell Inspirons) */
841 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
842
843 /* midi */
844 struct snd_rawmidi *rmidi;
845
846 /* pcm streams */
847 int num_substreams;
848 struct m3_dma *substreams;
849
850 spinlock_t reg_lock;
851 spinlock_t ac97_lock;
852
853 struct snd_kcontrol *master_switch;
854 struct snd_kcontrol *master_volume;
855 struct tasklet_struct hwvol_tq;
856
857#ifdef CONFIG_PM
858 u16 *suspend_mem;
859#endif
860
861 const struct firmware *assp_kernel_image;
862 const struct firmware *assp_minisrc_image;
863};
864
865/*
866 * pci ids
867 */
868static struct pci_device_id snd_m3_ids[] = {
869 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
870 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
871 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
872 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
873 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
874 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
875 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
876 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
877 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
878 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
880 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
882 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
883 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
884 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
885 {0,},
886};
887
888MODULE_DEVICE_TABLE(pci, snd_m3_ids);
889
890static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
891 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
892 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
893 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
894 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
895 {0} /* END */
896};
897
898static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
899 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
900 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
901 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
902 {0} /* END */
903};
904
905/* hardware volume quirks */
906static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
907 /* Allegro chips */
908 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
932 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
933 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
934 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
936 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
954 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
955 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
956 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
957 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
958 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
959 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
960 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
961 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
962 /* Maestro3 chips */
963 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
975 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
976 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
977 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
978 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
979 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
980 {0} /* END */
981};
982
983/* HP Omnibook quirks */
984static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
985 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
986 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
987 {0} /* END */
988};
989
990/*
991 * lowlevel functions
992 */
993
994static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
995{
996 outw(value, chip->iobase + reg);
997}
998
999static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1000{
1001 return inw(chip->iobase + reg);
1002}
1003
1004static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1005{
1006 outb(value, chip->iobase + reg);
1007}
1008
1009static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1010{
1011 return inb(chip->iobase + reg);
1012}
1013
1014/*
1015 * access 16bit words to the code or data regions of the dsp's memory.
1016 * index addresses 16bit words.
1017 */
1018static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1019{
1020 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1021 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1022 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1023}
1024
1025static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1026{
1027 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1028 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1029 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1030}
1031
1032static void snd_m3_assp_halt(struct snd_m3 *chip)
1033{
1034 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1035 msleep(10);
1036 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1037}
1038
1039static void snd_m3_assp_continue(struct snd_m3 *chip)
1040{
1041 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1042}
1043
1044
1045/*
1046 * This makes me sad. the maestro3 has lists
1047 * internally that must be packed.. 0 terminates,
1048 * apparently, or maybe all unused entries have
1049 * to be 0, the lists have static lengths set
1050 * by the binary code images.
1051 */
1052
1053static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1054{
1055 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1056 list->mem_addr + list->curlen,
1057 val);
1058 return list->curlen++;
1059}
1060
1061static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1062{
1063 u16 val;
1064 int lastindex = list->curlen - 1;
1065
1066 if (index != lastindex) {
1067 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1068 list->mem_addr + lastindex);
1069 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1070 list->mem_addr + index,
1071 val);
1072 }
1073
1074 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1075 list->mem_addr + lastindex,
1076 0);
1077
1078 list->curlen--;
1079}
1080
1081static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1082{
1083 chip->timer_users++;
1084 if (chip->timer_users != 1)
1085 return;
1086
1087 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088 KDATA_TIMER_COUNT_RELOAD,
1089 240);
1090
1091 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1092 KDATA_TIMER_COUNT_CURRENT,
1093 240);
1094
1095 snd_m3_outw(chip,
1096 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1097 HOST_INT_CTRL);
1098}
1099
1100static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1101{
1102 chip->timer_users--;
1103 if (chip->timer_users > 0)
1104 return;
1105
1106 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1107 KDATA_TIMER_COUNT_RELOAD,
1108 0);
1109
1110 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1111 KDATA_TIMER_COUNT_CURRENT,
1112 0);
1113
1114 snd_m3_outw(chip,
1115 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1116 HOST_INT_CTRL);
1117}
1118
1119/*
1120 * start/stop
1121 */
1122
1123/* spinlock held! */
1124static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1125 struct snd_pcm_substream *subs)
1126{
1127 if (! s || ! subs)
1128 return -EINVAL;
1129
1130 snd_m3_inc_timer_users(chip);
1131 switch (subs->stream) {
1132 case SNDRV_PCM_STREAM_PLAYBACK:
1133 chip->dacs_active++;
1134 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135 s->inst.data + CDATA_INSTANCE_READY, 1);
1136 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1137 KDATA_MIXER_TASK_NUMBER,
1138 chip->dacs_active);
1139 break;
1140 case SNDRV_PCM_STREAM_CAPTURE:
1141 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142 KDATA_ADC1_REQUEST, 1);
1143 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1144 s->inst.data + CDATA_INSTANCE_READY, 1);
1145 break;
1146 }
1147 return 0;
1148}
1149
1150/* spinlock held! */
1151static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1152 struct snd_pcm_substream *subs)
1153{
1154 if (! s || ! subs)
1155 return -EINVAL;
1156
1157 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1158 s->inst.data + CDATA_INSTANCE_READY, 0);
1159 snd_m3_dec_timer_users(chip);
1160 switch (subs->stream) {
1161 case SNDRV_PCM_STREAM_PLAYBACK:
1162 chip->dacs_active--;
1163 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1164 KDATA_MIXER_TASK_NUMBER,
1165 chip->dacs_active);
1166 break;
1167 case SNDRV_PCM_STREAM_CAPTURE:
1168 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1169 KDATA_ADC1_REQUEST, 0);
1170 break;
1171 }
1172 return 0;
1173}
1174
1175static int
1176snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1177{
1178 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1179 struct m3_dma *s = subs->runtime->private_data;
1180 int err = -EINVAL;
1181
1182 if (snd_BUG_ON(!s))
1183 return -ENXIO;
1184
1185 spin_lock(&chip->reg_lock);
1186 switch (cmd) {
1187 case SNDRV_PCM_TRIGGER_START:
1188 case SNDRV_PCM_TRIGGER_RESUME:
1189 if (s->running)
1190 err = -EBUSY;
1191 else {
1192 s->running = 1;
1193 err = snd_m3_pcm_start(chip, s, subs);
1194 }
1195 break;
1196 case SNDRV_PCM_TRIGGER_STOP:
1197 case SNDRV_PCM_TRIGGER_SUSPEND:
1198 if (! s->running)
1199 err = 0; /* should return error? */
1200 else {
1201 s->running = 0;
1202 err = snd_m3_pcm_stop(chip, s, subs);
1203 }
1204 break;
1205 }
1206 spin_unlock(&chip->reg_lock);
1207 return err;
1208}
1209
1210/*
1211 * setup
1212 */
1213static void
1214snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1215{
1216 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1217 struct snd_pcm_runtime *runtime = subs->runtime;
1218
1219 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1220 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1221 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1222 } else {
1223 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1224 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1225 }
1226 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1227 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1228
1229 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1230 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1231 s->hwptr = 0;
1232 s->count = 0;
1233
1234#define LO(x) ((x) & 0xffff)
1235#define HI(x) LO((x) >> 16)
1236
1237 /* host dma buffer pointers */
1238 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1239 s->inst.data + CDATA_HOST_SRC_ADDRL,
1240 LO(s->buffer_addr));
1241
1242 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1243 s->inst.data + CDATA_HOST_SRC_ADDRH,
1244 HI(s->buffer_addr));
1245
1246 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1247 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1248 LO(s->buffer_addr + s->dma_size));
1249
1250 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1251 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1252 HI(s->buffer_addr + s->dma_size));
1253
1254 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1255 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1256 LO(s->buffer_addr));
1257
1258 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1259 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1260 HI(s->buffer_addr));
1261#undef LO
1262#undef HI
1263
1264 /* dsp buffers */
1265
1266 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1267 s->inst.data + CDATA_IN_BUF_BEGIN,
1268 dsp_in_buffer);
1269
1270 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1271 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1272 dsp_in_buffer + (dsp_in_size / 2));
1273
1274 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1275 s->inst.data + CDATA_IN_BUF_HEAD,
1276 dsp_in_buffer);
1277
1278 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1279 s->inst.data + CDATA_IN_BUF_TAIL,
1280 dsp_in_buffer);
1281
1282 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1283 s->inst.data + CDATA_OUT_BUF_BEGIN,
1284 dsp_out_buffer);
1285
1286 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1287 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1288 dsp_out_buffer + (dsp_out_size / 2));
1289
1290 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1291 s->inst.data + CDATA_OUT_BUF_HEAD,
1292 dsp_out_buffer);
1293
1294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1295 s->inst.data + CDATA_OUT_BUF_TAIL,
1296 dsp_out_buffer);
1297}
1298
1299static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1300 struct snd_pcm_runtime *runtime)
1301{
1302 u32 freq;
1303
1304 /*
1305 * put us in the lists if we're not already there
1306 */
1307 if (! s->in_lists) {
1308 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1309 s->inst.data >> DP_SHIFT_COUNT);
1310 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1311 s->inst.data >> DP_SHIFT_COUNT);
1312 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1313 s->inst.data >> DP_SHIFT_COUNT);
1314 s->in_lists = 1;
1315 }
1316
1317 /* write to 'mono' word */
1318 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1319 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1320 runtime->channels == 2 ? 0 : 1);
1321 /* write to '8bit' word */
1322 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1323 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1324 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1325
1326 /* set up dac/adc rate */
1327 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1328 if (freq)
1329 freq--;
1330
1331 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1332 s->inst.data + CDATA_FREQUENCY,
1333 freq);
1334}
1335
1336
1337static const struct play_vals {
1338 u16 addr, val;
1339} pv[] = {
1340 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1341 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1342 {SRC3_DIRECTION_OFFSET, 0} ,
1343 /* +1, +2 are stereo/16 bit */
1344 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1345 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1346 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1347 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1348 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1349 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1350 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1351 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1352 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1353 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1354 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1355 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1356 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1357 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1358 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1359 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1360 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1361};
1362
1363
1364/* the mode passed should be already shifted and masked */
1365static void
1366snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1367 struct snd_pcm_substream *subs)
1368{
1369 unsigned int i;
1370
1371 /*
1372 * some per client initializers
1373 */
1374
1375 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1376 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1377 s->inst.data + 40 + 8);
1378
1379 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1380 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1381 s->inst.code + MINISRC_COEF_LOC);
1382
1383 /* enable or disable low pass filter? */
1384 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1385 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1386 subs->runtime->rate > 45000 ? 0xff : 0);
1387
1388 /* tell it which way dma is going? */
1389 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1390 s->inst.data + CDATA_DMA_CONTROL,
1391 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1392
1393 /*
1394 * set an armload of static initializers
1395 */
1396 for (i = 0; i < ARRAY_SIZE(pv); i++)
1397 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1398 s->inst.data + pv[i].addr, pv[i].val);
1399}
1400
1401/*
1402 * Native record driver
1403 */
1404static const struct rec_vals {
1405 u16 addr, val;
1406} rv[] = {
1407 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1408 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1409 {SRC3_DIRECTION_OFFSET, 1} ,
1410 /* +1, +2 are stereo/16 bit */
1411 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1412 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1413 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1414 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1415 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1416 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1417 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1418 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1419 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1420 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1421 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1422 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1423 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1424 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1425 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1426 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1427 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1428 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1429 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1430};
1431
1432static void
1433snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1434{
1435 unsigned int i;
1436
1437 /*
1438 * some per client initializers
1439 */
1440
1441 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1442 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1443 s->inst.data + 40 + 8);
1444
1445 /* tell it which way dma is going? */
1446 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1447 s->inst.data + CDATA_DMA_CONTROL,
1448 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1449 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1450
1451 /*
1452 * set an armload of static initializers
1453 */
1454 for (i = 0; i < ARRAY_SIZE(rv); i++)
1455 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1456 s->inst.data + rv[i].addr, rv[i].val);
1457}
1458
1459static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1460 struct snd_pcm_hw_params *hw_params)
1461{
1462 struct m3_dma *s = substream->runtime->private_data;
1463 int err;
1464
1465 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1466 return err;
1467 /* set buffer address */
1468 s->buffer_addr = substream->runtime->dma_addr;
1469 if (s->buffer_addr & 0x3) {
1470 snd_printk(KERN_ERR "oh my, not aligned\n");
1471 s->buffer_addr = s->buffer_addr & ~0x3;
1472 }
1473 return 0;
1474}
1475
1476static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1477{
1478 struct m3_dma *s;
1479
1480 if (substream->runtime->private_data == NULL)
1481 return 0;
1482 s = substream->runtime->private_data;
1483 snd_pcm_lib_free_pages(substream);
1484 s->buffer_addr = 0;
1485 return 0;
1486}
1487
1488static int
1489snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1490{
1491 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1492 struct snd_pcm_runtime *runtime = subs->runtime;
1493 struct m3_dma *s = runtime->private_data;
1494
1495 if (snd_BUG_ON(!s))
1496 return -ENXIO;
1497
1498 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1499 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1500 return -EINVAL;
1501 if (runtime->rate > 48000 ||
1502 runtime->rate < 8000)
1503 return -EINVAL;
1504
1505 spin_lock_irq(&chip->reg_lock);
1506
1507 snd_m3_pcm_setup1(chip, s, subs);
1508
1509 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1510 snd_m3_playback_setup(chip, s, subs);
1511 else
1512 snd_m3_capture_setup(chip, s, subs);
1513
1514 snd_m3_pcm_setup2(chip, s, runtime);
1515
1516 spin_unlock_irq(&chip->reg_lock);
1517
1518 return 0;
1519}
1520
1521/*
1522 * get current pointer
1523 */
1524static unsigned int
1525snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1526{
1527 u16 hi = 0, lo = 0;
1528 int retry = 10;
1529 u32 addr;
1530
1531 /*
1532 * try and get a valid answer
1533 */
1534 while (retry--) {
1535 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1536 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1537
1538 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1539 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1540
1541 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1542 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1543 break;
1544 }
1545 addr = lo | ((u32)hi<<16);
1546 return (unsigned int)(addr - s->buffer_addr);
1547}
1548
1549static snd_pcm_uframes_t
1550snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1551{
1552 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1553 unsigned int ptr;
1554 struct m3_dma *s = subs->runtime->private_data;
1555
1556 if (snd_BUG_ON(!s))
1557 return 0;
1558
1559 spin_lock(&chip->reg_lock);
1560 ptr = snd_m3_get_pointer(chip, s, subs);
1561 spin_unlock(&chip->reg_lock);
1562 return bytes_to_frames(subs->runtime, ptr);
1563}
1564
1565
1566/* update pointer */
1567/* spinlock held! */
1568static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1569{
1570 struct snd_pcm_substream *subs = s->substream;
1571 unsigned int hwptr;
1572 int diff;
1573
1574 if (! s->running)
1575 return;
1576
1577 hwptr = snd_m3_get_pointer(chip, s, subs);
1578
1579 /* try to avoid expensive modulo divisions */
1580 if (hwptr >= s->dma_size)
1581 hwptr %= s->dma_size;
1582
1583 diff = s->dma_size + hwptr - s->hwptr;
1584 if (diff >= s->dma_size)
1585 diff %= s->dma_size;
1586
1587 s->hwptr = hwptr;
1588 s->count += diff;
1589
1590 if (s->count >= (signed)s->period_size) {
1591
1592 if (s->count < 2 * (signed)s->period_size)
1593 s->count -= (signed)s->period_size;
1594 else
1595 s->count %= s->period_size;
1596
1597 spin_unlock(&chip->reg_lock);
1598 snd_pcm_period_elapsed(subs);
1599 spin_lock(&chip->reg_lock);
1600 }
1601}
1602
1603static void snd_m3_update_hw_volume(unsigned long private_data)
1604{
1605 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1606 int x, val;
1607 unsigned long flags;
1608
1609 /* Figure out which volume control button was pushed,
1610 based on differences from the default register
1611 values. */
1612 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1613
1614 /* Reset the volume control registers. */
1615 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1616 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1617 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1618 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1619
1620 if (!chip->master_switch || !chip->master_volume)
1621 return;
1622
1623 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1624 spin_lock_irqsave(&chip->ac97_lock, flags);
1625
1626 val = chip->ac97->regs[AC97_MASTER_VOL];
1627 switch (x) {
1628 case 0x88:
1629 /* mute */
1630 val ^= 0x8000;
1631 chip->ac97->regs[AC97_MASTER_VOL] = val;
1632 outw(val, chip->iobase + CODEC_DATA);
1633 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1634 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1635 &chip->master_switch->id);
1636 break;
1637 case 0xaa:
1638 /* volume up */
1639 if ((val & 0x7f) > 0)
1640 val--;
1641 if ((val & 0x7f00) > 0)
1642 val -= 0x0100;
1643 chip->ac97->regs[AC97_MASTER_VOL] = val;
1644 outw(val, chip->iobase + CODEC_DATA);
1645 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1646 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1647 &chip->master_volume->id);
1648 break;
1649 case 0x66:
1650 /* volume down */
1651 if ((val & 0x7f) < 0x1f)
1652 val++;
1653 if ((val & 0x7f00) < 0x1f00)
1654 val += 0x0100;
1655 chip->ac97->regs[AC97_MASTER_VOL] = val;
1656 outw(val, chip->iobase + CODEC_DATA);
1657 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1658 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1659 &chip->master_volume->id);
1660 break;
1661 }
1662 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1663}
1664
1665static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1666{
1667 struct snd_m3 *chip = dev_id;
1668 u8 status;
1669 int i;
1670
1671 status = inb(chip->iobase + HOST_INT_STATUS);
1672
1673 if (status == 0xff)
1674 return IRQ_NONE;
1675
1676 if (status & HV_INT_PENDING)
1677 tasklet_schedule(&chip->hwvol_tq);
1678
1679 /*
1680 * ack an assp int if its running
1681 * and has an int pending
1682 */
1683 if (status & ASSP_INT_PENDING) {
1684 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1685 if (!(ctl & STOP_ASSP_CLOCK)) {
1686 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1687 if (ctl & DSP2HOST_REQ_TIMER) {
1688 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1689 /* update adc/dac info if it was a timer int */
1690 spin_lock(&chip->reg_lock);
1691 for (i = 0; i < chip->num_substreams; i++) {
1692 struct m3_dma *s = &chip->substreams[i];
1693 if (s->running)
1694 snd_m3_update_ptr(chip, s);
1695 }
1696 spin_unlock(&chip->reg_lock);
1697 }
1698 }
1699 }
1700
1701#if 0 /* TODO: not supported yet */
1702 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1703 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1704#endif
1705
1706 /* ack ints */
1707 outb(status, chip->iobase + HOST_INT_STATUS);
1708
1709 return IRQ_HANDLED;
1710}
1711
1712
1713/*
1714 */
1715
1716static struct snd_pcm_hardware snd_m3_playback =
1717{
1718 .info = (SNDRV_PCM_INFO_MMAP |
1719 SNDRV_PCM_INFO_INTERLEAVED |
1720 SNDRV_PCM_INFO_MMAP_VALID |
1721 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1722 /*SNDRV_PCM_INFO_PAUSE |*/
1723 SNDRV_PCM_INFO_RESUME),
1724 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1725 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1726 .rate_min = 8000,
1727 .rate_max = 48000,
1728 .channels_min = 1,
1729 .channels_max = 2,
1730 .buffer_bytes_max = (512*1024),
1731 .period_bytes_min = 64,
1732 .period_bytes_max = (512*1024),
1733 .periods_min = 1,
1734 .periods_max = 1024,
1735};
1736
1737static struct snd_pcm_hardware snd_m3_capture =
1738{
1739 .info = (SNDRV_PCM_INFO_MMAP |
1740 SNDRV_PCM_INFO_INTERLEAVED |
1741 SNDRV_PCM_INFO_MMAP_VALID |
1742 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1743 /*SNDRV_PCM_INFO_PAUSE |*/
1744 SNDRV_PCM_INFO_RESUME),
1745 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1746 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1747 .rate_min = 8000,
1748 .rate_max = 48000,
1749 .channels_min = 1,
1750 .channels_max = 2,
1751 .buffer_bytes_max = (512*1024),
1752 .period_bytes_min = 64,
1753 .period_bytes_max = (512*1024),
1754 .periods_min = 1,
1755 .periods_max = 1024,
1756};
1757
1758
1759/*
1760 */
1761
1762static int
1763snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1764{
1765 int i;
1766 struct m3_dma *s;
1767
1768 spin_lock_irq(&chip->reg_lock);
1769 for (i = 0; i < chip->num_substreams; i++) {
1770 s = &chip->substreams[i];
1771 if (! s->opened)
1772 goto __found;
1773 }
1774 spin_unlock_irq(&chip->reg_lock);
1775 return -ENOMEM;
1776__found:
1777 s->opened = 1;
1778 s->running = 0;
1779 spin_unlock_irq(&chip->reg_lock);
1780
1781 subs->runtime->private_data = s;
1782 s->substream = subs;
1783
1784 /* set list owners */
1785 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1786 s->index_list[0] = &chip->mixer_list;
1787 } else
1788 s->index_list[0] = &chip->adc1_list;
1789 s->index_list[1] = &chip->msrc_list;
1790 s->index_list[2] = &chip->dma_list;
1791
1792 return 0;
1793}
1794
1795static void
1796snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1797{
1798 struct m3_dma *s = subs->runtime->private_data;
1799
1800 if (s == NULL)
1801 return; /* not opened properly */
1802
1803 spin_lock_irq(&chip->reg_lock);
1804 if (s->substream && s->running)
1805 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1806 if (s->in_lists) {
1807 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1808 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1809 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1810 s->in_lists = 0;
1811 }
1812 s->running = 0;
1813 s->opened = 0;
1814 spin_unlock_irq(&chip->reg_lock);
1815}
1816
1817static int
1818snd_m3_playback_open(struct snd_pcm_substream *subs)
1819{
1820 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1821 struct snd_pcm_runtime *runtime = subs->runtime;
1822 int err;
1823
1824 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1825 return err;
1826
1827 runtime->hw = snd_m3_playback;
1828
1829 return 0;
1830}
1831
1832static int
1833snd_m3_playback_close(struct snd_pcm_substream *subs)
1834{
1835 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1836
1837 snd_m3_substream_close(chip, subs);
1838 return 0;
1839}
1840
1841static int
1842snd_m3_capture_open(struct snd_pcm_substream *subs)
1843{
1844 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1845 struct snd_pcm_runtime *runtime = subs->runtime;
1846 int err;
1847
1848 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1849 return err;
1850
1851 runtime->hw = snd_m3_capture;
1852
1853 return 0;
1854}
1855
1856static int
1857snd_m3_capture_close(struct snd_pcm_substream *subs)
1858{
1859 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1860
1861 snd_m3_substream_close(chip, subs);
1862 return 0;
1863}
1864
1865/*
1866 * create pcm instance
1867 */
1868
1869static struct snd_pcm_ops snd_m3_playback_ops = {
1870 .open = snd_m3_playback_open,
1871 .close = snd_m3_playback_close,
1872 .ioctl = snd_pcm_lib_ioctl,
1873 .hw_params = snd_m3_pcm_hw_params,
1874 .hw_free = snd_m3_pcm_hw_free,
1875 .prepare = snd_m3_pcm_prepare,
1876 .trigger = snd_m3_pcm_trigger,
1877 .pointer = snd_m3_pcm_pointer,
1878};
1879
1880static struct snd_pcm_ops snd_m3_capture_ops = {
1881 .open = snd_m3_capture_open,
1882 .close = snd_m3_capture_close,
1883 .ioctl = snd_pcm_lib_ioctl,
1884 .hw_params = snd_m3_pcm_hw_params,
1885 .hw_free = snd_m3_pcm_hw_free,
1886 .prepare = snd_m3_pcm_prepare,
1887 .trigger = snd_m3_pcm_trigger,
1888 .pointer = snd_m3_pcm_pointer,
1889};
1890
1891static int __devinit
1892snd_m3_pcm(struct snd_m3 * chip, int device)
1893{
1894 struct snd_pcm *pcm;
1895 int err;
1896
1897 err = snd_pcm_new(chip->card, chip->card->driver, device,
1898 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1899 if (err < 0)
1900 return err;
1901
1902 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1903 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1904
1905 pcm->private_data = chip;
1906 pcm->info_flags = 0;
1907 strcpy(pcm->name, chip->card->driver);
1908 chip->pcm = pcm;
1909
1910 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1911 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1912
1913 return 0;
1914}
1915
1916
1917/*
1918 * ac97 interface
1919 */
1920
1921/*
1922 * Wait for the ac97 serial bus to be free.
1923 * return nonzero if the bus is still busy.
1924 */
1925static int snd_m3_ac97_wait(struct snd_m3 *chip)
1926{
1927 int i = 10000;
1928
1929 do {
1930 if (! (snd_m3_inb(chip, 0x30) & 1))
1931 return 0;
1932 cpu_relax();
1933 } while (i-- > 0);
1934
1935 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1936 return 1;
1937}
1938
1939static unsigned short
1940snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1941{
1942 struct snd_m3 *chip = ac97->private_data;
1943 unsigned long flags;
1944 unsigned short data = 0xffff;
1945
1946 if (snd_m3_ac97_wait(chip))
1947 goto fail;
1948 spin_lock_irqsave(&chip->ac97_lock, flags);
1949 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1950 if (snd_m3_ac97_wait(chip))
1951 goto fail_unlock;
1952 data = snd_m3_inw(chip, CODEC_DATA);
1953fail_unlock:
1954 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1955fail:
1956 return data;
1957}
1958
1959static void
1960snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1961{
1962 struct snd_m3 *chip = ac97->private_data;
1963 unsigned long flags;
1964
1965 if (snd_m3_ac97_wait(chip))
1966 return;
1967 spin_lock_irqsave(&chip->ac97_lock, flags);
1968 snd_m3_outw(chip, val, CODEC_DATA);
1969 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1970 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1971}
1972
1973
1974static void snd_m3_remote_codec_config(int io, int isremote)
1975{
1976 isremote = isremote ? 1 : 0;
1977
1978 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1979 io + RING_BUS_CTRL_B);
1980 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1981 io + SDO_OUT_DEST_CTRL);
1982 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1983 io + SDO_IN_DEST_CTRL);
1984}
1985
1986/*
1987 * hack, returns non zero on err
1988 */
1989static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1990{
1991 u16 ret;
1992
1993 if (snd_m3_ac97_wait(chip))
1994 return 1;
1995
1996 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1997
1998 if (snd_m3_ac97_wait(chip))
1999 return 1;
2000
2001 ret = snd_m3_inw(chip, 0x32);
2002
2003 return (ret == 0) || (ret == 0xffff);
2004}
2005
2006static void snd_m3_ac97_reset(struct snd_m3 *chip)
2007{
2008 u16 dir;
2009 int delay1 = 0, delay2 = 0, i;
2010 int io = chip->iobase;
2011
2012 if (chip->allegro_flag) {
2013 /*
2014 * the onboard codec on the allegro seems
2015 * to want to wait a very long time before
2016 * coming back to life
2017 */
2018 delay1 = 50;
2019 delay2 = 800;
2020 } else {
2021 /* maestro3 */
2022 delay1 = 20;
2023 delay2 = 500;
2024 }
2025
2026 for (i = 0; i < 5; i++) {
2027 dir = inw(io + GPIO_DIRECTION);
2028 if (!chip->irda_workaround)
2029 dir |= 0x10; /* assuming pci bus master? */
2030
2031 snd_m3_remote_codec_config(io, 0);
2032
2033 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2034 udelay(20);
2035
2036 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2037 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2038 outw(0, io + GPIO_DATA);
2039 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2040
2041 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2042
2043 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2044 udelay(5);
2045 /* ok, bring back the ac-link */
2046 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2047 outw(~0, io + GPIO_MASK);
2048
2049 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2050
2051 if (! snd_m3_try_read_vendor(chip))
2052 break;
2053
2054 delay1 += 10;
2055 delay2 += 100;
2056
2057 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2058 delay1, delay2);
2059 }
2060
2061#if 0
2062 /* more gung-ho reset that doesn't
2063 * seem to work anywhere :)
2064 */
2065 tmp = inw(io + RING_BUS_CTRL_A);
2066 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2067 msleep(20);
2068 outw(tmp, io + RING_BUS_CTRL_A);
2069 msleep(50);
2070#endif
2071}
2072
2073static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2074{
2075 struct snd_ac97_bus *pbus;
2076 struct snd_ac97_template ac97;
2077 struct snd_ctl_elem_id elem_id;
2078 int err;
2079 static struct snd_ac97_bus_ops ops = {
2080 .write = snd_m3_ac97_write,
2081 .read = snd_m3_ac97_read,
2082 };
2083
2084 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2085 return err;
2086
2087 memset(&ac97, 0, sizeof(ac97));
2088 ac97.private_data = chip;
2089 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2090 return err;
2091
2092 /* seems ac97 PCM needs initialization.. hack hack.. */
2093 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2094 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2095 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2096
2097 memset(&elem_id, 0, sizeof(elem_id));
2098 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2099 strcpy(elem_id.name, "Master Playback Switch");
2100 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2101 memset(&elem_id, 0, sizeof(elem_id));
2102 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2103 strcpy(elem_id.name, "Master Playback Volume");
2104 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2105
2106 return 0;
2107}
2108
2109
2110/*
2111 * initialize ASSP
2112 */
2113
2114#define MINISRC_LPF_LEN 10
2115static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2116 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2117 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2118};
2119
2120static void snd_m3_assp_init(struct snd_m3 *chip)
2121{
2122 unsigned int i;
2123 const u16 *data;
2124
2125 /* zero kernel data */
2126 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2127 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2128 KDATA_BASE_ADDR + i, 0);
2129
2130 /* zero mixer data? */
2131 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2133 KDATA_BASE_ADDR2 + i, 0);
2134
2135 /* init dma pointer */
2136 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2137 KDATA_CURRENT_DMA,
2138 KDATA_DMA_XFER0);
2139
2140 /* write kernel into code memory.. */
2141 data = (const u16 *)chip->assp_kernel_image->data;
2142 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2143 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2144 REV_B_CODE_MEMORY_BEGIN + i,
2145 le16_to_cpu(data[i]));
2146 }
2147
2148 /*
2149 * We only have this one client and we know that 0x400
2150 * is free in our kernel's mem map, so lets just
2151 * drop it there. It seems that the minisrc doesn't
2152 * need vectors, so we won't bother with them..
2153 */
2154 data = (const u16 *)chip->assp_minisrc_image->data;
2155 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2156 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2157 0x400 + i, le16_to_cpu(data[i]));
2158 }
2159
2160 /*
2161 * write the coefficients for the low pass filter?
2162 */
2163 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2164 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2165 0x400 + MINISRC_COEF_LOC + i,
2166 minisrc_lpf[i]);
2167 }
2168
2169 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2170 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2171 0x8000);
2172
2173 /*
2174 * the minisrc is the only thing on
2175 * our task list..
2176 */
2177 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2178 KDATA_TASK0,
2179 0x400);
2180
2181 /*
2182 * init the mixer number..
2183 */
2184
2185 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2186 KDATA_MIXER_TASK_NUMBER,0);
2187
2188 /*
2189 * EXTREME KERNEL MASTER VOLUME
2190 */
2191 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2192 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2193 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2194 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2195
2196 chip->mixer_list.curlen = 0;
2197 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2198 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2199 chip->adc1_list.curlen = 0;
2200 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2201 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2202 chip->dma_list.curlen = 0;
2203 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2204 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2205 chip->msrc_list.curlen = 0;
2206 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2207 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2208}
2209
2210
2211static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2212{
2213 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2214 MINISRC_IN_BUFFER_SIZE / 2 +
2215 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2216 int address, i;
2217
2218 /*
2219 * the revb memory map has 0x1100 through 0x1c00
2220 * free.
2221 */
2222
2223 /*
2224 * align instance address to 256 bytes so that its
2225 * shifted list address is aligned.
2226 * list address = (mem address >> 1) >> 7;
2227 */
2228 data_bytes = ALIGN(data_bytes, 256);
2229 address = 0x1100 + ((data_bytes/2) * index);
2230
2231 if ((address + (data_bytes/2)) >= 0x1c00) {
2232 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2233 data_bytes, index, address);
2234 return -ENOMEM;
2235 }
2236
2237 s->number = index;
2238 s->inst.code = 0x400;
2239 s->inst.data = address;
2240
2241 for (i = data_bytes / 2; i > 0; address++, i--) {
2242 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2243 address, 0);
2244 }
2245
2246 return 0;
2247}
2248
2249
2250/*
2251 * this works for the reference board, have to find
2252 * out about others
2253 *
2254 * this needs more magic for 4 speaker, but..
2255 */
2256static void
2257snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2258{
2259 int io = chip->iobase;
2260 u16 gpo, polarity;
2261
2262 if (! chip->external_amp)
2263 return;
2264
2265 polarity = enable ? 0 : 1;
2266 polarity = polarity << chip->amp_gpio;
2267 gpo = 1 << chip->amp_gpio;
2268
2269 outw(~gpo, io + GPIO_MASK);
2270
2271 outw(inw(io + GPIO_DIRECTION) | gpo,
2272 io + GPIO_DIRECTION);
2273
2274 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2275 io + GPIO_DATA);
2276
2277 outw(0xffff, io + GPIO_MASK);
2278}
2279
2280static void
2281snd_m3_hv_init(struct snd_m3 *chip)
2282{
2283 unsigned long io = chip->iobase;
2284 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2285
2286 if (!chip->is_omnibook)
2287 return;
2288
2289 /*
2290 * Volume buttons on some HP OmniBook laptops
2291 * require some GPIO magic to work correctly.
2292 */
2293 outw(0xffff, io + GPIO_MASK);
2294 outw(0x0000, io + GPIO_DATA);
2295
2296 outw(~val, io + GPIO_MASK);
2297 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2298 outw(val, io + GPIO_MASK);
2299
2300 outw(0xffff, io + GPIO_MASK);
2301}
2302
2303static int
2304snd_m3_chip_init(struct snd_m3 *chip)
2305{
2306 struct pci_dev *pcidev = chip->pci;
2307 unsigned long io = chip->iobase;
2308 u32 n;
2309 u16 w;
2310 u8 t; /* makes as much sense as 'n', no? */
2311
2312 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2313 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2314 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2315 DISABLE_LEGACY);
2316 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2317
2318 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2319 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2320 n |= chip->hv_config;
2321 /* For some reason we must always use reduced debounce. */
2322 n |= REDUCED_DEBOUNCE;
2323 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2324 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2325
2326 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2327 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2328 n &= ~INT_CLK_SELECT;
2329 if (!chip->allegro_flag) {
2330 n &= ~INT_CLK_MULT_ENABLE;
2331 n |= INT_CLK_SRC_NOT_PCI;
2332 }
2333 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2334 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2335
2336 if (chip->allegro_flag) {
2337 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2338 n |= IN_CLK_12MHZ_SELECT;
2339 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2340 }
2341
2342 t = inb(chip->iobase + ASSP_CONTROL_A);
2343 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2344 t |= ASSP_CLK_49MHZ_SELECT;
2345 t |= ASSP_0_WS_ENABLE;
2346 outb(t, chip->iobase + ASSP_CONTROL_A);
2347
2348 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2349 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2350
2351 outb(0x00, io + HARDWARE_VOL_CTRL);
2352 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2353 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2354 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2355 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2356
2357 return 0;
2358}
2359
2360static void
2361snd_m3_enable_ints(struct snd_m3 *chip)
2362{
2363 unsigned long io = chip->iobase;
2364 unsigned short val;
2365
2366 /* TODO: MPU401 not supported yet */
2367 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2368 if (chip->hv_config & HV_CTRL_ENABLE)
2369 val |= HV_INT_ENABLE;
2370 outw(val, io + HOST_INT_CTRL);
2371 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2372 io + ASSP_CONTROL_C);
2373}
2374
2375
2376/*
2377 */
2378
2379static int snd_m3_free(struct snd_m3 *chip)
2380{
2381 struct m3_dma *s;
2382 int i;
2383
2384 if (chip->substreams) {
2385 spin_lock_irq(&chip->reg_lock);
2386 for (i = 0; i < chip->num_substreams; i++) {
2387 s = &chip->substreams[i];
2388 /* check surviving pcms; this should not happen though.. */
2389 if (s->substream && s->running)
2390 snd_m3_pcm_stop(chip, s, s->substream);
2391 }
2392 spin_unlock_irq(&chip->reg_lock);
2393 kfree(chip->substreams);
2394 }
2395 if (chip->iobase) {
2396 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2397 }
2398
2399#ifdef CONFIG_PM
2400 vfree(chip->suspend_mem);
2401#endif
2402
2403 if (chip->irq >= 0)
2404 free_irq(chip->irq, chip);
2405
2406 if (chip->iobase)
2407 pci_release_regions(chip->pci);
2408
2409 release_firmware(chip->assp_kernel_image);
2410 release_firmware(chip->assp_minisrc_image);
2411
2412 pci_disable_device(chip->pci);
2413 kfree(chip);
2414 return 0;
2415}
2416
2417
2418/*
2419 * APM support
2420 */
2421#ifdef CONFIG_PM
2422static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2423{
2424 struct snd_card *card = pci_get_drvdata(pci);
2425 struct snd_m3 *chip = card->private_data;
2426 int i, dsp_index;
2427
2428 if (chip->suspend_mem == NULL)
2429 return 0;
2430
2431 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2432 snd_pcm_suspend_all(chip->pcm);
2433 snd_ac97_suspend(chip->ac97);
2434
2435 msleep(10); /* give the assp a chance to idle.. */
2436
2437 snd_m3_assp_halt(chip);
2438
2439 /* save dsp image */
2440 dsp_index = 0;
2441 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2442 chip->suspend_mem[dsp_index++] =
2443 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2444 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2445 chip->suspend_mem[dsp_index++] =
2446 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2447
2448 pci_disable_device(pci);
2449 pci_save_state(pci);
2450 pci_set_power_state(pci, pci_choose_state(pci, state));
2451 return 0;
2452}
2453
2454static int m3_resume(struct pci_dev *pci)
2455{
2456 struct snd_card *card = pci_get_drvdata(pci);
2457 struct snd_m3 *chip = card->private_data;
2458 int i, dsp_index;
2459
2460 if (chip->suspend_mem == NULL)
2461 return 0;
2462
2463 pci_set_power_state(pci, PCI_D0);
2464 pci_restore_state(pci);
2465 if (pci_enable_device(pci) < 0) {
2466 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2467 "disabling device\n");
2468 snd_card_disconnect(card);
2469 return -EIO;
2470 }
2471 pci_set_master(pci);
2472
2473 /* first lets just bring everything back. .*/
2474 snd_m3_outw(chip, 0, 0x54);
2475 snd_m3_outw(chip, 0, 0x56);
2476
2477 snd_m3_chip_init(chip);
2478 snd_m3_assp_halt(chip);
2479 snd_m3_ac97_reset(chip);
2480
2481 /* restore dsp image */
2482 dsp_index = 0;
2483 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2484 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2485 chip->suspend_mem[dsp_index++]);
2486 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2487 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2488 chip->suspend_mem[dsp_index++]);
2489
2490 /* tell the dma engine to restart itself */
2491 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2492 KDATA_DMA_ACTIVE, 0);
2493
2494 /* restore ac97 registers */
2495 snd_ac97_resume(chip->ac97);
2496
2497 snd_m3_assp_continue(chip);
2498 snd_m3_enable_ints(chip);
2499 snd_m3_amp_enable(chip, 1);
2500
2501 snd_m3_hv_init(chip);
2502
2503 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2504 return 0;
2505}
2506#endif /* CONFIG_PM */
2507
2508
2509/*
2510 */
2511
2512static int snd_m3_dev_free(struct snd_device *device)
2513{
2514 struct snd_m3 *chip = device->device_data;
2515 return snd_m3_free(chip);
2516}
2517
2518static int __devinit
2519snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2520 int enable_amp,
2521 int amp_gpio,
2522 struct snd_m3 **chip_ret)
2523{
2524 struct snd_m3 *chip;
2525 int i, err;
2526 const struct snd_pci_quirk *quirk;
2527 static struct snd_device_ops ops = {
2528 .dev_free = snd_m3_dev_free,
2529 };
2530
2531 *chip_ret = NULL;
2532
2533 if (pci_enable_device(pci))
2534 return -EIO;
2535
2536 /* check, if we can restrict PCI DMA transfers to 28 bits */
2537 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2538 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
2539 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2540 pci_disable_device(pci);
2541 return -ENXIO;
2542 }
2543
2544 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2545 if (chip == NULL) {
2546 pci_disable_device(pci);
2547 return -ENOMEM;
2548 }
2549
2550 spin_lock_init(&chip->reg_lock);
2551 spin_lock_init(&chip->ac97_lock);
2552
2553 switch (pci->device) {
2554 case PCI_DEVICE_ID_ESS_ALLEGRO:
2555 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2556 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2557 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2558 chip->allegro_flag = 1;
2559 break;
2560 }
2561
2562 chip->card = card;
2563 chip->pci = pci;
2564 chip->irq = -1;
2565
2566 chip->external_amp = enable_amp;
2567 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2568 chip->amp_gpio = amp_gpio;
2569 else {
2570 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2571 if (quirk) {
2572#ifndef TARGET_OS2
2573 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2574 "for '%s'\n", quirk->name);
2575#endif
2576 chip->amp_gpio = quirk->value;
2577 } else if (chip->allegro_flag)
2578 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2579 else /* presumably this is for all 'maestro3's.. */
2580 chip->amp_gpio = GPO_EXT_AMP_M3;
2581 }
2582
2583 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2584 if (quirk) {
2585#ifndef TARGET_OS2
2586 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2587 "for '%s'\n", quirk->name);
2588#endif
2589 chip->irda_workaround = 1;
2590 }
2591 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2592 if (quirk)
2593 chip->hv_config = quirk->value;
2594 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2595 chip->is_omnibook = 1;
2596
2597 chip->num_substreams = NR_DSPS;
2598 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2599 GFP_KERNEL);
2600 if (chip->substreams == NULL) {
2601 kfree(chip);
2602 pci_disable_device(pci);
2603 return -ENOMEM;
2604 }
2605
2606 err = request_firmware(&chip->assp_kernel_image,
2607 "ess/maestro3_assp_kernel.fw", &pci->dev);
2608 if (err < 0) {
2609 snd_m3_free(chip);
2610 return err;
2611 }
2612
2613 err = request_firmware(&chip->assp_minisrc_image,
2614 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2615 if (err < 0) {
2616 snd_m3_free(chip);
2617 return err;
2618 }
2619
2620 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2621 snd_m3_free(chip);
2622 return err;
2623 }
2624 chip->iobase = pci_resource_start(pci, 0);
2625
2626 /* just to be sure */
2627 pci_set_master(pci);
2628
2629 snd_m3_chip_init(chip);
2630 snd_m3_assp_halt(chip);
2631
2632 snd_m3_ac97_reset(chip);
2633
2634 snd_m3_amp_enable(chip, 1);
2635
2636 snd_m3_hv_init(chip);
2637
2638 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2639
2640 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2641 card->driver, chip)) {
2642 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2643 snd_m3_free(chip);
2644 return -ENOMEM;
2645 }
2646 chip->irq = pci->irq;
2647
2648#ifdef CONFIG_PM
2649 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2650 if (chip->suspend_mem == NULL)
2651 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2652#endif
2653
2654 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2655 snd_m3_free(chip);
2656 return err;
2657 }
2658
2659 if ((err = snd_m3_mixer(chip)) < 0)
2660 return err;
2661
2662 for (i = 0; i < chip->num_substreams; i++) {
2663 struct m3_dma *s = &chip->substreams[i];
2664 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2665 return err;
2666 }
2667
2668 if ((err = snd_m3_pcm(chip, 0)) < 0)
2669 return err;
2670
2671 snd_m3_enable_ints(chip);
2672 snd_m3_assp_continue(chip);
2673
2674 snd_card_set_dev(card, &pci->dev);
2675
2676 *chip_ret = chip;
2677
2678 return 0;
2679}
2680
2681/*
2682 */
2683static int __devinit
2684snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2685{
2686 static int dev;
2687 struct snd_card *card;
2688 struct snd_m3 *chip;
2689 int err;
2690
2691#ifndef TARGET_OS2
2692 /* don't pick up modems */
2693 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2694 return -ENODEV;
2695#endif
2696 if (dev >= SNDRV_CARDS)
2697 return -ENODEV;
2698 if (!enable[dev]) {
2699 dev++;
2700 return -ENOENT;
2701 }
2702
2703 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2704 if (err < 0)
2705 return err;
2706
2707 switch (pci->device) {
2708 case PCI_DEVICE_ID_ESS_ALLEGRO:
2709 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2710 strcpy(card->driver, "Allegro");
2711 break;
2712 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2713 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2714 strcpy(card->driver, "Canyon3D-2");
2715 break;
2716 default:
2717 strcpy(card->driver, "Maestro3");
2718 break;
2719 }
2720
2721 if ((err = snd_m3_create(card, pci,
2722 external_amp[dev],
2723 amp_gpio[dev],
2724 &chip)) < 0) {
2725 snd_card_free(card);
2726 return err;
2727 }
2728 card->private_data = chip;
2729
2730 sprintf(card->shortname, "ESS %s PCI", card->driver);
2731 sprintf(card->longname, "%s at 0x%lx, irq %d",
2732 card->shortname, chip->iobase, chip->irq);
2733
2734 if ((err = snd_card_register(card)) < 0) {
2735 snd_card_free(card);
2736 return err;
2737 }
2738
2739#if 0 /* TODO: not supported yet */
2740 /* TODO enable MIDI IRQ and I/O */
2741 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2742 chip->iobase + MPU401_DATA_PORT,
2743 MPU401_INFO_INTEGRATED,
2744 chip->irq, 0, &chip->rmidi);
2745 if (err < 0)
2746 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2747#endif
2748
2749 pci_set_drvdata(pci, card);
2750 dev++;
2751 return 0;
2752}
2753
2754static void __devexit snd_m3_remove(struct pci_dev *pci)
2755{
2756 snd_card_free(pci_get_drvdata(pci));
2757 pci_set_drvdata(pci, NULL);
2758}
2759
2760static struct pci_driver driver = {
2761 .name = "Maestro3",
2762 .id_table = snd_m3_ids,
2763 .probe = snd_m3_probe,
2764 .remove = __devexit_p(snd_m3_remove),
2765#ifdef CONFIG_PM
2766 .suspend = m3_suspend,
2767 .resume = m3_resume,
2768#endif
2769};
2770
2771static int __init alsa_card_m3_init(void)
2772{
2773 return pci_register_driver(&driver);
2774}
2775
2776static void __exit alsa_card_m3_exit(void)
2777{
2778 pci_unregister_driver(&driver);
2779}
2780
2781module_init(alsa_card_m3_init)
2782module_exit(alsa_card_m3_exit)
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