source: GPL/trunk/alsa-kernel/pci/intel8x0.c@ 77

Last change on this file since 77 was 77, checked in by vladest, 19 years ago

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1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/mpu401.h>
41#define SNDRV_GET_ID
42#include <sound/initval.h>
43
44#define I810_DEBUG
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_CLASSES("{sound}");
50MODULE_DEVICES("{{Intel,82801AA-ICH},"
51 "{Intel,82901AB-ICH0},"
52 "{Intel,82801BA-ICH2},"
53 "{Intel,82801CA-ICH3},"
54 "{Intel,82801DB-ICH4},"
55 "{Intel,ICH5},"
56 "{Intel,ICH6},"
57 "{Intel,ICH7},"
58 "{Intel,6300ESB},"
59 "{Intel,ESB2},"
60 "{Intel,MX440},"
61 "{SiS,SI7012},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
64 "{AMD,AMD768},"
65 "{AMD,AMD8111},"
66 "{ALI,M5455}}");
67
68#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
69//#define SUPPORT_JOYSTICK 1
70#endif
71#define SUPPORT_MIDI 1
72
73extern int midi_port;
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78#ifdef TARGET_OS2
79static int ac97_clock[SNDRV_CARDS] = {REPEAT_SNDRV(0)};
80static char *ac97_quirk[SNDRV_CARDS];
81#else
82static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
83#endif
84#ifdef SUPPORT_JOYSTICK
85static int joystick[SNDRV_CARDS];
86#endif
87#ifdef SUPPORT_MIDI
88static int mpu_port[SNDRV_CARDS];// = {REPEAT_SNDRV(0x330)};;
89/* disabled */
90#endif
91
92static int buggy_semaphore;
93static int buggy_irq = -1; /* auto-check */
94
95MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
96MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
97MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
98MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
99MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
100MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
101MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
102MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
103MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
104MODULE_PARM(ac97_clock, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
105MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
106MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
107MODULE_PARM(ac97_quirk, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
108MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
109MODULE_PARM_SYNTAX(ac97_quirk, SNDRV_ENABLED ",allows:{{-1,3}},dialog:list,default:-1");
110#ifdef SUPPORT_JOYSTICK
111MODULE_PARM(joystick, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
112MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
113MODULE_PARM_SYNTAX(joystick, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
114#endif
115#ifdef SUPPORT_MIDI
116MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
117MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
118MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x300}},dialog:list");
119#endif
120
121/*
122 * Direct registers
123 */
124
125#ifndef PCI_DEVICE_ID_INTEL_82801
126#define PCI_DEVICE_ID_INTEL_82801 0x2415
127#endif
128#ifndef PCI_DEVICE_ID_INTEL_82901
129#define PCI_DEVICE_ID_INTEL_82901 0x2425
130#endif
131#ifndef PCI_DEVICE_ID_INTEL_82801BA
132#define PCI_DEVICE_ID_INTEL_82801BA 0x2445
133#endif
134#ifndef PCI_DEVICE_ID_INTEL_440MX
135#define PCI_DEVICE_ID_INTEL_440MX 0x7195
136#endif
137#ifndef PCI_DEVICE_ID_INTEL_ICH3
138#define PCI_DEVICE_ID_INTEL_ICH3 0x2485
139#endif
140#ifndef PCI_DEVICE_ID_INTEL_ICH4
141#define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
142#endif
143#ifndef PCI_DEVICE_ID_INTEL_ICH5
144#define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
145#endif
146#ifndef PCI_DEVICE_ID_INTEL_ESB_5
147#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
148#endif
149#ifndef PCI_DEVICE_ID_INTEL_ICH6_18
150#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
151#endif
152#ifndef PCI_DEVICE_ID_INTEL_ICH7_20
153#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
154#endif
155#ifndef PCI_DEVICE_ID_INTEL_ESB2_14
156#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
157#endif
158#ifndef PCI_DEVICE_ID_SI_7012
159#define PCI_DEVICE_ID_SI_7012 0x7012
160#endif
161#ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
162#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
163#endif
164#ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
165#define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
166#endif
167#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
168#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
169#endif
170#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
171#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
172#endif
173#ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
174#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
175#endif
176#ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
177#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
178#endif
179
180enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_INTEL_ICH5, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
181
182#define ICHREG(x) ICH_REG_##x
183
184#define DEFINE_REGSET(name,base) \
185 enum { \
186 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
187 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
188 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
189 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
190 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
191 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
192 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
193 };
194
195/* busmaster blocks */
196DEFINE_REGSET(OFF, 0); /* offset */
197DEFINE_REGSET(PI, 0x00); /* PCM in */
198DEFINE_REGSET(PO, 0x10); /* PCM out */
199DEFINE_REGSET(MC, 0x20); /* Mic in */
200
201/* ICH4 busmaster blocks */
202DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
203DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
204DEFINE_REGSET(SP, 0x60); /* SPDIF out */
205
206/* values for each busmaster block */
207
208/* LVI */
209#define ICH_REG_LVI_MASK 0x1f
210
211/* SR */
212#define ICH_FIFOE 0x10 /* FIFO error */
213#define ICH_BCIS 0x08 /* buffer completion interrupt status */
214#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
215#define ICH_CELV 0x02 /* current equals last valid */
216#define ICH_DCH 0x01 /* DMA controller halted */
217
218/* PIV */
219#define ICH_REG_PIV_MASK 0x1f /* mask */
220
221/* CR */
222#define ICH_IOCE 0x10 /* interrupt on completion enable */
223#define ICH_FEIE 0x08 /* fifo error interrupt enable */
224#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
225#define ICH_RESETREGS 0x02 /* reset busmaster registers */
226#define ICH_STARTBM 0x01 /* start busmaster operation */
227
228
229/* global block */
230#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
231#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
232#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
233#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
234#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
235#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
236#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
237#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
238#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
239#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
240#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
241#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
242#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
243#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
244#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
245#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
246#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
247#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
248#define ICH_ACLINK 0x00000008 /* AClink shut off */
249#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
250#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
251#define ICH_GIE 0x00000001 /* GPI interrupt enable */
252#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
253#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
254#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
255#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
256#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
257#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
258#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
259#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
260#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
261#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
262#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
263#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
264#define ICH_MD3 0x00020000 /* modem power down semaphore */
265#define ICH_AD3 0x00010000 /* audio power down semaphore */
266#define ICH_RCS 0x00008000 /* read completion status */
267#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
268#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
269#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
270#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
271#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
272#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
273#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
274#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
275#define ICH_POINT 0x00000040 /* playback interrupt */
276#define ICH_PIINT 0x00000020 /* capture interrupt */
277#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
278#define ICH_MOINT 0x00000004 /* modem playback interrupt */
279#define ICH_MIINT 0x00000002 /* modem capture interrupt */
280#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
281#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
282#define ICH_CAS 0x01 /* codec access semaphore */
283#define ICH_REG_SDM 0x80
284#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
285#define ICH_DI2L_SHIFT 6
286#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
287#define ICH_DI1L_SHIFT 4
288#define ICH_SE 0x00000008 /* steer enable */
289#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
290
291#define ICH_MAX_FRAGS 32 /* max hw frags */
292
293
294/*
295 * registers for Ali5455
296 */
297
298/* ALi 5455 busmaster blocks */
299DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
300DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
301DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
302DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
303DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
304DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
305DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
306DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
307DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
308DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
309DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
310
311enum {
312 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
313 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
314 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
315 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
316 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
317 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
318 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
319 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
320 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
321 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
322 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
323 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
324 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
325 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
326 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
327 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
328 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
329 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
330 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
331 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
332 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
333};
334
335#define ALI_CAS_SEM_BUSY 0x80000000
336#define ALI_CPR_ADDR_SECONDARY 0x100
337#define ALI_CPR_ADDR_READ 0x80
338#define ALI_CSPSR_CODEC_READY 0x08
339#define ALI_CSPSR_READ_OK 0x02
340#define ALI_CSPSR_WRITE_OK 0x01
341
342/* interrupts for the whole chip by interrupt status register finish */
343
344#define ALI_INT_MICIN2 (1<<26)
345#define ALI_INT_PCMIN2 (1<<25)
346#define ALI_INT_I2SIN (1<<24)
347#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
348#define ALI_INT_SPDIFIN (1<<22)
349#define ALI_INT_LFEOUT (1<<21)
350#define ALI_INT_CENTEROUT (1<<20)
351#define ALI_INT_CODECSPDIFOUT (1<<19)
352#define ALI_INT_MICIN (1<<18)
353#define ALI_INT_PCMOUT (1<<17)
354#define ALI_INT_PCMIN (1<<16)
355#define ALI_INT_CPRAIS (1<<7) /* command port available */
356#define ALI_INT_SPRAIS (1<<5) /* status port available */
357#define ALI_INT_GPIO (1<<1)
358#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
359
360#define ICH_ALI_SC_RESET (1<<31) /* master reset */
361#define ICH_ALI_SC_AC97_DBL (1<<30)
362#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
363#define ICH_ALI_SC_IN_BITS (3<<18)
364#define ICH_ALI_SC_OUT_BITS (3<<16)
365#define ICH_ALI_SC_6CH_CFG (3<<14)
366#define ICH_ALI_SC_PCM_4 (1<<8)
367#define ICH_ALI_SC_PCM_6 (2<<8)
368#define ICH_ALI_SC_PCM_246_MASK (3<<8)
369
370#define ICH_ALI_SS_SEC_ID (3<<5)
371#define ICH_ALI_SS_PRI_ID (3<<3)
372
373#define ICH_ALI_IF_AC97SP (1<<21)
374#define ICH_ALI_IF_MC (1<<20)
375#define ICH_ALI_IF_PI (1<<19)
376#define ICH_ALI_IF_MC2 (1<<18)
377#define ICH_ALI_IF_PI2 (1<<17)
378#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
379#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
380#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
381#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
382#define ICH_ALI_IF_PO_SPDF (1<<3)
383#define ICH_ALI_IF_PO (1<<1)
384
385/*
386 *
387 */
388
389enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
390enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
391enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
392
393#define get_ichdev(substream) (struct ichdev *)(substream->runtime->private_data)
394
395typedef struct ichdev {
396 unsigned int ichd; /* ich device number */
397 unsigned long reg_offset; /* offset to bmaddr */
398 u32 *bdbar; /* CPU address (32bit) */
399 unsigned int bdbar_addr; /* PCI bus address (32bit) */
400 snd_pcm_substream_t *substream;
401 unsigned int physbuf; /* physical address (32bit) */
402 unsigned int size;
403 unsigned int fragsize;
404 unsigned int fragsize1;
405 unsigned int position;
406 unsigned int pos_shift;
407 int frags;
408 int lvi;
409 int lvi_frag;
410 int civ;
411 int ack;
412 int ack_reload;
413 unsigned int ack_bit;
414 unsigned int roff_sr;
415 unsigned int roff_picb;
416 unsigned int int_sta_mask; /* interrupt status mask */
417 unsigned int ali_slot; /* ALI DMA slot */
418 struct ac97_pcm *pcm;
419 int pcm_open_flag;
420 unsigned int page_attr_changed: 1;
421 unsigned int suspended: 1;
422};
423
424struct intel8x0 {
425 unsigned int device_type;
426
427 int irq;
428
429 unsigned int mmio;
430 unsigned long addr;
431 unsigned long remap_addr;
432 unsigned int bm_mmio;
433 unsigned long bmaddr;
434 unsigned long remap_bmaddr;
435
436 struct pci_dev *pci;
437 snd_card_t *card;
438
439 int pcm_devs;
440 snd_pcm_t *pcm[6];
441 struct ichdev ichd[6];
442
443 int multi4: 1,
444 multi6: 1,
445 dra: 1,
446 smp20bit: 1;
447 int in_ac97_init: 1,
448 in_sdin_init: 1;
449 unsigned in_measurement: 1; /* during ac97 clock measurement */
450 unsigned fix_nocache: 1; /* workaround for 440MX */
451 unsigned buggy_irq: 1; /* workaround for buggy mobos */
452 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
453 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
454
455 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
456 unsigned int sdm_saved; /* SDM reg value */
457
458 ac97_bus_t *ac97_bus;
459 ac97_t *ac97[3];
460 unsigned int ac97_sdin[3];
461 unsigned int max_codecs, ncodecs;
462 unsigned int *codec_bit;
463 unsigned int codec_isr_bits;
464 unsigned int codec_ready_bits;
465
466 snd_rawmidi_t *rmidi;
467
468 spinlock_t reg_lock;
469
470 u32 bdbars_count;
471 struct snd_dma_buffer bdbars;
472 u32 int_sta_reg; /* interrupt status register */
473 u32 int_sta_mask; /* interrupt status mask */
474};
475
476static struct pci_device_id snd_intel8x0_ids[] = {
477 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
478 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
479 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
480 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
481 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
482 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH5 */
483 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ESB */
484 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH6 */
485 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH7 */
486 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
487 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
488 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
489 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
490 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
491 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
492 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
493 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
494 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
495 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
496 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
497 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
498 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
499 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
500 { 0 }
501};
502
503MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
504
505
506/*
507 * Lowlevel I/O - busmaster
508 */
509
510static u8 igetbyte(struct intel8x0 *chip, u32 offset)
511{
512 if (chip->bm_mmio)
513 return readb(chip->remap_bmaddr + offset);
514 else
515 return inb(chip->bmaddr + offset);
516}
517
518static u16 igetword(struct intel8x0 *chip, u32 offset)
519{
520 if (chip->bm_mmio)
521 return readw(chip->remap_bmaddr + offset);
522 else
523 return inw(chip->bmaddr + offset);
524}
525
526static u32 igetdword(struct intel8x0 *chip, u32 offset)
527{
528 if (chip->bm_mmio)
529 return readl(chip->remap_bmaddr + offset);
530 else
531 return inl(chip->bmaddr + offset);
532}
533
534static void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
535{
536 if (chip->bm_mmio)
537 writeb(val, chip->remap_bmaddr + offset);
538 else
539 outb(val, chip->bmaddr + offset);
540}
541
542static void iputword(struct intel8x0 *chip, u32 offset, u16 val)
543{
544 if (chip->bm_mmio)
545 writew(val, chip->remap_bmaddr + offset);
546 else
547 outw(val, chip->bmaddr + offset);
548}
549
550static void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
551{
552 if (chip->bm_mmio)
553 writel(val, chip->remap_bmaddr + offset);
554 else
555 outl(val, chip->bmaddr + offset);
556}
557
558/*
559 * Lowlevel I/O - AC'97 registers
560 */
561
562static u16 iagetword(struct intel8x0 *chip, u32 offset)
563{
564 if (chip->mmio)
565 return readw(chip->remap_addr + offset);
566 else
567 return inw(chip->addr + offset);
568}
569
570static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
571{
572 if (chip->mmio)
573 writew(val, chip->remap_addr + offset);
574 else
575 outw(val, chip->addr + offset);
576}
577
578/*
579 * Basic I/O
580 */
581
582/*
583 * access to AC97 codec via normal i/o (for ICH and SIS7012)
584 */
585
586static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
587{
588 int time;
589
590 if (codec > 2)
591 return -EIO;
592 if (chip->in_sdin_init) {
593 /* we don't know the ready bit assignment at the moment */
594 /* so we check any */
595 codec = chip->codec_isr_bits;
596 } else {
597 codec = chip->codec_bit[chip->ac97_sdin[codec]];
598 }
599
600 /* codec ready ? */
601 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
602 return -EIO;
603
604 /* Anyone holding a semaphore for 1 msec should be shot... */
605 time = 100;
606 do {
607 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
608 return 0;
609 udelay(10);
610 } while (time--);
611
612 /* access to some forbidden (non existant) ac97 registers will not
613 * reset the semaphore. So even if you don't get the semaphore, still
614 * continue the access. We don't need the semaphore anyway. */
615 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
616 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
617 iagetword(chip, 0); /* clear semaphore flag */
618 /* I don't care about the semaphore */
619 return -EBUSY;
620}
621
622static void snd_intel8x0_codec_write(ac97_t *ac97,
623 unsigned short reg,
624 unsigned short val)
625{
626 struct intel8x0 *chip = ac97->private_data;
627
628 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
629 if (! chip->in_ac97_init)
630 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
631 }
632 iaputword(chip, reg + ac97->num * 0x80, val);
633}
634
635static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
636 unsigned short reg)
637{
638 struct intel8x0 *chip = ac97->private_data;
639 unsigned short res;
640 unsigned int tmp;
641
642 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
643 if (! chip->in_ac97_init)
644 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
645 res = 0xffff;
646 } else {
647 res = iagetword(chip, reg + ac97->num * 0x80);
648 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
649 /* reset RCS and preserve other R/WC bits */
650 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(chip->codec_ready_bits | ICH_GSCI));
651 if (! chip->in_ac97_init)
652 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
653 res = 0xffff;
654 }
655 }
656 return res;
657}
658
659static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
660 unsigned int codec)
661{
662 unsigned int tmp;
663
664 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
665 iagetword(chip, codec * 0x80);
666 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
667 /* reset RCS and preserve other R/WC bits */
668 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(chip->codec_ready_bits | ICH_GSCI));
669 }
670 }
671}
672
673/*
674 * access to AC97 for Ali5455
675 */
676static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
677{
678 int count = 0;
679 for (count = 0; count < 0x7f; count++) {
680 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
681 if (val & mask)
682 return 0;
683 }
684 if (! chip->in_ac97_init)
685 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
686 return -EBUSY;
687}
688
689static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
690{
691 int time = 100;
692 if (chip->buggy_semaphore)
693 return 0; /* just ignore ... */
694 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
695 udelay(1);
696 if (! time && ! chip->in_ac97_init)
697 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
698 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
699}
700
701static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
702{
703 struct intel8x0 *chip = ac97->private_data;
704 unsigned short data = 0xffff;
705
706 if (snd_intel8x0_ali_codec_semaphore(chip))
707 goto __err;
708 reg |= ALI_CPR_ADDR_READ;
709 if (ac97->num)
710 reg |= ALI_CPR_ADDR_SECONDARY;
711 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
712 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
713 goto __err;
714 data = igetword(chip, ICHREG(ALI_SPR));
715__err:
716 return data;
717}
718
719static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
720{
721 struct intel8x0 *chip = ac97->private_data;
722
723 if (snd_intel8x0_ali_codec_semaphore(chip))
724 return;
725 iputword(chip, ICHREG(ALI_CPR), val);
726 if (ac97->num)
727 reg |= ALI_CPR_ADDR_SECONDARY;
728 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
729 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
730}
731
732
733/*
734 * DMA I/O
735 */
736static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
737{
738 int idx;
739 u32 *bdbar = ichdev->bdbar;
740 unsigned long port = ichdev->reg_offset;
741
742 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
743 if (ichdev->size == ichdev->fragsize) {
744 ichdev->ack_reload = ichdev->ack = 2;
745 ichdev->fragsize1 = ichdev->fragsize >> 1;
746 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
747 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
748 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
749 ichdev->fragsize1 >> ichdev->pos_shift);
750 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
751 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
752 ichdev->fragsize1 >> ichdev->pos_shift);
753 }
754 ichdev->frags = 2;
755 } else {
756 ichdev->ack_reload = ichdev->ack = 1;
757 ichdev->fragsize1 = ichdev->fragsize;
758 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
759 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
760 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
761 ichdev->fragsize >> ichdev->pos_shift);
762 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
763 }
764 ichdev->frags = ichdev->size / ichdev->fragsize;
765 }
766 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
767 ichdev->civ = 0;
768 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
769 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
770 ichdev->position = 0;
771#if 0
772 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
773 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
774#endif
775 /* clear interrupts */
776 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
777}
778
779/*
780 * Interrupt handler
781 */
782
783static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
784{
785 unsigned long port = ichdev->reg_offset;
786 int status, civ, i, step;
787 int ack = 0;
788
789 spin_lock(&chip->reg_lock);
790 status = igetbyte(chip, port + ichdev->roff_sr);
791 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
792 if (!(status & ICH_BCIS)) {
793 step = 0;
794 } else if (civ == ichdev->civ) {
795 // snd_printd("civ same %d\n", civ);
796 step = 1;
797 ichdev->civ++;
798 ichdev->civ &= ICH_REG_LVI_MASK;
799 } else {
800 step = civ - ichdev->civ;
801 if (step < 0)
802 step += ICH_REG_LVI_MASK + 1;
803 // if (step != 1)
804 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
805 ichdev->civ = civ;
806 }
807
808 ichdev->position += step * ichdev->fragsize1;
809 ichdev->position %= ichdev->size;
810 ichdev->lvi += step;
811 ichdev->lvi &= ICH_REG_LVI_MASK;
812 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
813 for (i = 0; i < step; i++) {
814 ichdev->lvi_frag++;
815 ichdev->lvi_frag %= ichdev->frags;
816 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
817 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
818 if (--ichdev->ack == 0) {
819 ichdev->ack = ichdev->ack_reload;
820 ack = 1;
821 }
822 }
823 spin_unlock(&chip->reg_lock);
824 if (ack && ichdev->substream) {
825 snd_pcm_period_elapsed(ichdev->substream);
826 }
827 iputbyte(chip, port + ichdev->roff_sr,
828 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
829}
830
831static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
832{
833 struct intel8x0 *chip = dev_id;
834 struct ichdev *ichdev;
835 unsigned int status;
836 unsigned int i;
837#ifdef TARGET_OS2
838 int fOurIrq = FALSE;
839#endif
840
841 status = igetdword(chip, chip->int_sta_reg);
842 if (status == 0xffffffff) /* we are not yet resumed */
843 return IRQ_NONE;
844
845 if ((status & chip->int_sta_mask) == 0) {
846 static int err_count = 10;
847 if (status) {
848 /* ack */
849 iputdword(chip, chip->int_sta_reg, status);
850 /* FIXME: on some ICH5 board shows the same
851 * problem. So we return IRQ_HANDLED
852 * in any cases.
853 * (or, maybe add a new module param to control this?)
854 */
855#if 0
856 if (chip->device_type != DEVICE_NFORCE)
857 status ^= igetdword(chip, chip->int_sta_reg);
858#endif
859 }
860 return IRQ_NONE/*RETVAL(status)*/;
861 }
862#ifdef TARGET_OS2
863 fOurIrq = TRUE;
864#endif
865
866 for (i = 0; i < chip->bdbars_count; i++) {
867 ichdev = &chip->ichd[i];
868 if (status & ichdev->int_sta_mask)
869 snd_intel8x0_update(chip, ichdev);
870 }
871
872 /* ack them */
873 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
874#ifdef TARGET_OS2
875 if (fOurIrq) {
876 //eoi_irq(irq);
877 }
878#endif //TARGET_OS2
879
880 return IRQ_HANDLED;
881}
882
883/*
884 * PCM part
885 */
886
887static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
888{
889 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
890 struct ichdev *ichdev = get_ichdev(substream);
891 unsigned char val = 0;
892 unsigned long port = ichdev->reg_offset;
893
894 switch (cmd) {
895 case SNDRV_PCM_TRIGGER_RESUME:
896 ichdev->suspended = 0;
897 /* fallthru */
898 case SNDRV_PCM_TRIGGER_START:
899 val = ICH_IOCE | ICH_STARTBM;
900 break;
901 case SNDRV_PCM_TRIGGER_SUSPEND:
902 ichdev->suspended = 1;
903 /* fallthru */
904 case SNDRV_PCM_TRIGGER_STOP:
905 val = 0;
906 break;
907 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
908 val = ICH_IOCE;
909 break;
910 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
911 val = ICH_IOCE | ICH_STARTBM;
912 break;
913 default:
914 return -EINVAL;
915 }
916 iputbyte(chip, port + ICH_REG_OFF_CR, val);
917 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
918 /* wait until DMA stopped */
919 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
920 /* reset whole DMA things */
921 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
922 }
923 return 0;
924}
925
926static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
927{
928 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
929 struct ichdev *ichdev = get_ichdev(substream);
930 unsigned long port = ichdev->reg_offset;
931 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
932 unsigned int val, fifo;
933
934 val = igetdword(chip, ICHREG(ALI_DMACR));
935 switch (cmd) {
936 case SNDRV_PCM_TRIGGER_RESUME:
937 ichdev->suspended = 0;
938 /* fallthru */
939 case SNDRV_PCM_TRIGGER_START:
940 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
941 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
942 /* clear FIFO for synchronization of channels */
943 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
944 fifo &= ~(0xff << (ichdev->ali_slot % 4));
945 fifo |= 0x83 << (ichdev->ali_slot % 4);
946 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
947 }
948 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
949 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
950 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
951 break;
952 case SNDRV_PCM_TRIGGER_SUSPEND:
953 ichdev->suspended = 1;
954 /* fallthru */
955 case SNDRV_PCM_TRIGGER_STOP:
956 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
957 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
958 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
959 while (igetbyte(chip, port + ICH_REG_OFF_CR))
960 ;
961 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
962 break;
963 /* reset whole DMA things */
964 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
965 /* clear interrupts */
966 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
967 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
968 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
969 break;
970 default:
971 return -EINVAL;
972 }
973 return 0;
974}
975
976static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
977 snd_pcm_hw_params_t * hw_params)
978{
979 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
980 struct ichdev *ichdev = get_ichdev(substream);
981 int dbl = params_rate(hw_params) > 48000;
982 int err;
983
984 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
985 if (err < 0)
986 return err;
987 if (ichdev->pcm_open_flag) {
988 snd_ac97_pcm_close(ichdev->pcm);
989 ichdev->pcm_open_flag = 0;
990 }
991 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
992 params_channels(hw_params),
993 ichdev->pcm->r[dbl].slots);
994 if (err >= 0) {
995 ichdev->pcm_open_flag = 1;
996 /* Force SPDIF setting */
997 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
998 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
999 }
1000 return err;
1001}
1002
1003static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
1004{
1005 struct ichdev *ichdev = get_ichdev(substream);
1006
1007 if (ichdev->pcm_open_flag) {
1008 snd_ac97_pcm_close(ichdev->pcm);
1009 ichdev->pcm_open_flag = 0;
1010 }
1011 return snd_pcm_lib_free_pages(substream);
1012}
1013
1014static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
1015 snd_pcm_runtime_t *runtime)
1016{
1017 unsigned int cnt;
1018 int dbl = runtime->rate > 48000;
1019
1020 spin_lock_irq(&chip->reg_lock);
1021 switch (chip->device_type) {
1022 case DEVICE_ALI:
1023 cnt = igetdword(chip, ICHREG(ALI_SCR));
1024 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1025 if (runtime->channels == 4 || dbl)
1026 cnt |= ICH_ALI_SC_PCM_4;
1027 else if (runtime->channels == 6)
1028 cnt |= ICH_ALI_SC_PCM_6;
1029 iputdword(chip, ICHREG(ALI_SCR), cnt);
1030 break;
1031 case DEVICE_SIS:
1032 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1033 cnt &= ~ICH_SIS_PCM_246_MASK;
1034 if (runtime->channels == 4 || dbl)
1035 cnt |= ICH_SIS_PCM_4;
1036 else if (runtime->channels == 6)
1037 cnt |= ICH_SIS_PCM_6;
1038 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1039 break;
1040 default:
1041 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1042 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1043 if (runtime->channels == 4 || dbl)
1044 cnt |= ICH_PCM_4;
1045 else if (runtime->channels == 6)
1046 cnt |= ICH_PCM_6;
1047 if (chip->device_type == DEVICE_NFORCE) {
1048 /* reset to 2ch once to keep the 6 channel data in alignment,
1049 * to start from Front Left always
1050 */
1051 if (cnt & ICH_PCM_246_MASK) {
1052 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1053 spin_unlock_irq(&chip->reg_lock);
1054 msleep(50); /* grrr... */
1055 spin_lock_irq(&chip->reg_lock);
1056 }
1057 } else if (chip->device_type == DEVICE_INTEL_ICH4 ||
1058 chip->device_type == DEVICE_INTEL_ICH5) {
1059 if (runtime->sample_bits > 16)
1060 cnt |= ICH_PCM_20BIT;
1061 }
1062 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1063 break;
1064 }
1065 spin_unlock_irq(&chip->reg_lock);
1066}
1067
1068static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1069{
1070 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1071 snd_pcm_runtime_t *runtime = substream->runtime;
1072 struct ichdev *ichdev = get_ichdev(substream);
1073
1074 ichdev->physbuf = runtime->dma_addr;
1075 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1076 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1077 if (ichdev->ichd == ICHD_PCMOUT) {
1078 snd_intel8x0_setup_pcm_out(chip, runtime);
1079 if (chip->device_type == DEVICE_INTEL_ICH4 ||
1080 chip->device_type == DEVICE_INTEL_ICH5)
1081 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1082 }
1083 snd_intel8x0_setup_periods(chip, ichdev);
1084 return 0;
1085}
1086
1087static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1088{
1089 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1090 struct ichdev *ichdev = get_ichdev(substream);
1091 size_t ptr1, ptr;
1092 int civ, timeout = 100;
1093 unsigned int position;
1094
1095 spin_lock(&chip->reg_lock);
1096 do {
1097 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1098 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1099 position = ichdev->position;
1100 if (ptr1 == 0) {
1101 udelay(10);
1102 continue;
1103 }
1104 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1105 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1106 break;
1107 } while (timeout--);
1108 ptr1 <<= ichdev->pos_shift;
1109 ptr = ichdev->fragsize1 - ptr1;
1110 ptr += position;
1111 spin_unlock(&chip->reg_lock);
1112 if (ptr >= ichdev->size)
1113 return 0;
1114 return bytes_to_frames(substream->runtime, ptr);
1115}
1116
1117static snd_pcm_hardware_t snd_intel8x0_stream =
1118{
1119 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1120 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1121 SNDRV_PCM_INFO_MMAP_VALID |
1122 SNDRV_PCM_INFO_PAUSE |
1123 SNDRV_PCM_INFO_RESUME),
1124 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1125 .rates = SNDRV_PCM_RATE_48000,
1126 .rate_min = 48000,
1127 .rate_max = 48000,
1128 .channels_min = 2,
1129 .channels_max = 2,
1130 .buffer_bytes_max = 128 * 1024,
1131 .period_bytes_min = 32,
1132 .period_bytes_max = 128 * 1024,
1133 .periods_min = 1,
1134 .periods_max = 1024,
1135 .fifo_size = 0,
1136};
1137
1138static unsigned int channels4[] = {
1139 2, 4,
1140};
1141
1142static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1143 .count = ARRAY_SIZE(channels4),
1144 .list = channels4,
1145 .mask = 0,
1146};
1147
1148static unsigned int channels6[] = {
1149 2, 4, 6,
1150};
1151
1152static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1153 .count = ARRAY_SIZE(channels6),
1154 .list = channels6,
1155 .mask = 0,
1156};
1157
1158static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, struct ichdev *ichdev)
1159{
1160 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1161 snd_pcm_runtime_t *runtime = substream->runtime;
1162 int err;
1163
1164 ichdev->substream = substream;
1165 runtime->hw = snd_intel8x0_stream;
1166 runtime->hw.rates = ichdev->pcm->rates;
1167 snd_pcm_limit_hw_rates(runtime);
1168 if (chip->device_type == DEVICE_SIS) {
1169 // vladest workaround
1170 if (!runtime->hw.rates)
1171 runtime->hw.rates = SNDRV_PCM_RATE_48000;
1172 runtime->hw.buffer_bytes_max = 64*1024;
1173 runtime->hw.period_bytes_max = 64*1024;
1174 }
1175#if 1 /* vladest */
1176 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1177 return err;
1178#endif
1179 runtime->private_data = ichdev;
1180 return 0;
1181}
1182
1183static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1184{
1185 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1186 snd_pcm_runtime_t *runtime = substream->runtime;
1187 int err;
1188
1189 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1190 if (err < 0)
1191 {
1192 printk("snd_intel8x0_pcm_open open error: %i\n", err);
1193 return err;
1194 }
1195 if (chip->multi6) {
1196 runtime->hw.channels_max = 6;
1197 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1198 } else if (chip->multi4) {
1199 runtime->hw.channels_max = 4;
1200 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1201 }
1202 if (chip->dra) {
1203 snd_ac97_pcm_double_rate_rules(runtime);
1204 }
1205 if (chip->smp20bit)
1206 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1207 return 0;
1208}
1209
1210static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1211{
1212 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1213
1214 chip->ichd[ICHD_PCMOUT].substream = NULL;
1215 return 0;
1216}
1217
1218static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1219{
1220 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1221
1222 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1223}
1224
1225static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1226{
1227 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1228
1229 chip->ichd[ICHD_PCMIN].substream = NULL;
1230 return 0;
1231}
1232
1233static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1234{
1235 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1236
1237 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1238}
1239
1240static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1241{
1242 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1243
1244 chip->ichd[ICHD_MIC].substream = NULL;
1245 return 0;
1246}
1247
1248static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1249{
1250 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1251
1252 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1253}
1254
1255static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1256{
1257 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1258
1259 chip->ichd[ICHD_MIC2].substream = NULL;
1260 return 0;
1261}
1262
1263static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1264{
1265 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1266
1267 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1268}
1269
1270static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1271{
1272 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1273
1274 chip->ichd[ICHD_PCM2IN].substream = NULL;
1275 return 0;
1276}
1277
1278static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1279{
1280 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1281 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1282
1283 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1284}
1285
1286static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1287{
1288 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1289 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1290
1291 chip->ichd[idx].substream = NULL;
1292 return 0;
1293}
1294
1295static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1296{
1297 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1298 unsigned int val;
1299
1300 spin_lock_irq(&chip->reg_lock);
1301 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1302 val |= ICH_ALI_IF_AC97SP;
1303 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1304 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1305 spin_unlock_irq(&chip->reg_lock);
1306
1307 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1308}
1309
1310static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1311{
1312 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1313 unsigned int val;
1314
1315 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1316 spin_lock_irq(&chip->reg_lock);
1317 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1318 val &= ~ICH_ALI_IF_AC97SP;
1319 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1320 spin_unlock_irq(&chip->reg_lock);
1321
1322 return 0;
1323}
1324
1325static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1326{
1327 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1328
1329 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1330}
1331
1332static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1333{
1334 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1335
1336 chip->ichd[ALID_SPDIFIN].substream = NULL;
1337 return 0;
1338}
1339
1340#if 0 // NYI
1341static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1342{
1343 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1344
1345 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1346}
1347
1348static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1349{
1350 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1351
1352 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1353 return 0;
1354}
1355#endif
1356
1357static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1358 .open = snd_intel8x0_playback_open,
1359 .close = snd_intel8x0_playback_close,
1360 .ioctl = snd_pcm_lib_ioctl,
1361 .hw_params = snd_intel8x0_hw_params,
1362 .hw_free = snd_intel8x0_hw_free,
1363 .prepare = snd_intel8x0_pcm_prepare,
1364 .trigger = snd_intel8x0_pcm_trigger,
1365 .pointer = snd_intel8x0_pcm_pointer,
1366};
1367
1368static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1369 .open = snd_intel8x0_capture_open,
1370 .close = snd_intel8x0_capture_close,
1371 .ioctl = snd_pcm_lib_ioctl,
1372 .hw_params = snd_intel8x0_hw_params,
1373 .hw_free = snd_intel8x0_hw_free,
1374 .prepare = snd_intel8x0_pcm_prepare,
1375 .trigger = snd_intel8x0_pcm_trigger,
1376 .pointer = snd_intel8x0_pcm_pointer,
1377};
1378
1379static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1380 .open = snd_intel8x0_mic_open,
1381 .close = snd_intel8x0_mic_close,
1382 .ioctl = snd_pcm_lib_ioctl,
1383 .hw_params = snd_intel8x0_hw_params,
1384 .hw_free = snd_intel8x0_hw_free,
1385 .prepare = snd_intel8x0_pcm_prepare,
1386 .trigger = snd_intel8x0_pcm_trigger,
1387 .pointer = snd_intel8x0_pcm_pointer,
1388};
1389
1390static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1391 .open = snd_intel8x0_mic2_open,
1392 .close = snd_intel8x0_mic2_close,
1393 .ioctl = snd_pcm_lib_ioctl,
1394 .hw_params = snd_intel8x0_hw_params,
1395 .hw_free = snd_intel8x0_hw_free,
1396 .prepare = snd_intel8x0_pcm_prepare,
1397 .trigger = snd_intel8x0_pcm_trigger,
1398 .pointer = snd_intel8x0_pcm_pointer,
1399};
1400
1401static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1402 .open = snd_intel8x0_capture2_open,
1403 .close = snd_intel8x0_capture2_close,
1404 .ioctl = snd_pcm_lib_ioctl,
1405 .hw_params = snd_intel8x0_hw_params,
1406 .hw_free = snd_intel8x0_hw_free,
1407 .prepare = snd_intel8x0_pcm_prepare,
1408 .trigger = snd_intel8x0_pcm_trigger,
1409 .pointer = snd_intel8x0_pcm_pointer,
1410};
1411
1412static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1413 .open = snd_intel8x0_spdif_open,
1414 .close = snd_intel8x0_spdif_close,
1415 .ioctl = snd_pcm_lib_ioctl,
1416 .hw_params = snd_intel8x0_hw_params,
1417 .hw_free = snd_intel8x0_hw_free,
1418 .prepare = snd_intel8x0_pcm_prepare,
1419 .trigger = snd_intel8x0_pcm_trigger,
1420 .pointer = snd_intel8x0_pcm_pointer,
1421};
1422
1423static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1424 .open = snd_intel8x0_playback_open,
1425 .close = snd_intel8x0_playback_close,
1426 .ioctl = snd_pcm_lib_ioctl,
1427 .hw_params = snd_intel8x0_hw_params,
1428 .hw_free = snd_intel8x0_hw_free,
1429 .prepare = snd_intel8x0_pcm_prepare,
1430 .trigger = snd_intel8x0_ali_trigger,
1431 .pointer = snd_intel8x0_pcm_pointer,
1432};
1433
1434static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1435 .open = snd_intel8x0_capture_open,
1436 .close = snd_intel8x0_capture_close,
1437 .ioctl = snd_pcm_lib_ioctl,
1438 .hw_params = snd_intel8x0_hw_params,
1439 .hw_free = snd_intel8x0_hw_free,
1440 .prepare = snd_intel8x0_pcm_prepare,
1441 .trigger = snd_intel8x0_ali_trigger,
1442 .pointer = snd_intel8x0_pcm_pointer,
1443};
1444
1445static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1446 .open = snd_intel8x0_mic_open,
1447 .close = snd_intel8x0_mic_close,
1448 .ioctl = snd_pcm_lib_ioctl,
1449 .hw_params = snd_intel8x0_hw_params,
1450 .hw_free = snd_intel8x0_hw_free,
1451 .prepare = snd_intel8x0_pcm_prepare,
1452 .trigger = snd_intel8x0_ali_trigger,
1453 .pointer = snd_intel8x0_pcm_pointer,
1454};
1455
1456static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1457 .open = snd_intel8x0_ali_ac97spdifout_open,
1458 .close = snd_intel8x0_ali_ac97spdifout_close,
1459 .ioctl = snd_pcm_lib_ioctl,
1460 .hw_params = snd_intel8x0_hw_params,
1461 .hw_free = snd_intel8x0_hw_free,
1462 .prepare = snd_intel8x0_pcm_prepare,
1463 .trigger = snd_intel8x0_ali_trigger,
1464 .pointer = snd_intel8x0_pcm_pointer,
1465};
1466
1467static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1468 .open = snd_intel8x0_ali_spdifin_open,
1469 .close = snd_intel8x0_ali_spdifin_close,
1470 .ioctl = snd_pcm_lib_ioctl,
1471 .hw_params = snd_intel8x0_hw_params,
1472 .hw_free = snd_intel8x0_hw_free,
1473 .prepare = snd_intel8x0_pcm_prepare,
1474 .trigger = snd_intel8x0_pcm_trigger,
1475 .pointer = snd_intel8x0_pcm_pointer,
1476};
1477
1478#if 0 // NYI
1479static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1480 .open = snd_intel8x0_ali_spdifout_open,
1481 .close = snd_intel8x0_ali_spdifout_close,
1482 .ioctl = snd_pcm_lib_ioctl,
1483 .hw_params = snd_intel8x0_hw_params,
1484 .hw_free = snd_intel8x0_hw_free,
1485 .prepare = snd_intel8x0_pcm_prepare,
1486 .trigger = snd_intel8x0_pcm_trigger,
1487 .pointer = snd_intel8x0_pcm_pointer,
1488};
1489#endif // NYI
1490
1491
1492struct ich_pcm_table {
1493 char *suffix;
1494 snd_pcm_ops_t *playback_ops;
1495 snd_pcm_ops_t *capture_ops;
1496 size_t prealloc_size;
1497 size_t prealloc_max_size;
1498 int ac97_idx;
1499};
1500
1501static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device, struct ich_pcm_table *rec)
1502{
1503 snd_pcm_t *pcm;
1504 int err;
1505 char name[32];
1506
1507 if (rec->suffix)
1508 sprintf(name, "Intel ICH - %s", rec->suffix);
1509 else
1510 strcpy(name, "Intel ICH");
1511 err = snd_pcm_new(chip->card, name, device,
1512 rec->playback_ops ? 1 : 0,
1513 rec->capture_ops ? 1 : 0, &pcm);
1514 if (err < 0)
1515 return err;
1516
1517 if (rec->playback_ops)
1518 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1519 if (rec->capture_ops)
1520 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1521
1522 pcm->private_data = chip;
1523 pcm->info_flags = 0;
1524 if (rec->suffix)
1525 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1526 else
1527 strcpy(pcm->name, chip->card->shortname);
1528 chip->pcm[device] = pcm;
1529
1530 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1531 rec->prealloc_size, rec->prealloc_max_size);
1532
1533 return 0;
1534}
1535
1536static struct ich_pcm_table intel_pcms[] __devinitdata = {
1537 {
1538 .playback_ops = &snd_intel8x0_playback_ops,
1539 .capture_ops = &snd_intel8x0_capture_ops,
1540 .prealloc_size = 64 * 1024,
1541 .prealloc_max_size = 128 * 1024,
1542 },
1543 {
1544 .suffix = "MIC ADC",
1545 .capture_ops = &snd_intel8x0_capture_mic_ops,
1546 .prealloc_size = 0,
1547 .prealloc_max_size = 128 * 1024,
1548 .ac97_idx = ICHD_MIC,
1549 },
1550 {
1551 .suffix = "MIC2 ADC",
1552 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1553 .prealloc_size = 0,
1554 .prealloc_max_size = 128 * 1024,
1555 .ac97_idx = ICHD_MIC2,
1556 },
1557 {
1558 .suffix = "ADC2",
1559 .capture_ops = &snd_intel8x0_capture2_ops,
1560 .prealloc_size = 0,
1561 .prealloc_max_size = 128 * 1024,
1562 .ac97_idx = ICHD_PCM2IN,
1563 },
1564 {
1565 .suffix = "IEC958",
1566 .playback_ops = &snd_intel8x0_spdif_ops,
1567 .prealloc_size = 64 * 1024,
1568 .prealloc_max_size = 128 * 1024,
1569 .ac97_idx = ICHD_SPBAR,
1570 },
1571};
1572
1573static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1574 {
1575 .playback_ops = &snd_intel8x0_playback_ops,
1576 .capture_ops = &snd_intel8x0_capture_ops,
1577 .prealloc_size = 64 * 1024,
1578 .prealloc_max_size = 128 * 1024,
1579 },
1580 {
1581 .suffix = "MIC ADC",
1582 .capture_ops = &snd_intel8x0_capture_mic_ops,
1583 .prealloc_size = 0,
1584 .prealloc_max_size = 128 * 1024,
1585 .ac97_idx = NVD_MIC,
1586 },
1587 {
1588 .suffix = "IEC958",
1589 .playback_ops = &snd_intel8x0_spdif_ops,
1590 .prealloc_size = 64 * 1024,
1591 .prealloc_max_size = 128 * 1024,
1592 .ac97_idx = NVD_SPBAR,
1593 },
1594};
1595
1596static struct ich_pcm_table ali_pcms[] __devinitdata = {
1597 {
1598 .playback_ops = &snd_intel8x0_ali_playback_ops,
1599 .capture_ops = &snd_intel8x0_ali_capture_ops,
1600 .prealloc_size = 64 * 1024,
1601 .prealloc_max_size = 128 * 1024,
1602 },
1603 {
1604 .suffix = "MIC ADC",
1605 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1606 .prealloc_size = 0,
1607 .prealloc_max_size = 128 * 1024,
1608 .ac97_idx = ALID_MIC,
1609 },
1610 {
1611 .suffix = "IEC958",
1612 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1613 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1614 .prealloc_size = 64 * 1024,
1615 .prealloc_max_size = 128 * 1024,
1616 .ac97_idx = ALID_AC97SPDIFOUT,
1617 },
1618#if 0 // NYI
1619 {
1620 .suffix = "HW IEC958",
1621 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1622 .prealloc_size = 64 * 1024,
1623 .prealloc_max_size = 128 * 1024,
1624 },
1625#endif
1626};
1627
1628
1629static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1630{
1631 int i, tblsize, device, err;
1632 struct ich_pcm_table *tbl, *rec;
1633
1634 switch (chip->device_type) {
1635 case DEVICE_INTEL_ICH4:
1636 case DEVICE_INTEL_ICH5:
1637 tbl = intel_pcms;
1638 tblsize = ARRAY_SIZE(intel_pcms);
1639 break;
1640 case DEVICE_NFORCE:
1641 tbl = nforce_pcms;
1642 tblsize = ARRAY_SIZE(nforce_pcms);
1643 break;
1644 case DEVICE_ALI:
1645 tbl = ali_pcms;
1646 tblsize = ARRAY_SIZE(ali_pcms);
1647 break;
1648 default:
1649 tbl = intel_pcms;
1650 tblsize = 2;
1651 break;
1652 }
1653
1654 device = 0;
1655 for (i = 0; i < tblsize; i++) {
1656 rec = tbl + i;
1657 if (i > 0 && rec->ac97_idx) {
1658 /* activate PCM only when associated AC'97 codec */
1659 if (! chip->ichd[rec->ac97_idx].pcm)
1660 continue;
1661 }
1662 err = snd_intel8x0_pcm1(chip, device, rec);
1663 if (err < 0)
1664 return err;
1665 device++;
1666 }
1667
1668 chip->pcm_devs = device;
1669 return 0;
1670}
1671
1672
1673/*
1674 * Mixer part
1675 */
1676
1677static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1678{
1679 struct intel8x0 *chip = bus->private_data;
1680 chip->ac97_bus = NULL;
1681}
1682
1683static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1684{
1685 struct intel8x0 *chip = ac97->private_data;
1686 chip->ac97[ac97->num] = NULL;
1687}
1688
1689static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1690 /* front PCM */
1691 {
1692 .exclusive = 1,
1693 .r =
1694 {
1695 {
1696 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1697 (1 << AC97_SLOT_PCM_RIGHT) |
1698 (1 << AC97_SLOT_PCM_CENTER) |
1699 (1 << AC97_SLOT_PCM_SLEFT) |
1700 (1 << AC97_SLOT_PCM_SRIGHT) |
1701 (1 << AC97_SLOT_LFE)
1702 },
1703 {
1704 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1705 (1 << AC97_SLOT_PCM_RIGHT) |
1706 (1 << AC97_SLOT_PCM_LEFT_0) |
1707 (1 << AC97_SLOT_PCM_RIGHT_0)
1708 }
1709 }
1710 },
1711 /* PCM IN #1 */
1712 {
1713 .stream = 1,
1714 .exclusive = 1,
1715 .r = { {
1716 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1717 (1 << AC97_SLOT_PCM_RIGHT)
1718 }
1719 }
1720 },
1721 /* MIC IN #1 */
1722 {
1723 .stream = 1,
1724 .exclusive = 1,
1725 .r = { {
1726 .slots = (1 << AC97_SLOT_MIC)
1727 }
1728 }
1729 },
1730 /* S/PDIF PCM */
1731 {
1732 .exclusive = 1,
1733 .spdif = 1,
1734 .r = { {
1735 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1736 (1 << AC97_SLOT_SPDIF_RIGHT2)
1737 }
1738 }
1739 },
1740 /* PCM IN #2 */
1741 {
1742 .stream = 1,
1743 .exclusive = 1,
1744 .r = { {
1745 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1746 (1 << AC97_SLOT_PCM_RIGHT)
1747 }
1748 }
1749 },
1750 /* MIC IN #2 */
1751 {
1752 .stream = 1,
1753 .exclusive = 1,
1754 .r = { {
1755 .slots = (1 << AC97_SLOT_MIC)
1756 }
1757 }
1758 },
1759};
1760
1761static struct ac97_quirk ac97_quirks[] __devinitdata = {
1762 {
1763 .subvendor = 0x0e11,
1764 .subdevice = 0x008a,
1765 .name = "Compaq Evo W4000", /* AD1885 */
1766 .type = AC97_TUNE_HP_ONLY
1767 },
1768 {
1769 .subvendor = 0x0e11,
1770 .subdevice = 0x00b8,
1771 .name = "Compaq Evo D510C",
1772 .type = AC97_TUNE_HP_ONLY
1773 },
1774 {
1775 .subvendor = 0x0e11,
1776 .subdevice = 0x0860,
1777 .name = "HP/Compaq nx7010",
1778 .type = AC97_TUNE_MUTE_LED
1779 },
1780 {
1781 .subvendor = 0x1014,
1782 .subdevice = 0x1f00,
1783 .name = "MS-9128",
1784 .type = AC97_TUNE_ALC_JACK
1785 },
1786 {
1787 .subvendor = 0x1014,
1788 .subdevice = 0x0267,
1789 .name = "IBM NetVista A30p", /* AD1981B */
1790 .type = AC97_TUNE_HP_ONLY
1791 },
1792 {
1793 .subvendor = 0x1025,
1794 .subdevice = 0x0083,
1795 .name = "Acer Aspire 3003LCi",
1796 .type = AC97_TUNE_HP_ONLY
1797 },
1798 {
1799 .subvendor = 0x1028,
1800 .subdevice = 0x00d8,
1801 .name = "Dell Precision 530", /* AD1885 */
1802 .type = AC97_TUNE_HP_ONLY
1803 },
1804 {
1805 .subvendor = 0x1028,
1806 .subdevice = 0x010d,
1807 .name = "Dell", /* which model? AD1885 */
1808 .type = AC97_TUNE_HP_ONLY
1809 },
1810 {
1811 .subvendor = 0x1028,
1812 .subdevice = 0x0126,
1813 .name = "Dell Optiplex GX260", /* AD1981A */
1814 .type = AC97_TUNE_HP_ONLY
1815 },
1816 {
1817 .subvendor = 0x1028,
1818 .subdevice = 0x012c,
1819 .name = "Dell Precision 650", /* AD1981A */
1820 .type = AC97_TUNE_HP_ONLY
1821 },
1822 {
1823 .subvendor = 0x1028,
1824 .subdevice = 0x012d,
1825 .name = "Dell Precision 450", /* AD1981B*/
1826 .type = AC97_TUNE_HP_ONLY
1827 },
1828 {
1829 .subvendor = 0x1028,
1830 .subdevice = 0x0147,
1831 .name = "Dell", /* which model? AD1981B*/
1832 .type = AC97_TUNE_HP_ONLY
1833 },
1834 {
1835 .subvendor = 0x1028,
1836 .subdevice = 0x0151,
1837 .name = "Dell Optiplex GX270", /* AD1981B */
1838 .type = AC97_TUNE_HP_ONLY
1839 },
1840 {
1841 .subvendor = 0x1028,
1842 .subdevice = 0x014e,
1843 .name = "Dell D800", /* STAC9750/51 */
1844 .type = AC97_TUNE_HP_ONLY
1845 },
1846 {
1847 .subvendor = 0x1028,
1848 .subdevice = 0x0163,
1849 .name = "Dell Unknown", /* STAC9750/51 */
1850 .type = AC97_TUNE_HP_ONLY
1851 },
1852 {
1853 .subvendor = 0x1028,
1854 .subdevice = 0x0191,
1855 .name = "Dell Inspiron 8600",
1856 .type = AC97_TUNE_HP_ONLY
1857 },
1858 {
1859 .subvendor = 0x103c,
1860 .subdevice = 0x006d,
1861 .name = "HP zv5000",
1862 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1863 },
1864 { /* FIXME: which codec? */
1865 .subvendor = 0x103c,
1866 .subdevice = 0x00c3,
1867 .name = "HP xw6000",
1868 .type = AC97_TUNE_HP_ONLY
1869 },
1870 {
1871 .subvendor = 0x103c,
1872 .subdevice = 0x088c,
1873 .name = "HP nc8000",
1874 .type = AC97_TUNE_MUTE_LED
1875 },
1876 {
1877 .subvendor = 0x103c,
1878 .subdevice = 0x0890,
1879 .name = "HP nc6000",
1880 .type = AC97_TUNE_MUTE_LED
1881 },
1882 {
1883 .subvendor = 0x103c,
1884 .subdevice = 0x0934,
1885 .name = "HP nx8220",
1886 .type = AC97_TUNE_MUTE_LED
1887 },
1888 {
1889 .subvendor = 0x103c,
1890 .subdevice = 0x129d,
1891 .name = "HP xw8000",
1892 .type = AC97_TUNE_HP_ONLY
1893 },
1894 {
1895 .subvendor = 0x103c,
1896 .subdevice = 0x0938,
1897 .name = "HP nc4200",
1898 .type = AC97_TUNE_HP_MUTE_LED
1899 },
1900 {
1901 .subvendor = 0x103c,
1902 .subdevice = 0x099c,
1903 .name = "HP nc6120",
1904 .type = AC97_TUNE_HP_MUTE_LED
1905 },
1906 {
1907 .subvendor = 0x103c,
1908 .subdevice = 0x0944,
1909 .name = "HP nx6110/nc6120",
1910 .type = AC97_TUNE_HP_MUTE_LED
1911 },
1912 {
1913 .subvendor = 0x103c,
1914 .subdevice = 0x0934,
1915 .name = "HP nc8220",
1916 .type = AC97_TUNE_HP_MUTE_LED
1917 },
1918 {
1919 .subvendor = 0x103c,
1920 .subdevice = 0x12f1,
1921 .name = "HP xw8200", /* AD1981B*/
1922 .type = AC97_TUNE_HP_ONLY
1923 },
1924 {
1925 .subvendor = 0x103c,
1926 .subdevice = 0x12f2,
1927 .name = "HP xw6200",
1928 .type = AC97_TUNE_HP_ONLY
1929 },
1930 {
1931 .subvendor = 0x103c,
1932 .subdevice = 0x3008,
1933 .name = "HP xw4200", /* AD1981B*/
1934 .type = AC97_TUNE_HP_ONLY
1935 },
1936 {
1937 .subvendor = 0x104d,
1938 .subdevice = 0x8197,
1939 .name = "Sony S1XP",
1940 .type = AC97_TUNE_INV_EAPD
1941 },
1942 {
1943 .subvendor = 0x1043,
1944 .subdevice = 0x80f3,
1945 .name = "ASUS ICH5/AD1985",
1946 .type = AC97_TUNE_AD_SHARING
1947 },
1948 {
1949 .subvendor = 0x10cf,
1950 .subdevice = 0x11c3,
1951 .name = "Fujitsu-Siemens E4010",
1952 .type = AC97_TUNE_HP_ONLY
1953 },
1954 {
1955 .subvendor = 0x10cf,
1956 .subdevice = 0x1225,
1957 .name = "Fujitsu-Siemens T3010",
1958 .type = AC97_TUNE_HP_ONLY
1959 },
1960 {
1961 .subvendor = 0x10cf,
1962 .subdevice = 0x1253,
1963 .name = "Fujitsu S6210", /* STAC9750/51 */
1964 .type = AC97_TUNE_HP_ONLY
1965 },
1966 {
1967 .subvendor = 0x10cf,
1968 .subdevice = 0x12ec,
1969 .name = "Fujitsu-Siemens 4010",
1970 .type = AC97_TUNE_HP_ONLY
1971 },
1972 {
1973 .subvendor = 0x10cf,
1974 .subdevice = 0x12f2,
1975 .name = "Fujitsu-Siemens Celsius H320",
1976 .type = AC97_TUNE_SWAP_HP
1977 },
1978 {
1979 .subvendor = 0x10f1,
1980 .subdevice = 0x2665,
1981 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1982 .type = AC97_TUNE_HP_ONLY
1983 },
1984 {
1985 .subvendor = 0x10f1,
1986 .subdevice = 0x2885,
1987 .name = "AMD64 Mobo", /* ALC650 */
1988 .type = AC97_TUNE_HP_ONLY
1989 },
1990 {
1991 .subvendor = 0x10f1,
1992 .subdevice = 0x2895,
1993 .name = "Tyan Thunder K8WE",
1994 .type = AC97_TUNE_HP_ONLY
1995 },
1996 {
1997 .subvendor = 0x110a,
1998 .subdevice = 0x0056,
1999 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2000 .type = AC97_TUNE_HP_ONLY
2001 },
2002 {
2003 .subvendor = 0x11d4,
2004 .subdevice = 0x5375,
2005 .name = "ADI AD1985 (discrete)",
2006 .type = AC97_TUNE_HP_ONLY
2007 },
2008 {
2009 .subvendor = 0x1462,
2010 .subdevice = 0x5470,
2011 .name = "MSI P4 ATX 645 Ultra",
2012 .type = AC97_TUNE_HP_ONLY
2013 },
2014 {
2015 .subvendor = 0x1734,
2016 .subdevice = 0x0088,
2017 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2018 .type = AC97_TUNE_HP_ONLY
2019 },
2020 {
2021 .subvendor = 0x8086,
2022 .subdevice = 0x0104,
2023 .name = "Intel D845GEBV2", /* AD1981B */
2024 .type = AC97_TUNE_HP_ONLY
2025 },
2026 {
2027 .subvendor = 0x8086,
2028 .subdevice = 0x2000,
2029 .mask = 0xfff0,
2030 .name = "Intel ICH5/AD1985",
2031 .type = AC97_TUNE_AD_SHARING
2032 },
2033 {
2034 .subvendor = 0x8086,
2035 .subdevice = 0x4000,
2036 .mask = 0xfff0,
2037 .name = "Intel ICH5/AD1985",
2038 .type = AC97_TUNE_AD_SHARING
2039 },
2040 {
2041 .subvendor = 0x8086,
2042 .subdevice = 0x4856,
2043 .name = "Intel D845WN (82801BA)",
2044 .type = AC97_TUNE_SWAP_HP
2045 },
2046 {
2047 .subvendor = 0x8086,
2048 .subdevice = 0x4d44,
2049 .name = "Intel D850EMV2", /* AD1885 */
2050 .type = AC97_TUNE_HP_ONLY
2051 },
2052 {
2053 .subvendor = 0x8086,
2054 .subdevice = 0x4d56,
2055 .name = "Intel ICH/AD1885",
2056 .type = AC97_TUNE_HP_ONLY
2057 },
2058 {
2059 .subvendor = 0x8086,
2060 .subdevice = 0x6000,
2061 .mask = 0xfff0,
2062 .name = "Intel ICH5/AD1985",
2063 .type = AC97_TUNE_AD_SHARING
2064 },
2065 {
2066 .subvendor = 0x8086,
2067 .subdevice = 0xe000,
2068 .mask = 0xfff0,
2069 .name = "Intel ICH5/AD1985",
2070 .type = AC97_TUNE_AD_SHARING
2071 },
2072#if 0 /* FIXME: this seems wrong on most boards */
2073 {
2074 .subvendor = 0x8086,
2075 .subdevice = 0xa000,
2076 .mask = 0xfff0,
2077 .name = "Intel ICH5/AD1985",
2078 .type = AC97_TUNE_HP_ONLY
2079 },
2080#endif
2081 {0} /* terminator */
2082};
2083
2084static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, char *quirk_override)
2085{
2086 ac97_bus_t *pbus;
2087 ac97_template_t ac97;
2088 int err;
2089 unsigned int i, codecs;
2090 unsigned int glob_sta = 0;
2091 ac97_bus_ops_t *ops;
2092 static ac97_bus_ops_t standard_bus_ops = {
2093 0,snd_intel8x0_codec_write,
2094 snd_intel8x0_codec_read,0,0
2095 };
2096 static ac97_bus_ops_t ali_bus_ops = {
2097 0,snd_intel8x0_ali_codec_write,
2098 snd_intel8x0_ali_codec_read,0,0
2099 };
2100 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2101 switch (chip->device_type) {
2102 case DEVICE_NFORCE:
2103 chip->spdif_idx = NVD_SPBAR;
2104 break;
2105 case DEVICE_ALI:
2106 chip->spdif_idx = ALID_AC97SPDIFOUT;
2107 break;
2108 case DEVICE_INTEL_ICH4:
2109 case DEVICE_INTEL_ICH5:
2110 chip->spdif_idx = ICHD_SPBAR;
2111 break;
2112 };
2113
2114 chip->in_ac97_init = 1;
2115
2116 memset(&ac97, 0, sizeof(ac97));
2117 ac97.private_data = chip;
2118 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2119 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2120 if (chip->device_type != DEVICE_ALI) {
2121 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2122 ops = &standard_bus_ops;
2123 chip->in_sdin_init = 1;
2124 codecs = 0;
2125 for (i = 0; i < chip->max_codecs; i++) {
2126 if (! (glob_sta & chip->codec_bit[i]))
2127 continue;
2128 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2129 chip->device_type == DEVICE_INTEL_ICH5) {
2130 snd_intel8x0_codec_read_test(chip, codecs);
2131 chip->ac97_sdin[codecs] =
2132 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2133 snd_assert(chip->ac97_sdin[codecs] < 3,
2134 chip->ac97_sdin[codecs] = 0);
2135 } else
2136 chip->ac97_sdin[codecs] = i;
2137 codecs++;
2138 chip->in_sdin_init = 1;
2139 }
2140 chip->in_sdin_init = 0;
2141 if (! codecs)
2142 codecs = 1;
2143 } else {
2144 ops = &ali_bus_ops;
2145 codecs = 1;
2146 /* detect the secondary codec */
2147 for (i = 0; i < 100; i++) {
2148 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2149 if (reg & 0x40) {
2150 codecs = 2;
2151 break;
2152 }
2153 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2154 udelay(1);
2155 }
2156 }
2157 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2158 goto __err;
2159 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2160 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2161 pbus->clock = ac97_clock;
2162 /* FIXME: my test board doesn't work well with VRA... */
2163 if (chip->device_type == DEVICE_ALI)
2164 pbus->no_vra = 1;
2165 else
2166 pbus->dra = 1;
2167 chip->ac97_bus = pbus;
2168 chip->ncodecs = codecs;
2169
2170 ac97.pci = chip->pci;
2171 for (i = 0; i < codecs; i++) {
2172 ac97.num = i;
2173 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2174 if (err != -EACCES)
2175 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2176 if (i == 0)
2177 goto __err;
2178 continue;
2179 }
2180 }
2181 /* tune up the primary codec */
2182 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2183 /* enable separate SDINs for ICH4 */
2184 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2185 chip->device_type == DEVICE_INTEL_ICH5)
2186 pbus->isdin = 1;
2187 /* find the available PCM streams */
2188 i = ARRAY_SIZE(ac97_pcm_defs);
2189 if (chip->device_type != DEVICE_INTEL_ICH4 &&
2190 chip->device_type != DEVICE_INTEL_ICH5)
2191 i -= 2; /* do not allocate PCM2IN and MIC2 */
2192 if (chip->spdif_idx < 0)
2193 i--; /* do not allocate S/PDIF */
2194 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2195 if (err < 0)
2196 goto __err;
2197 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2198 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2199 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2200 if (chip->spdif_idx >= 0)
2201 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2202 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2203 chip->device_type == DEVICE_INTEL_ICH5) {
2204 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2205 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2206 }
2207 /* enable separate SDINs for ICH4 */
2208 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2209 chip->device_type == DEVICE_INTEL_ICH5) {
2210 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2211 u8 tmp = igetbyte(chip, ICHREG(SDM));
2212 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2213 if (pcm) {
2214 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2215 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2216 for (i = 1; i < 4; i++) {
2217 if (pcm->r[0].codec[i]) {
2218 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2219 break;
2220 }
2221 }
2222 } else {
2223 tmp &= ~ICH_SE; /* steer disable */
2224 }
2225 iputbyte(chip, ICHREG(SDM), tmp);
2226 }
2227 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2228 chip->multi4 = 1;
2229 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2230 chip->multi6 = 1;
2231 }
2232 if (pbus->pcms[0].r[1].rslots[0]) {
2233 chip->dra = 1;
2234 }
2235 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2236 chip->device_type == DEVICE_INTEL_ICH5) {
2237 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2238 chip->smp20bit = 1;
2239 }
2240 if (chip->device_type == DEVICE_NFORCE) {
2241 /* 48kHz only */
2242 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2243 }
2244
2245 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2246 chip->device_type == DEVICE_INTEL_ICH5) {
2247 /* use slot 10/11 for SPDIF */
2248 u32 val;
2249 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2250 val |= ICH_PCM_SPDIF_1011;
2251 iputdword(chip, ICHREG(GLOB_CNT), val);
2252 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2253 }
2254 chip->in_ac97_init = 0;
2255 return 0;
2256
2257 __err:
2258 /* clear the cold-reset bit for the next chance */
2259 if (chip->device_type != DEVICE_ALI)
2260 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2261 return err;
2262}
2263
2264
2265/*
2266 *
2267 */
2268
2269static void do_ali_reset(struct intel8x0 *chip)
2270{
2271 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2272 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2273 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2274 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2275 iputdword(chip, ICHREG(ALI_INTERFACECR),
2276 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2277 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2278 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2279}
2280
2281#define do_delay(chip) do {\
2282 set_current_state(TASK_UNINTERRUPTIBLE);\
2283 schedule_timeout(1);\
2284 } while (0)
2285
2286static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2287{
2288 unsigned long end_time;
2289 unsigned int cnt, status, nstatus,i;
2290
2291#ifdef DEBUG
2292 dprintf(("ICH chip init begins"));
2293#endif
2294 /* put logic to right state */
2295 /* first clear status bits */
2296#if 1 // noone do it. wtf? //vladest 06.10.2003 13:51
2297 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2298 if (chip->device_type == DEVICE_NFORCE)
2299 status |= ICH_NVSPINT;
2300 cnt = igetdword(chip, ICHREG(GLOB_STA));
2301 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2302#endif
2303 // hmm. at least we should try
2304 //iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2305 /* ACLink on, 2 channels */
2306 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2307 // added by vladest
2308 // cnt &= ~ICH_ACLINK;
2309 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2310#ifdef CONFIG_SND_AC97_POWER_SAVE
2311 /* do cold reset - the full ac97 powerdown may leave the controller
2312 * in a warm state but actually it cannot communicate with the codec.
2313 */
2314 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2315 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2316 udelay(10);
2317 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2318 msleep(1);
2319#else
2320 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2321
2322 // ??? 25.03.2004 by vladest cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2323 // FIXME!!! cmi drivers didnt uses ICH_PCM_246_MASK
2324 /* finish cold or do warm reset */
2325#ifdef DEBUG
2326 dprintf(("ICH chip init try to wake up ACLink with %x",cnt));
2327#endif
2328 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2329// mdelay(500); //vladest 06.10.2003 15:08
2330 end_time = (jiffies + (HZ / 4)) + 1;
2331 i = 0;
2332 do {
2333 cnt=igetdword(chip, ICHREG(GLOB_CNT));
2334 if ((cnt & ICH_AC97WARM) == 0)
2335 goto __ok;
2336#ifdef DEBUG
2337 dprintf(("ICH chip init ACLink ON. try no %d got %x",i,cnt));
2338#endif
2339 do_delay(chip);
2340 i++;
2341 } while (i<100); //(time_after_eq(end_time, jiffies));
2342 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2343 return -EIO;
2344__ok:
2345#endif /* CONFIG_SND_AC97_POWER_SAVE */
2346#ifdef DEBUG
2347 dprintf(("ICH chip init ACLink ON"));
2348#endif
2349
2350// mdelay(50);
2351
2352 if (probing) {
2353 /* wait for any codec ready status.
2354 * Once it becomes ready it should remain ready
2355 * as long as we do not disable the ac97 link.
2356 */
2357 end_time = jiffies + HZ;
2358 do {
2359 status = igetdword(chip, ICHREG(GLOB_STA)) &
2360 chip->codec_isr_bits;
2361 if (status)
2362 break;
2363 mdelay(1);
2364 //do_delay(chip);
2365 } while (time_after_eq(end_time, jiffies));
2366
2367 if (! status) {
2368 /* no codec is found */
2369 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2370 return -EIO;
2371 }
2372#ifdef DEBUG
2373 dprintf(("ICH chip init codec ready"));
2374#endif
2375// mdelay(50);
2376
2377 /* wait for other codecs ready status. */
2378 end_time = jiffies + HZ / 4;
2379 while (status != chip->codec_isr_bits &&
2380 time_after_eq(end_time, jiffies)) {
2381 do_delay(chip);
2382 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2383 chip->codec_isr_bits;
2384 }
2385 } else {
2386 /* resume phase */
2387 int i;
2388 status = 0;
2389 for (i = 0; i < chip->ncodecs; i++)
2390 if (chip->ac97[i])
2391 status |= chip->codec_bit[chip->ac97_sdin[i]];
2392 /* wait until all the probed codecs are ready */
2393 end_time = jiffies + HZ;
2394 do {
2395 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & chip->codec_isr_bits;;
2396 if (status == nstatus)
2397 break;
2398 do_delay(chip);
2399 } while (time_after_eq(end_time, jiffies));
2400 }
2401
2402 if (chip->device_type == DEVICE_SIS) {
2403 /* unmute the output on SIS7012 */
2404 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2405 }
2406 if (chip->device_type == DEVICE_NFORCE) {
2407 /* enable SPDIF interrupt */
2408 unsigned int val;
2409 pci_read_config_dword(chip->pci, 0x4c, &val);
2410 val |= 0x1000000;
2411 pci_write_config_dword(chip->pci, 0x4c, val);
2412 }
2413#ifdef DEBUG
2414 dprintf(("ICH chip init finished"));
2415#endif
2416
2417 return 0;
2418}
2419
2420static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2421{
2422 u32 reg;
2423 int i = 0;
2424
2425 reg = igetdword(chip, ICHREG(ALI_SCR));
2426 if ((reg & 2) == 0) /* Cold required */
2427 reg |= 2;
2428 else
2429 reg |= 1; /* Warm */
2430 reg &= ~0x80000000; /* ACLink on */
2431 iputdword(chip, ICHREG(ALI_SCR), reg);
2432
2433 for (i = 0; i < HZ / 2; i++) {
2434 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2435 goto __ok;
2436 do_delay(chip);
2437 }
2438 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2439 if (probing)
2440 return -EIO;
2441
2442 __ok:
2443 for (i = 0; i < HZ / 2; i++) {
2444 reg = igetdword(chip, ICHREG(ALI_RTSR));
2445 if (reg & 0x80) /* primary codec */
2446 break;
2447 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2448 do_delay(chip);
2449 }
2450
2451 do_ali_reset(chip);
2452 return 0;
2453}
2454
2455static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2456{
2457 unsigned int i, timeout;
2458 int err;
2459
2460 if (chip->device_type != DEVICE_ALI) {
2461 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2462 return err;
2463 iagetword(chip, 0); /* clear semaphore flag */
2464 } else {
2465 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2466 return err;
2467 }
2468
2469 /* disable interrupts */
2470 for (i = 0; i < chip->bdbars_count; i++)
2471 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2472 /* reset channels */
2473 for (i = 0; i < chip->bdbars_count; i++)
2474 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2475 for (i = 0; i < chip->bdbars_count; i++) {
2476 timeout = 100000;
2477 while (--timeout != 0) {
2478 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2479 break;
2480 }
2481 if (timeout == 0)
2482 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2483 }
2484 /* initialize Buffer Descriptor Lists */
2485 for (i = 0; i < chip->bdbars_count; i++)
2486 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2487 return 0;
2488}
2489
2490static int snd_intel8x0_free(struct intel8x0 *chip)
2491{
2492 unsigned int i;
2493
2494 if (chip->irq < 0)
2495 goto __hw_end;
2496 /* disable interrupts */
2497 for (i = 0; i < chip->bdbars_count; i++)
2498 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2499 /* reset channels */
2500 for (i = 0; i < chip->bdbars_count; i++)
2501 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2502 if (chip->device_type == DEVICE_NFORCE) {
2503 /* stop the spdif interrupt */
2504 unsigned int val;
2505 pci_read_config_dword(chip->pci, 0x4c, &val);
2506 val &= ~0x1000000;
2507 pci_write_config_dword(chip->pci, 0x4c, val);
2508 }
2509 /* --- */
2510 synchronize_irq(chip->irq);
2511__hw_end:
2512 if (chip->irq >= 0)
2513 free_irq(chip->irq, (void *)chip);
2514 if (chip->bdbars.area)
2515 snd_dma_free_pages(&chip->bdbars);
2516 if (chip->remap_addr)
2517 iounmap((void *) chip->remap_addr);
2518 if (chip->remap_bmaddr)
2519 iounmap((void *) chip->remap_bmaddr);
2520 pci_release_regions(chip->pci);
2521 kfree(chip);
2522 return 0;
2523}
2524
2525#ifdef CONFIG_PM
2526/*
2527 * power management
2528 */
2529static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2530{
2531 struct snd_card *card = pci_get_drvdata(pci);
2532 struct intel8x0 *chip = card->private_data;
2533 int i;
2534
2535 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2536
2537 for (i = 0; i < chip->pcm_devs; i++)
2538 snd_pcm_suspend_all(chip->pcm[i]);
2539
2540 for (i = 0; i < chip->ncodecs; i++)
2541 if (chip->ac97[i]) //Rudi: check, if codec present !!!
2542 snd_ac97_suspend(chip->ac97[i]);
2543 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2544 chip->device_type == DEVICE_INTEL_ICH5)
2545 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2546
2547 if (chip->irq >= 0)
2548 free_irq(chip->irq, (void *)chip);
2549 pci_disable_device(pci);
2550 pci_save_state(pci);
2551 return 0;
2552}
2553
2554static int intel8x0_resume(struct pci_dev *pci)
2555{
2556 struct snd_card *card = pci_get_drvdata(pci);
2557 struct intel8x0 *chip = card->private_data;
2558 int i;
2559
2560 pci_restore_state(pci);
2561 pci_enable_device(pci);
2562 pci_set_master(pci);
2563 request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ,
2564 card->shortname, (void *)chip);
2565 chip->irq = pci->irq;
2566 synchronize_irq(chip->irq);
2567 snd_intel8x0_chip_init(chip, 0);
2568 /* re-initialize mixer stuff */
2569 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2570 chip->device_type == DEVICE_INTEL_ICH5) {
2571 /* enable separate SDINs for ICH4 */
2572 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2573 /* use slot 10/11 for SPDIF */
2574 iputdword(chip, ICHREG(GLOB_CNT),
2575 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2576 ICH_PCM_SPDIF_1011);
2577 }
2578
2579 for (i = 0; i < chip->ncodecs; i++)
2580 if (chip->ac97[i]) //Rudi: check, if codec present !!!
2581 snd_ac97_resume(chip->ac97[i]);
2582 /* resume status */
2583 for (i = 0; i < chip->bdbars_count; i++) {
2584 struct ichdev *ichdev = &chip->ichd[i];
2585 unsigned long port = ichdev->reg_offset;
2586 if (! ichdev->substream || ! ichdev->suspended)
2587 continue;
2588 if (ichdev->ichd == ICHD_PCMOUT)
2589 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2590 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2591 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2592 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2593 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2594 }
2595 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2596 return 0;
2597}
2598
2599#endif /* CONFIG_PM */
2600
2601#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2602
2603static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2604{
2605 snd_pcm_substream_t *subs;
2606 struct ichdev *ichdev;
2607 unsigned long port;
2608 unsigned long pos, t;
2609 struct timeval start_time, stop_time;
2610
2611 if (chip->ac97_bus->clock != 48000)
2612 return; /* specified in module option */
2613
2614 subs = chip->pcm[0]->streams[0].substream;
2615 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2616 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2617 return;
2618 }
2619 ichdev = &chip->ichd[ICHD_PCMOUT];
2620 ichdev->physbuf = subs->dma_buffer.addr;
2621 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2622 ichdev->substream = NULL; /* don't process interrupts */
2623
2624 /* set rate */
2625 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2626 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2627 return;
2628 }
2629 snd_intel8x0_setup_periods(chip, ichdev);
2630 port = ichdev->reg_offset;
2631 spin_lock_irq(&chip->reg_lock);
2632 /* trigger */
2633 if (chip->device_type != DEVICE_ALI)
2634 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2635 else {
2636 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2637 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2638 }
2639 do_gettimeofday(&start_time);
2640 spin_unlock_irq(&chip->reg_lock);
2641 mdelay(50);
2642
2643 spin_lock_irq(&chip->reg_lock);
2644 /* check the position */
2645 pos = ichdev->fragsize1;
2646 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2647 pos += ichdev->position;
2648 do_gettimeofday(&stop_time);
2649 /* stop */
2650 if (chip->device_type == DEVICE_ALI) {
2651 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2652 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2653 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2654 ;
2655 } else {
2656 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2657 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2658 ;
2659 }
2660 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2661 spin_unlock_irq(&chip->reg_lock);
2662#if 0
2663 t = stop_time.tv_sec - start_time.tv_sec;
2664 t *= 1000000;
2665 t += stop_time.tv_usec - start_time.tv_usec;
2666#else
2667 t = 50000; /* patch, suggested by r.ihle */
2668#endif
2669 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2670 if (t == 0) {
2671 snd_printk(KERN_ERR "?? calculation error..\n");
2672 return;
2673 }
2674 pos = (pos / 4) * 1000;
2675 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2676 if (pos < 40000 || pos >= 60000)
2677 /* abnormal value. hw problem? */
2678 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2679 else if (pos < 47500 || pos > 48500)
2680 /* not 48000Hz, tuning the clock.. */
2681 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2682 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2683 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2684}
2685
2686#ifdef CONFIG_PROC_FS
2687static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2688 snd_info_buffer_t * buffer)
2689{
2690 struct intel8x0 *chip = entry->private_data;
2691 unsigned int tmp;
2692
2693 snd_iprintf(buffer, "Intel8x0\n\n");
2694 if (chip->device_type == DEVICE_ALI)
2695 return;
2696 tmp = igetdword(chip, ICHREG(GLOB_STA));
2697 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2698 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2699 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2700 chip->device_type == DEVICE_INTEL_ICH5)
2701 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2702 snd_iprintf(buffer, "AC'97 codecs ready :");
2703 if (tmp & chip->codec_isr_bits) {
2704 int i;
2705 static const char *codecs[3] = {
2706 "primary", "secondary", "tertiary"
2707 };
2708 for (i = 0; i < chip->max_codecs; i++)
2709 if (tmp & chip->codec_bit[i])
2710 snd_iprintf(buffer, " %s", codecs[i]);
2711 } else
2712 snd_iprintf(buffer, " none");
2713 snd_iprintf(buffer, "\n");
2714 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2715 chip->device_type == DEVICE_SIS)
2716 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2717 chip->ac97_sdin[0],
2718 chip->ac97_sdin[1],
2719 chip->ac97_sdin[2]);
2720}
2721
2722static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2723{
2724 snd_info_entry_t *entry;
2725
2726 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2727 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2728}
2729#else
2730#define snd_intel8x0_proc_init(x)
2731#endif
2732
2733static int snd_intel8x0_dev_free(snd_device_t *device)
2734{
2735 struct intel8x0 *chip = device->device_data;
2736 return snd_intel8x0_free(chip);
2737}
2738
2739struct ich_reg_info {
2740 unsigned int int_sta_mask;
2741 unsigned int offset;
2742};
2743
2744static unsigned int ich_codec_bits[3] = {
2745 ICH_PCR, ICH_SCR, ICH_TCR
2746};
2747static unsigned int sis_codec_bits[3] = {
2748 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2749};
2750
2751static int __devinit snd_intel8x0_create(snd_card_t * card,
2752 struct pci_dev *pci,
2753 unsigned long device_type,
2754 struct intel8x0 ** r_intel8x0)
2755{
2756 struct intel8x0 *chip;
2757 int err;
2758 unsigned int i,pci_dword;
2759 unsigned int int_sta_masks;
2760 unsigned short pci_word;
2761 unsigned char pci_byte;
2762
2763 struct ichdev *ichdev;
2764#ifdef TARGET_OS2
2765 static snd_device_ops_t ops = {
2766 snd_intel8x0_dev_free,0,0,0
2767 };
2768#else
2769 static snd_device_ops_t ops = {
2770 .dev_free = snd_intel8x0_dev_free,
2771 };
2772#endif
2773 static unsigned int bdbars[] = {
2774 3, /* DEVICE_INTEL */
2775 6, /* DEVICE_INTEL_ICH4 */
2776 6, /* DEVICE_INTEL_ICH5 */
2777 3, /* DEVICE_SIS */
2778 6, /* DEVICE_ALI */
2779 4, /* DEVICE_NFORCE */
2780 };
2781 static struct ich_reg_info intel_regs[6] = {
2782 { ICH_PIINT, 0 },
2783 { ICH_POINT, 0x10 },
2784 { ICH_MCINT, 0x20 },
2785 { ICH_M2INT, 0x40 },
2786 { ICH_P2INT, 0x50 },
2787 { ICH_SPINT, 0x60 },
2788 };
2789 static struct ich_reg_info nforce_regs[4] = {
2790 { ICH_PIINT, 0 },
2791 { ICH_POINT, 0x10 },
2792 { ICH_MCINT, 0x20 },
2793 { ICH_NVSPINT, 0x70 },
2794 };
2795 static struct ich_reg_info ali_regs[6] = {
2796 { ALI_INT_PCMIN, 0x40 },
2797 { ALI_INT_PCMOUT, 0x50 },
2798 { ALI_INT_MICIN, 0x60 },
2799 { ALI_INT_CODECSPDIFOUT, 0x70 },
2800 { ALI_INT_SPDIFIN, 0xa0 },
2801 { ALI_INT_SPDIFOUT, 0xb0 },
2802 };
2803 struct ich_reg_info *tbl;
2804
2805 *r_intel8x0 = NULL;
2806
2807 if ((err = pci_enable_device(pci)) < 0)
2808 return err;
2809 pci_set_master(pci);
2810
2811// pci_write_config_byte(pci, 0x40, 0xff); // added by vladest
2812
2813 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2814 if (chip == NULL)
2815 return -ENOMEM;
2816 spin_lock_init(&chip->reg_lock);
2817 chip->device_type = device_type;
2818 chip->card = card;
2819 chip->pci = pci;
2820 chip->irq = -1;
2821 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2822 kfree(chip);
2823 return err;
2824 }
2825 if (device_type == DEVICE_ALI) {
2826 /* ALI5455 has no ac97 region */
2827 chip->bmaddr = pci_resource_start(pci, 0);
2828 goto port_inited;
2829 }
2830 /*
2831 ¥áâì €¢  ­î ­á .  €® ᬮâà¥âì. ¥à¢®¥: pci_cfg_space 54h,
2832 €¢  ¬« €èšå ¡šâ  㪠§ë¢ îâ á®áâ®ï­š¥ 皯 . ¥á«š â ¬ 11, â®
2833 ªà®¬¥ ª®­äš£á¯¥©á  ¡®«ìè¥ ­š å७  ­¥ à ¡®â ¥â.
2834 ’〠 ­ €® § ¯šá âì 00.
2835 ‚â®à®¥: ॣšáâà PCICMD, íâ® 16-¡šâ­ë© ॣšáâà ¯® ᬥ饭šî 04h
2836 ¢ cfg_space. šâ 1 ¢ëáâ ¢šâì ¢ 1
2837 */
2838#if 1
2839 if (chip->device_type == DEVICE_INTEL_ICH5 ||
2840 chip->device_type == DEVICE_INTEL_ICH4)
2841 {
2842 pci_read_config_dword(pci, 0x40, &pci_dword);
2843 printk("acpi_base %x\n", pci_dword);
2844 pci_read_config_byte(pci, 0x44, &pci_byte);
2845 printk("acpi_cntl %i\n", pci_byte);
2846// pci_write_config_byte(pci, 0x44, pci_byte & ~(0x10));
2847 pci_read_config_word(pci, 0x54, &pci_word);
2848// pci_write_config_word(pci, 0x54, pci_word & ~(0x3));
2849
2850 pci_read_config_word(pci, PCI_COMMAND, &pci_word);
2851// pci_write_config_word(pci, PCI_COMMAND, pci_word | (PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
2852
2853 pci_read_config_byte(pci, 0x55, &pci_byte);
2854 printk("pci config at 0x55 %i\n", pci_byte);
2855
2856 pci_write_config_byte(pci, 0x55, 0x01);
2857 }
2858#endif
2859 // make sure that pci allow mmio operations
2860
2861 if (pci_resource_flags(pci, /*2*/0) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2862 chip->mmio = 1;
2863 chip->addr = pci_resource_start(pci, /*2*/0);
2864 chip->remap_addr = (unsigned long)
2865 ioremap_nocache(chip->addr, pci_resource_len(pci, /*2*/0));
2866 if (chip->remap_addr == 0) {
2867 snd_printk("AC'97 space ioremap problem\n");
2868 snd_intel8x0_free(chip);
2869 return -EIO;
2870 }
2871 printk("ioremap %x len %i remap addr: %x\n",
2872 chip->addr, pci_resource_len(pci, /*2*/0), chip->remap_addr);
2873 }
2874 else if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2875 chip->mmio = 1;
2876 chip->addr = pci_resource_start(pci, 2);
2877 chip->remap_addr = (unsigned long)
2878 ioremap_nocache(chip->addr, pci_resource_len(pci, 2));
2879 if (chip->remap_addr == 0) {
2880 snd_printk("AC'97 space ioremap problem\n");
2881 snd_intel8x0_free(chip);
2882 return -EIO;
2883 }
2884 printk("ioremap %x len %i remap addr: %x\n",
2885 chip->addr, pci_resource_len(pci, 2), chip->remap_addr);
2886 } else {
2887 chip->addr = pci_resource_start(pci, 0);
2888 }
2889
2890 if (pci_resource_flags(pci, /*3*/1) & IORESOURCE_MEM) { /* ICH4 */
2891 chip->bm_mmio = 1;
2892 chip->bmaddr = pci_resource_start(pci, /*3*/1);
2893 chip->remap_bmaddr = (unsigned long)
2894 ioremap_nocache(chip->bmaddr, pci_resource_len(pci, /*3*/1));
2895 if (chip->remap_bmaddr == 0) {
2896 snd_printk("Controller space ioremap problem\n");
2897 snd_intel8x0_free(chip);
2898 return -EIO;
2899 }
2900 printk("ioremap bm %x len %i remap addr: %x\n",
2901 chip->bmaddr, pci_resource_len(pci, /*3*/1), chip->remap_bmaddr);
2902 }
2903 else if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2904 chip->bm_mmio = 1;
2905 chip->bmaddr = pci_resource_start(pci, 3);
2906 chip->remap_bmaddr = (unsigned long)
2907 ioremap_nocache(chip->bmaddr, pci_resource_len(pci, 3));
2908 if (chip->remap_bmaddr == 0) {
2909 snd_printk("Controller space ioremap problem\n");
2910 snd_intel8x0_free(chip);
2911 return -EIO;
2912 }
2913 printk("ioremap bm %x len %i remap addr: %x\n",
2914 chip->bmaddr, pci_resource_len(pci, 3), chip->remap_bmaddr);
2915 } else {
2916 chip->bmaddr = pci_resource_start(pci, 1);
2917 }
2918
2919port_inited:
2920 chip->bdbars_count = bdbars[device_type];
2921
2922 /* initialize offsets */
2923 switch (device_type) {
2924 case DEVICE_NFORCE:
2925 tbl = nforce_regs;
2926 break;
2927 case DEVICE_ALI:
2928 tbl = ali_regs;
2929 break;
2930 default:
2931 tbl = intel_regs;
2932 break;
2933 }
2934 for (i = 0; i < chip->bdbars_count; i++) {
2935 ichdev = &chip->ichd[i];
2936 ichdev->ichd = i;
2937 ichdev->reg_offset = tbl[i].offset;
2938 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2939 if (device_type == DEVICE_SIS) {
2940 /* SiS 7012 swaps the registers */
2941 ichdev->roff_sr = ICH_REG_OFF_PICB;
2942 ichdev->roff_picb = ICH_REG_OFF_SR;
2943 } else {
2944 ichdev->roff_sr = ICH_REG_OFF_SR;
2945 ichdev->roff_picb = ICH_REG_OFF_PICB;
2946 }
2947 if (device_type == DEVICE_ALI)
2948 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2949 /* SIS7012 handles the pcm data in bytes, others are in samples */
2950 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2951 }
2952
2953 /* allocate buffer descriptor lists */
2954 /* the start of each lists must be aligned to 8 bytes */
2955 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2956 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2957 &chip->bdbars) < 0) {
2958 snd_intel8x0_free(chip);
2959 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2960 return -ENOMEM;
2961 }
2962 /* tables must be aligned to 8 bytes here, but the kernel pages
2963 are much bigger, so we don't care (on i386) */
2964
2965 int_sta_masks = 0;
2966 for (i = 0; i < chip->bdbars_count; i++) {
2967 ichdev = &chip->ichd[i];
2968 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2969 (i * ICH_MAX_FRAGS * 2);
2970 ichdev->bdbar_addr = chip->bdbars.addr +
2971 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2972 int_sta_masks |= ichdev->int_sta_mask;
2973 }
2974 chip->int_sta_reg = device_type == DEVICE_ALI ?
2975 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2976 chip->int_sta_mask = int_sta_masks;
2977
2978 /* request irq after initializaing int_sta_mask, etc */
2979 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2980 SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2981 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2982 snd_intel8x0_free(chip);
2983 return -EBUSY;
2984 }
2985 chip->irq = pci->irq;
2986 pci_set_master(pci);
2987 synchronize_irq(chip->irq);
2988
2989 switch(chip->device_type) {
2990 case DEVICE_INTEL_ICH4:
2991 case DEVICE_INTEL_ICH5:
2992 /* ICH4/5 can have three codecs */
2993 chip->max_codecs = 3;
2994 chip->codec_bit = ich_codec_bits;
2995 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2996 break;
2997 case DEVICE_SIS:
2998 /* recent SIS7012 can have three codecs */
2999 chip->max_codecs = 3;
3000 chip->codec_bit = sis_codec_bits;
3001 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3002 break;
3003 default:
3004 /* others up to two codecs */
3005 chip->max_codecs = 2;
3006 chip->codec_bit = ich_codec_bits;
3007 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3008 break;
3009 }
3010 for (i = 0; i < chip->max_codecs; i++)
3011 chip->codec_isr_bits |= chip->codec_bit[i];
3012
3013 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3014 snd_intel8x0_free(chip);
3015 return err;
3016 }
3017
3018 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3019 snd_intel8x0_free(chip);
3020 return err;
3021 }
3022
3023 *r_intel8x0 = chip;
3024 return 0;
3025}
3026
3027static struct shortname_table {
3028 unsigned int id;
3029 const char *s;
3030} shortnames[] __devinitdata = {
3031 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
3032 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
3033 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
3034 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3035 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
3036 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
3037 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
3038 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel ICH 6300ESB" },
3039 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3040 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3041 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3042 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3043 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
3044 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3045 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3046 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3047 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3048 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3049 { 0x003a, "NVidia MCP04" },
3050 { 0x746d, "AMD AMD8111" },
3051 { 0x7445, "AMD AMD768" },
3052 { 0x5455, "ALi M5455" },
3053 { 0, 0 },
3054};
3055
3056static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3057 const struct pci_device_id *pci_id)
3058{
3059 static int dev;
3060 snd_card_t *card;
3061 struct intel8x0 *chip;
3062 int err;
3063 struct shortname_table *name;
3064
3065 if (dev >= SNDRV_CARDS)
3066 return -ENODEV;
3067 if (!enable[dev]) {
3068 dev++;
3069 return -ENOENT;
3070 }
3071
3072 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3073 if (card == NULL)
3074 return -ENOMEM;
3075 switch (pci_id->driver_data) {
3076 case DEVICE_NFORCE:
3077 strcpy(card->driver, "NFORCE");
3078 break;
3079 case DEVICE_INTEL_ICH4:
3080 strcpy(card->driver, "ICH4");
3081 break;
3082 case DEVICE_INTEL_ICH5:
3083 strcpy(card->driver, "ICH5");
3084 break;
3085 default:
3086 strcpy(card->driver, "ICH");
3087 break;
3088 }
3089
3090 strcpy(card->shortname, "Intel ICH");
3091 for (name = shortnames; name->id; name++) {
3092 if (pci->device == name->id) {
3093 strcpy(card->shortname, name->s);
3094 break;
3095 }
3096 }
3097 // card->dev = &pci->dev;
3098 if (buggy_irq < 0) {
3099 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3100 * Needs to return IRQ_HANDLED for unknown irqs.
3101 */
3102 if (pci_id->driver_data == DEVICE_NFORCE)
3103 buggy_irq = 1;
3104 else
3105 buggy_irq = 0;
3106 }
3107
3108 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
3109 snd_card_free(card);
3110 printk(KERN_ERR "ICH: create error. err = %x\n",err);
3111 return err;
3112 }
3113
3114 card->private_data = chip;
3115
3116 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0){
3117 snd_card_free(card);
3118 // printk(KERN_ERR "ICH: mixer error. err = %x\n",err);
3119 return err;
3120 }
3121 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3122 snd_card_free(card);
3123 printk(KERN_ERR "ICH: pcm error. err = %x\n",err);
3124 return err;
3125 }
3126
3127 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
3128 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
3129 mpu_port[dev], 0,
3130 -1, 0, &chip->rmidi)) < 0) {
3131 printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
3132 mpu_port[dev] = 0;
3133 }
3134 } else
3135 mpu_port[dev] = 0;
3136
3137 snd_intel8x0_proc_init(chip);
3138
3139 sprintf(card->longname, "%s at 0x%lx, irq %i",
3140 card->shortname, chip->addr, chip->irq);
3141
3142 if (! ac97_clock[dev])
3143 intel8x0_measure_ac97_clock(chip);
3144
3145 if ((err = snd_card_register(card)) < 0) {
3146 snd_card_free(card);
3147 printk(KERN_ERR "ICH: card register error. err = %x\n",err);
3148 return err;
3149 }
3150 pci_set_drvdata(pci, card);
3151 dev++;
3152 return 0;
3153}
3154
3155static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3156{
3157 snd_card_free(pci_get_drvdata(pci));
3158 pci_set_drvdata(pci, NULL);
3159}
3160
3161static struct pci_driver driver = {
3162 .name = "Intel ICH",
3163 .id_table = snd_intel8x0_ids,
3164 .probe = snd_intel8x0_probe,
3165 .remove = snd_intel8x0_remove,
3166#ifdef CONFIG_PM
3167 .suspend = intel8x0_suspend,
3168 .resume = intel8x0_resume,
3169#endif
3170};
3171
3172#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3173/*
3174 * initialize joystick/midi addresses
3175 */
3176#ifdef SUPPORT_JOYSTICK
3177/* there is only one available device, so we keep it here */
3178static struct pci_dev *ich_gameport_pci;
3179static struct gameport ich_gameport = { .io = 0x200 };
3180#endif
3181
3182
3183static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
3184 const struct pci_device_id *id)
3185{
3186 u16 val;
3187 static int dev;
3188 if (dev >= SNDRV_CARDS)
3189 return -ENODEV;
3190 if (!enable[dev]) {
3191 dev++;
3192 return -ENOENT;
3193 }
3194
3195 pci_read_config_word(pci, 0xe6, &val);
3196#ifdef SUPPORT_JOYSTICK
3197 if (joystick[dev]) {
3198 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
3199 printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n", ich_gameport.io);
3200 joystick[dev] = 0;
3201 } else {
3202 ich_gameport_pci = pci;
3203 gameport_register_port(&ich_gameport);
3204 val |= 0x100;
3205 }
3206 }
3207#endif
3208#ifdef SUPPORT_MIDI
3209 if (mpu_port[dev] > 0) {
3210 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
3211 u8 b;
3212 val |= 0x20;
3213 pci_read_config_byte(pci, 0xe2, &b);
3214 if (mpu_port[dev] == 0x300)
3215 b |= 0x08;
3216 else
3217 b &= ~0x08;
3218 pci_write_config_byte(pci, 0xe2, b);
3219 }
3220 }
3221#endif
3222 pci_write_config_word(pci, 0xe6, val);
3223 return 0;
3224}
3225
3226static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
3227{
3228 u16 val;
3229#ifdef SUPPORT_JOYSTICK
3230 if (ich_gameport_pci == pci) {
3231 gameport_unregister_port(&ich_gameport);
3232 release_region(ich_gameport.io, 8);
3233 ich_gameport_pci = NULL;
3234 }
3235#endif
3236 /* disable joystick and MIDI */
3237 pci_read_config_word(pci, 0xe6, &val);
3238 val &= ~0x120;
3239 pci_write_config_word(pci, 0xe6, val);
3240}
3241
3242static struct pci_device_id snd_intel8x0_joystick_ids[] = {
3243 { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82801AA */
3244 { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82901AB */
3245 { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
3246 { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
3247 { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH3 */
3248 // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
3249 // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
3250 //Rudi: this is not a joystick !!!!
3251 // { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE */
3252 // { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE2 */
3253 { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE3 */
3254 { 0, }
3255};
3256
3257static struct pci_driver joystick_driver = {
3258 0, 0, 0,
3259 /* name: */ "Intel ICH Joystick",
3260 /* id_table: */ snd_intel8x0_joystick_ids,
3261 /* probe: */ snd_intel8x0_joystick_probe,
3262 0,0,0
3263};
3264static int have_joystick;
3265#endif
3266
3267static int __init alsa_card_intel8x0_init(void)
3268{
3269 int err = 0;
3270
3271 // printk(KERN_ERR "alsa_card_intel8x0_init\n");
3272#ifdef TARGET_OS2
3273 if (midi_port > 0) mpu_port[0] = midi_port;
3274#endif
3275
3276 if ((err = pci_module_init(&driver)) < 0) {
3277#ifdef MODULE
3278 // printk(KERN_ERR "Intel ICH soundcard not found or device busy. err = %x\n",err);
3279#endif
3280 return err;
3281 }
3282#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3283 if (pci_module_init(&joystick_driver) < 0) {
3284 snd_printdd(KERN_INFO "no joystick found\n");
3285 have_joystick = 0;
3286 } else {
3287 snd_printdd(KERN_INFO "joystick(s) found\n");
3288 have_joystick = 1;
3289 }
3290#endif
3291 return 0;
3292}
3293
3294static void __exit alsa_card_intel8x0_exit(void)
3295{
3296 pci_unregister_driver(&driver);
3297#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3298 if (have_joystick)
3299 pci_unregister_driver(&joystick_driver);
3300#endif
3301}
3302
3303module_init(alsa_card_intel8x0_init)
3304module_exit(alsa_card_intel8x0_exit)
3305
3306#ifndef MODULE
3307
3308/* format is: snd-intel8x0=enable,index,id,ac97_clock,mpu_port,joystick */
3309
3310static int __init alsa_card_intel8x0_setup(char *str)
3311{
3312 static unsigned __initdata nr_dev = 0;
3313
3314 if (nr_dev >= SNDRV_CARDS)
3315 return 0;
3316 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
3317 get_option(&str,&index[nr_dev]) == 2 &&
3318 get_id(&str,&id[nr_dev]) == 2 &&
3319 get_option(&str,&ac97_clock[nr_dev]) == 2 &&
3320 get_option(&str,&ac97_quirk[nr_dev]) == 2
3321#ifdef SUPPORT_MIDI
3322 && get_option(&str,&mpu_port[nr_dev]) == 2
3323#endif
3324#ifdef SUPPORT_JOYSTICK
3325 && get_option(&str,&joystick[nr_dev]) == 2
3326#endif
3327 );
3328 nr_dev++;
3329 return 1;
3330}
3331
3332__setup("snd-intel8x0=", alsa_card_intel8x0_setup);
3333
3334#endif /* ifndef MODULE */
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