source: GPL/trunk/alsa-kernel/pci/hda/patch_si3054.c

Last change on this file was 679, checked in by David Azarewicz, 5 years ago

Merge changes from Paul's uniaud32next branch.
File size: 8.7 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Universal Interface for Intel High Definition Audio Codec
4 *
5 * HD audio interface patch for Silicon Labs 3054/5 modem codec
6 *
7 * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
8 * Takashi Iwai <tiwai@suse.de>
9 */
10
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <sound/core.h>
16#include <sound/hda_codec.h>
17#include "hda_local.h"
18
19#ifdef TARGET_OS2
20#define KBUILD_MODNAME "patch_si3054"
21#endif
22
23/* si3054 verbs */
24#define SI3054_VERB_READ_NODE 0x900
25#define SI3054_VERB_WRITE_NODE 0x100
26
27/* si3054 nodes (registers) */
28#define SI3054_EXTENDED_MID 2
29#define SI3054_LINE_RATE 3
30#define SI3054_LINE_LEVEL 4
31#define SI3054_GPIO_CFG 5
32#define SI3054_GPIO_POLARITY 6
33#define SI3054_GPIO_STICKY 7
34#define SI3054_GPIO_WAKEUP 8
35#define SI3054_GPIO_STATUS 9
36#define SI3054_GPIO_CONTROL 10
37#define SI3054_MISC_AFE 11
38#define SI3054_CHIPID 12
39#define SI3054_LINE_CFG1 13
40#define SI3054_LINE_STATUS 14
41#define SI3054_DC_TERMINATION 15
42#define SI3054_LINE_CONFIG 16
43#define SI3054_CALLPROG_ATT 17
44#define SI3054_SQ_CONTROL 18
45#define SI3054_MISC_CONTROL 19
46#define SI3054_RING_CTRL1 20
47#define SI3054_RING_CTRL2 21
48
49/* extended MID */
50#define SI3054_MEI_READY 0xf
51
52/* line level */
53#define SI3054_ATAG_MASK 0x00f0
54#define SI3054_DTAG_MASK 0xf000
55
56/* GPIO bits */
57#define SI3054_GPIO_OH 0x0001
58#define SI3054_GPIO_CID 0x0002
59
60/* chipid and revisions */
61#define SI3054_CHIPID_CODEC_REV_MASK 0x000f
62#define SI3054_CHIPID_DAA_REV_MASK 0x00f0
63#define SI3054_CHIPID_INTERNATIONAL 0x0100
64#define SI3054_CHIPID_DAA_ID 0x0f00
65#define SI3054_CHIPID_CODEC_ID (1<<12)
66
67/* si3054 codec registers (nodes) access macros */
68#define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
69#define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
70#define SET_REG_CACHE(codec,reg,val) \
71 snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val)
72
73
74struct si3054_spec {
75 unsigned international;
76};
77
78
79/*
80 * Modem mixer
81 */
82
83#define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
84#define PRIVATE_REG(val) ((val>>16)&0xffff)
85#define PRIVATE_MASK(val) (val&0xffff)
86
87#define si3054_switch_info snd_ctl_boolean_mono_info
88
89static int si3054_switch_get(struct snd_kcontrol *kcontrol,
90 struct snd_ctl_elem_value *uvalue)
91{
92 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
93 u16 reg = PRIVATE_REG(kcontrol->private_value);
94 u16 mask = PRIVATE_MASK(kcontrol->private_value);
95 uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
96 return 0;
97}
98
99static int si3054_switch_put(struct snd_kcontrol *kcontrol,
100 struct snd_ctl_elem_value *uvalue)
101{
102 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
103 u16 reg = PRIVATE_REG(kcontrol->private_value);
104 u16 mask = PRIVATE_MASK(kcontrol->private_value);
105 if (uvalue->value.integer.value[0])
106 SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask);
107 else
108 SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask);
109 return 0;
110}
111
112#define SI3054_KCONTROL(kname,reg,mask) { \
113 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
114 .name = kname, \
115 .subdevice = HDA_SUBDEV_NID_FLAG | reg, \
116 .info = si3054_switch_info, \
117 .get = si3054_switch_get, \
118 .put = si3054_switch_put, \
119 .private_value = PRIVATE_VALUE(reg,mask), \
120}
121
122
123static const struct snd_kcontrol_new si3054_modem_mixer[] = {
124 SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
125 SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
126 {0}
127};
128
129static int si3054_build_controls(struct hda_codec *codec)
130{
131 return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
132}
133
134
135/*
136 * PCM callbacks
137 */
138
139static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
140 struct hda_codec *codec,
141 unsigned int stream_tag,
142 unsigned int format,
143 struct snd_pcm_substream *substream)
144{
145 u16 val;
146
147 SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
148 val = GET_REG(codec, SI3054_LINE_LEVEL);
149 val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
150 val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
151 SET_REG(codec, SI3054_LINE_LEVEL, val);
152
153 snd_hda_codec_setup_stream(codec, hinfo->nid,
154 stream_tag, 0, format);
155 return 0;
156}
157
158static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
159 struct hda_codec *codec,
160 struct snd_pcm_substream *substream)
161{
162 static const unsigned int rates[] = { 8000, 9600, 16000 };
163 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
164 .count = ARRAY_SIZE(rates),
165 .list = rates,
166 .mask = 0,
167 };
168 substream->runtime->hw.period_bytes_min = 80;
169 return snd_pcm_hw_constraint_list(substream->runtime, 0,
170 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
171}
172
173
174static const struct hda_pcm_stream si3054_pcm = {
175 .substreams = 1,
176 .channels_min = 1,
177 .channels_max = 1,
178 .nid = 0x1,
179 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
180 .formats = SNDRV_PCM_FMTBIT_S16_LE,
181 .maxbps = 16,
182 .ops = {
183 .open = si3054_pcm_open,
184 .prepare = si3054_pcm_prepare,
185 },
186};
187
188
189static int si3054_build_pcms(struct hda_codec *codec)
190{
191 struct hda_pcm *info;
192
193 info = snd_hda_codec_pcm_new(codec, "Si3054 Modem");
194 if (!info)
195 return -ENOMEM;
196 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
197 info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm;
198 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = codec->core.mfg;
199 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = codec->core.mfg;
200 info->pcm_type = HDA_PCM_TYPE_MODEM;
201 return 0;
202}
203
204
205/*
206 * Init part
207 */
208
209static int si3054_init(struct hda_codec *codec)
210{
211 struct si3054_spec *spec = codec->spec;
212 unsigned wait_count;
213 u16 val;
214
215 if (snd_hdac_regmap_add_vendor_verb(&codec->core,
216 SI3054_VERB_WRITE_NODE))
217 return -ENOMEM;
218
219 snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
220 snd_hda_codec_write(codec, codec->core.mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
221 SET_REG(codec, SI3054_LINE_RATE, 9600);
222 SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
223 SET_REG(codec, SI3054_EXTENDED_MID, 0);
224
225 wait_count = 10;
226 do {
227 msleep(2);
228 val = GET_REG(codec, SI3054_EXTENDED_MID);
229 } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
230
231 if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
232 codec_err(codec, "si3054: cannot initialize. EXT MID = %04x\n", val);
233 /* let's pray that this is no fatal error */
234 /* return -EACCES; */
235 }
236
237 SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
238 SET_REG(codec, SI3054_GPIO_CFG, 0x0);
239 SET_REG(codec, SI3054_MISC_AFE, 0);
240 SET_REG(codec, SI3054_LINE_CFG1,0x200);
241
242 if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
243 codec_dbg(codec,
244 "Link Frame Detect(FDT) is not ready (line status: %04x)\n",
245 GET_REG(codec,SI3054_LINE_STATUS));
246 }
247
248 spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
249
250 return 0;
251}
252
253static void si3054_free(struct hda_codec *codec)
254{
255 kfree(codec->spec);
256}
257
258
259/*
260 */
261
262static const struct hda_codec_ops si3054_patch_ops = {
263 .build_controls = si3054_build_controls,
264 .build_pcms = si3054_build_pcms,
265 .init = si3054_init,
266 .free = si3054_free,
267};
268
269static int patch_si3054(struct hda_codec *codec)
270{
271 struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
272 if (spec == NULL)
273 return -ENOMEM;
274 codec->spec = spec;
275 codec->patch_ops = si3054_patch_ops;
276 return 0;
277}
278
279/*
280 * patch entries
281 */
282static const struct hda_device_id snd_hda_id_si3054[] = {
283 HDA_CODEC_ENTRY(0x163c3055, "Si3054", patch_si3054),
284 HDA_CODEC_ENTRY(0x163c3155, "Si3054", patch_si3054),
285 HDA_CODEC_ENTRY(0x11c13026, "Si3054", patch_si3054),
286 HDA_CODEC_ENTRY(0x11c13055, "Si3054", patch_si3054),
287 HDA_CODEC_ENTRY(0x11c13155, "Si3054", patch_si3054),
288 HDA_CODEC_ENTRY(0x10573055, "Si3054", patch_si3054),
289 HDA_CODEC_ENTRY(0x10573057, "Si3054", patch_si3054),
290 HDA_CODEC_ENTRY(0x10573155, "Si3054", patch_si3054),
291 /* VIA HDA on Clevo m540 */
292 HDA_CODEC_ENTRY(0x11063288, "Si3054", patch_si3054),
293 /* Asus A8J Modem (SM56) */
294 HDA_CODEC_ENTRY(0x15433155, "Si3054", patch_si3054),
295 /* LG LW20 modem */
296 HDA_CODEC_ENTRY(0x18540018, "Si3054", patch_si3054),
297 {0}
298};
299MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_si3054);
300
301MODULE_LICENSE("GPL");
302MODULE_DESCRIPTION("Si3054 HD-audio modem codec");
303
304static struct hda_codec_driver si3054_driver = {
305 .id = snd_hda_id_si3054,
306};
307
308module_hda_codec_driver(si3054_driver);
Note: See TracBrowser for help on using the repository browser.