| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */
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| 2 | /*
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| 3 | * Common functionality for the alsa driver code base for HD Audio.
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| 4 | */
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| 5 |
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| 6 | #ifndef __SOUND_HDA_CONTROLLER_H
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| 7 | #define __SOUND_HDA_CONTROLLER_H
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| 8 |
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| 9 | #include <linux/timecounter.h>
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| 10 | #include <linux/interrupt.h>
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| 11 | #include <sound/core.h>
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| 12 | #include <sound/pcm.h>
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| 13 | #include <sound/initval.h>
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| 14 | #include <sound/hda_codec.h>
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| 15 | #include <sound/hda_register.h>
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| 16 |
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| 17 | #define AZX_MAX_CODECS HDA_MAX_CODECS
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| 18 | #define AZX_DEFAULT_CODECS 4
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| 19 |
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| 20 | /* driver quirks (capabilities) */
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| 21 | /* bits 0-7 are used for indicating driver type */
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| 22 | #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
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| 23 | #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
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| 24 | #define AZX_DCAPS_SNOOP_MASK (3 << 10) /* snoop type mask */
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| 25 | #define AZX_DCAPS_SNOOP_OFF (1 << 12) /* snoop default off */
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| 26 | #ifdef CONFIG_SND_HDA_I915
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| 27 | #define AZX_DCAPS_I915_COMPONENT (1 << 13) /* bind with i915 gfx */
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| 28 | #else
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| 29 | #define AZX_DCAPS_I915_COMPONENT 0 /* NOP */
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| 30 | #endif
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| 31 | /* 14 unused */
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| 32 | #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
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| 33 | #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
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| 34 | #define AZX_DCAPS_AMD_WORKAROUND (1 << 17) /* AMD-specific workaround */
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| 35 | #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
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| 36 | /* 19 unused */
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| 37 | #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
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| 38 | #define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21) /* no buffer size alignment */
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| 39 | /* 22 unused */
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| 40 | #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
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| 41 | /* 24 unused */
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| 42 | #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
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| 43 | #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
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| 44 | #define AZX_DCAPS_RETRY_PROBE (1 << 27) /* retry probe if no codec is configured */
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| 45 | #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
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| 46 | #define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
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| 47 | #define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */
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| 48 | #define AZX_DCAPS_PIO_COMMANDS (1 << 31) /* Use PIO instead of CORB for commands */
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| 49 |
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| 50 | enum {
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| 51 | AZX_SNOOP_TYPE_NONE,
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| 52 | AZX_SNOOP_TYPE_SCH,
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| 53 | AZX_SNOOP_TYPE_ATI,
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| 54 | AZX_SNOOP_TYPE_NVIDIA,
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| 55 | };
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| 56 |
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| 57 | struct azx_dev {
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| 58 | struct hdac_stream core;
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| 59 |
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| 60 | unsigned int irq_pending:1;
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| 61 | /*
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| 62 | * For VIA:
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| 63 | * A flag to ensure DMA position is 0
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| 64 | * when link position is not greater than FIFO size
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| 65 | */
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| 66 | unsigned int insufficient:1;
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| 67 | };
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| 68 |
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| 69 | #define azx_stream(dev) (&(dev)->core)
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| 70 | #define stream_to_azx_dev(s) container_of(s, struct azx_dev, core)
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| 71 |
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| 72 | struct azx;
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| 73 |
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| 74 | /* Functions to read/write to hda registers. */
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| 75 | struct hda_controller_ops {
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| 76 | /* Disable msi if supported, PCI only */
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| 77 | int (*disable_msi_reset_irq)(struct azx *);
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| 78 | /* Check if current position is acceptable */
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| 79 | int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
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| 80 | /* enable/disable the link power */
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| 81 | int (*link_power)(struct azx *chip, bool enable);
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| 82 | };
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| 83 |
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| 84 | struct azx_pcm {
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| 85 | struct azx *chip;
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| 86 | struct snd_pcm *pcm;
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| 87 | struct hda_codec *codec;
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| 88 | struct hda_pcm *info;
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| 89 | struct list_head list;
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| 90 | };
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| 91 |
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| 92 | typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
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| 93 | typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
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| 94 |
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| 95 | struct azx {
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| 96 | struct hda_bus bus;
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| 97 |
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| 98 | struct snd_card *card;
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| 99 | struct pci_dev *pci;
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| 100 | int dev_index;
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| 101 |
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| 102 | /* chip type specific */
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| 103 | int driver_type;
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| 104 | unsigned int driver_caps;
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| 105 | int playback_streams;
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| 106 | int playback_index_offset;
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| 107 | int capture_streams;
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| 108 | int capture_index_offset;
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| 109 | int num_streams;
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| 110 | int jackpoll_interval; /* jack poll interval in jiffies */
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| 111 |
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| 112 | /* Register interaction. */
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| 113 | const struct hda_controller_ops *ops;
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| 114 |
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| 115 | /* position adjustment callbacks */
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| 116 | azx_get_pos_callback_t get_position[2];
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| 117 | azx_get_delay_callback_t get_delay[2];
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| 118 |
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| 119 | /* locks */
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| 120 | struct mutex open_mutex; /* Prevents concurrent open/close operations */
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| 121 |
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| 122 | /* PCM */
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| 123 | struct list_head pcm_list; /* azx_pcm list */
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| 124 |
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| 125 | /* HD codec */
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| 126 | int codec_probe_mask; /* copied from probe_mask option */
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| 127 | unsigned int beep_mode;
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| 128 | bool ctl_dev_id;
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| 129 |
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| 130 | #ifdef CONFIG_SND_HDA_PATCH_LOADER
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| 131 | const struct firmware *fw;
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| 132 | #endif
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| 133 |
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| 134 | /* flags */
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| 135 | int bdl_pos_adj;
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| 136 | unsigned int running:1;
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| 137 | unsigned int fallback_to_single_cmd:1;
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| 138 | unsigned int single_cmd:1;
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| 139 | unsigned int msi:1;
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| 140 | unsigned int probing:1; /* codec probing phase */
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| 141 | unsigned int snoop:1;
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| 142 | unsigned int uc_buffer:1; /* non-cached pages for stream buffers */
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| 143 | unsigned int align_buffer_size:1;
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| 144 | unsigned int disabled:1; /* disabled by vga_switcheroo */
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| 145 | unsigned int pm_prepared:1;
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| 146 |
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| 147 | /* GTS present */
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| 148 | unsigned int gts_present:1;
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| 149 |
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| 150 | #ifdef CONFIG_SND_HDA_DSP_LOADER
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| 151 | struct azx_dev saved_azx_dev;
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| 152 | #endif
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| 153 | };
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| 154 |
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| 155 | #define azx_bus(chip) (&(chip)->bus.core)
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| 156 | #define bus_to_azx(_bus) container_of(_bus, struct azx, bus.core)
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| 157 |
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| 158 | static inline bool azx_snoop(struct azx *chip)
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| 159 | {
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| 160 | return /*!IS_ENABLED(CONFIG_X86) ||*/ chip->snoop;
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| 161 | }
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| 162 |
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| 163 | /*
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| 164 | * macros for easy use
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| 165 | */
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| 166 |
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| 167 | #define azx_writel(chip, reg, value) \
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| 168 | snd_hdac_chip_writel(azx_bus(chip), reg, value)
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| 169 | #define azx_readl(chip, reg) \
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| 170 | snd_hdac_chip_readl(azx_bus(chip), reg)
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| 171 | #define azx_writew(chip, reg, value) \
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| 172 | snd_hdac_chip_writew(azx_bus(chip), reg, value)
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| 173 | #define azx_readw(chip, reg) \
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| 174 | snd_hdac_chip_readw(azx_bus(chip), reg)
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| 175 | #define azx_writeb(chip, reg, value) \
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| 176 | snd_hdac_chip_writeb(azx_bus(chip), reg, value)
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| 177 | #define azx_readb(chip, reg) \
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| 178 | snd_hdac_chip_readb(azx_bus(chip), reg)
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| 179 |
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| 180 | #define azx_has_pm_runtime(chip) \
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| 181 | ((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME)
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| 182 |
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| 183 | /* PCM setup */
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| 184 | static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
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| 185 | {
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| 186 | return substream->runtime->private_data;
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| 187 | }
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| 188 | unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
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| 189 | unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
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| 190 | unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
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| 191 |
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| 192 | /* Stream control. */
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| 193 | void azx_stop_all_streams(struct azx *chip);
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| 194 |
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| 195 | /* Allocation functions. */
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| 196 | #define azx_alloc_stream_pages(chip) \
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| 197 | snd_hdac_bus_alloc_stream_pages(azx_bus(chip))
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| 198 | #define azx_free_stream_pages(chip) \
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| 199 | snd_hdac_bus_free_stream_pages(azx_bus(chip))
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| 200 |
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| 201 | /* Low level azx interface */
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| 202 | void azx_init_chip(struct azx *chip, bool full_reset);
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| 203 | void azx_stop_chip(struct azx *chip);
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| 204 | #define azx_enter_link_reset(chip) \
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| 205 | snd_hdac_bus_enter_link_reset(azx_bus(chip))
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| 206 | irqreturn_t azx_interrupt(int irq, void *dev_id);
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| 207 |
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| 208 | /* Codec interface */
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| 209 | int azx_bus_init(struct azx *chip, const char *model);
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| 210 | int azx_probe_codecs(struct azx *chip, unsigned int max_slots);
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| 211 | int azx_codec_configure(struct azx *chip);
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| 212 | int azx_init_streams(struct azx *chip);
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| 213 | void azx_free_streams(struct azx *chip);
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| 214 |
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| 215 | #endif /* __SOUND_HDA_CONTROLLER_H */
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